stats.txt revision 11731
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 0.000024 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 24405000 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711731Sjason@lowepower.comhost_inst_rate 38911 # Simulator instruction rate (inst/s) 811731Sjason@lowepower.comhost_op_rate 38904 # Simulator op (including micro ops) rate (op/s) 911731Sjason@lowepower.comhost_tick_rate 189891987 # Simulator tick rate (ticks/s) 1011731Sjason@lowepower.comhost_mem_usage 234100 # Number of bytes of host memory used 1111731Sjason@lowepower.comhost_seconds 0.13 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 4999 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 4999 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 1711440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 1811390Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 1911440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 30016 # Number of bytes read from this memory 2011440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory 2111440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory 2211440SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory 2311390Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory 2411440SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 469 # Number of read requests responded to by this memory 2511680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 862774022 # Total read bandwidth from this memory (bytes/s) 2611680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 367137882 # Total read bandwidth from this memory (bytes/s) 2711680SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1229911903 # Total read bandwidth from this memory (bytes/s) 2811680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 862774022 # Instruction read bandwidth from this memory (bytes/s) 2911680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 862774022 # Instruction read bandwidth from this memory (bytes/s) 3011680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 862774022 # Total bandwidth to/from this memory (bytes/s) 3111680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 367137882 # Total bandwidth to/from this memory (bytes/s) 3211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 1229911903 # Total bandwidth to/from this memory (bytes/s) 3311440SCurtis.Dunham@arm.comsystem.physmem.readReqs 469 # Number of read requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511440SCurtis.Dunham@arm.comsystem.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue 369978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711440SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM 389978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 399978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011440SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 30016 # Total read bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 429978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 439978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 449978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4510488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::0 29 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 0 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 1 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 0 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 7 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 3 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 13 # Per bank write bursts 5210488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::7 53 # Per bank write bursts 5310488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::8 59 # Per bank write bursts 5410488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::9 76 # Per bank write bursts 5510352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 43 # Per bank write bursts 5611440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 21 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 51 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 29 # Per bank write bursts 5911390Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::14 77 # Per bank write bursts 6010242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 7 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 789978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911680SCurtis.Dunham@arm.comsystem.physmem.totGap 24305500 # Total gap between requests 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611440SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 469 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see 9511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see 9611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see 9711440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see 9811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 999322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 114 # Bytes accessed per row activation 19111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 261.614035 # Bytes accessed per row activation 19211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 175.762153 # Bytes accessed per row activation 19311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 255.654479 # Bytes accessed per row activation 19411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 36 31.58% 31.58% # Bytes accessed per row activation 19511680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 34 29.82% 61.40% # Bytes accessed per row activation 19611680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 19 16.67% 78.07% # Bytes accessed per row activation 19711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 8 7.02% 85.09% # Bytes accessed per row activation 19811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 4 3.51% 88.60% # Bytes accessed per row activation 19911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 2 1.75% 90.35% # Bytes accessed per row activation 20011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # Bytes accessed per row activation 20111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation 20211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation 20311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation 20411731Sjason@lowepower.comsystem.physmem.totQLat 7577250 # Total ticks spent queuing 20511731Sjason@lowepower.comsystem.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM 20611440SCurtis.Dunham@arm.comsystem.physmem.totBusLat 2345000 # Total ticks spent in databus transfers 20711731Sjason@lowepower.comsystem.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst 2089978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911731Sjason@lowepower.comsystem.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst 21011680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s 2119978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2149978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511680SCurtis.Dunham@arm.comsystem.physmem.busUtil 9.61 # Data bus utilization in percentage 21611680SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 9.61 # Data bus utilization in percentage for reads 2179978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811680SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing 2199978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011680SCurtis.Dunham@arm.comsystem.physmem.readRowHits 352 # Number of row buffer hits during reads 2219312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211680SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads 2239312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411680SCurtis.Dunham@arm.comsystem.physmem.avgGap 51824.09 # Average gap between requests 22511680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 75.05 # Row buffer hit rate, read and write combined 22611680SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 192780 # Energy for activate commands per rank (pJ) 22711680SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 98670 # Energy for precharge commands per rank (pJ) 22811680SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011680SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 23111680SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) 23211731Sjason@lowepower.comsystem.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ) 23311680SCurtis.Dunham@arm.comsystem.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) 23411731Sjason@lowepower.comsystem.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ) 23511680SCurtis.Dunham@arm.comsystem.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 23611680SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) 23711680SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 566.830977 # Core power per rank (mW) 23811680SCurtis.Dunham@arm.comsystem.physmem_0.totalIdleTime 20709000 # Total Idle time Per DRAM Rank 23911680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states 24011680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 780000 # Time in different power states 24111680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::SREF 0 # Time in different power states 24211731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::PRE_PDN 2481250 # Time in different power states 24311680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states 24411731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT_PDN 18291500 # Time in different power states 24511680SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ) 24611680SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ) 24711680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) 24810628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24911680SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 25011680SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ) 25111680SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ) 25211680SCurtis.Dunham@arm.comsystem.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ) 25311680SCurtis.Dunham@arm.comsystem.physmem_1.prePowerDownEnergy 180480 # Energy for precharge power-down per rank (pJ) 25411680SCurtis.Dunham@arm.comsystem.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 25511680SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 16490310 # Total energy per rank (pJ) 25611680SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 675.693915 # Core power per rank (mW) 25711680SCurtis.Dunham@arm.comsystem.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank 25811680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states 25911680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 780000 # Time in different power states 26011680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::SREF 0 # Time in different power states 26111680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 470250 # Time in different power states 26211680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states 26311680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 14468500 # Time in different power states 26411680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 26511680SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 2188 # Number of BP lookups 26611680SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 1456 # Number of conditional branches predicted 26711680SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 424 # Number of conditional branches incorrect 26811606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups 26911440SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 587 # Number of BTB hits 2709481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 27111606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage 27211680SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 252 # Number of times the RAS was used to get a target. 27311440SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 27411606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. 27511440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 2 # Number of indirect target hits. 27611606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectMisses 268 # Number of indirect misses. 27711680SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 95 # Number of mispredicted indirect branches. 27810628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2798428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2808428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2818428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2828428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2838428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2848428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2856039SN/Asystem.cpu.dtb.hits 0 # DTB hits 2866039SN/Asystem.cpu.dtb.misses 0 # DTB misses 2878428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2888428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2898428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2908428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2918428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2928428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2938428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2948428SN/Asystem.cpu.itb.hits 0 # DTB hits 2958428SN/Asystem.cpu.itb.misses 0 # DTB misses 2968428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 29710488Snilay@cs.wisc.edusystem.cpu.workload.num_syscalls 7 # Number of system calls 29811680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 24405000 # Cumulative time (in ticks) in various power states 29911680SCurtis.Dunham@arm.comsystem.cpu.numCycles 48811 # number of cpu cycles simulated 3008428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3018428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 30211731Sjason@lowepower.comsystem.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss 30311680SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 13001 # Number of instructions fetch has processed 30411680SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 2188 # Number of branches that fetch encountered 30511680SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken 30611680SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked 30711680SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing 30811390Ssteve.reinhardt@amd.comsystem.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps 30911606Sandreas.sandberg@arm.comsystem.cpu.fetch.CacheLines 2050 # Number of cache lines fetched 31011606Sandreas.sandberg@arm.comsystem.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed 31111731Sjason@lowepower.comsystem.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total) 31211731Sjason@lowepower.comsystem.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total) 31311731Sjason@lowepower.comsystem.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total) 3146291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31511731Sjason@lowepower.comsystem.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total) 31611680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) 31711680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) 31811680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) 31911680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total) 32011680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total) 32111680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total) 32211680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total) 32311680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total) 3246291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3256291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3266291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 32711731Sjason@lowepower.comsystem.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total) 32811680SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle 32911680SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle 33011680SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle 33111731Sjason@lowepower.comsystem.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked 33211680SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 2768 # Number of cycles decode is running 33311680SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking 33411680SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing 33511606Sandreas.sandberg@arm.comsystem.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch 33611390Ssteve.reinhardt@amd.comsystem.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction 33711680SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode 33811440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode 33911680SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing 34011680SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle 34111731Sjason@lowepower.comsystem.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking 34211680SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst 34311680SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 2740 # Number of cycles rename is running 34411680SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking 34511680SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename 34611440SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 34711103Snilay@cs.wisc.edusystem.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 34811680SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full 34911680SCurtis.Dunham@arm.comsystem.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full 35011680SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed 35111680SCurtis.Dunham@arm.comsystem.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made 35211680SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups 3539924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 35411390Ssteve.reinhardt@amd.comsystem.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed 35511680SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing 35611440SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 13 # count of serializing insts renamed 35711440SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed 35811680SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 323 # count of insts added to the skid buffer 35911731Sjason@lowepower.comsystem.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit. 36011731Sjason@lowepower.comsystem.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. 36111440SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. 36210488Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. 36311731Sjason@lowepower.comsystem.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec) 36411680SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ 36511731Sjason@lowepower.comsystem.cpu.iq.iqInstsIssued 8118 # Number of instructions issued 36611440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued 36711731Sjason@lowepower.comsystem.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling 36811731Sjason@lowepower.comsystem.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph 36911680SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 37011731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle 37111731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle 37211731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle 3738428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 37411731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle 37511731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle 37611731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle 37711731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle 37811680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle 37911680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle 38011680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle 38111680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle 38211103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle 3838428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3848428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3858428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38611731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle 3878428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 38811680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available 38911680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available 39011680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available 39111680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available 39211680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available 39311680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available 39411680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available 39511687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available 39611680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available 39711687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMisc 0 0.00% 3.33% # attempts to use FU when none available 39811680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available 39911680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available 40011680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available 40111680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available 40211680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available 40311680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available 40411680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available 40511680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available 40611680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available 40711680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available 40811680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available 40911680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available 41011680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available 41111680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available 41211680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available 41311680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available 41411680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available 41511680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available 41611680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available 41711680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available 41811680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available 41911680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 117 65.00% 68.33% # attempts to use FU when none available 42011680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 57 31.67% 100.00% # attempts to use FU when none available 42111687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 42211687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 4238428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4248428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4258241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 42611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued 42711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued 42811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued 42911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued 43011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued 43111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued 43211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued 43311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued 43411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued 43511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued 43611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued 43711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued 43811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued 43911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued 44011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued 44111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued 44211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued 44311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued 44411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued 44511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued 44611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued 44711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued 44811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued 44911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued 45011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued 45111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued 45211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued 45311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued 45411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued 45511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued 45611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued 45711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued 45811680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued 45911687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 46011687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 4618241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4628241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 46311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::total 8118 # Type of FU issued 46411731Sjason@lowepower.comsystem.cpu.iq.rate 0.166315 # Inst issue rate 46511680SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 180 # FU busy when requested 46611731Sjason@lowepower.comsystem.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst) 46711731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads 46811731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes 46911731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses 4708428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 4718428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 4728428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 47311731Sjason@lowepower.comsystem.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses 4748428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 47511440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores 4768428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 47711731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed 47811440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 47910242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 48011731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed 4818428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4828428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4838428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 48411440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 4858428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 48611680SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing 48711731Sjason@lowepower.comsystem.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking 48811680SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking 48911731Sjason@lowepower.comsystem.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ 49011680SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch 49111731Sjason@lowepower.comsystem.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions 49211731Sjason@lowepower.comsystem.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions 49311680SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions 49410352Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 49511680SCurtis.Dunham@arm.comsystem.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall 49610242Ssteve.reinhardt@amd.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 49711440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 49811680SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly 49911680SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute 50011731Sjason@lowepower.comsystem.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions 50111731Sjason@lowepower.comsystem.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed 50211731Sjason@lowepower.comsystem.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute 5038428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 50411731Sjason@lowepower.comsystem.cpu.iew.exec_nop 1596 # number of nop insts executed 50511731Sjason@lowepower.comsystem.cpu.iew.exec_refs 3178 # number of memory reference insts executed 50611731Sjason@lowepower.comsystem.cpu.iew.exec_branches 1363 # Number of branches executed 50711440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 1049 # Number of stores executed 50811731Sjason@lowepower.comsystem.cpu.iew.exec_rate 0.159595 # Inst execution rate 50911731Sjason@lowepower.comsystem.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit 51011731Sjason@lowepower.comsystem.cpu.iew.wb_count 7339 # cumulative count of insts written-back 51111680SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 2867 # num instructions producing a value 51211731Sjason@lowepower.comsystem.cpu.iew.wb_consumers 4274 # num instructions consuming a value 51311731Sjason@lowepower.comsystem.cpu.iew.wb_rate 0.150355 # insts written-back per cycle 51411731Sjason@lowepower.comsystem.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back 51511731Sjason@lowepower.comsystem.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit 51610488Snilay@cs.wisc.edusystem.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 51711680SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted 51811680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle 51911680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle 52011680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle 5218428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 52211680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle 52311680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle 52411680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 521 3.65% 94.50% # Number of insts commited each cycle 52511680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle 52611680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle 52711680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle 52811680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 63 0.44% 99.00% # Number of insts commited each cycle 52911680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 41 0.29% 99.29% # Number of insts commited each cycle 53011680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Number of insts commited each cycle 5318428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5328428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5338428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 53411680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 14293 # Number of insts commited each cycle 53511390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedInsts 5640 # Number of instructions committed 53611390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed 5378428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 53811390Ssteve.reinhardt@amd.comsystem.cpu.commit.refs 2036 # Number of memory references committed 53911390Ssteve.reinhardt@amd.comsystem.cpu.commit.loads 1135 # Number of loads committed 5408428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 54111390Ssteve.reinhardt@amd.comsystem.cpu.commit.branches 886 # Number of branches committed 5428428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 54311390Ssteve.reinhardt@amd.comsystem.cpu.commit.int_insts 4955 # Number of committed integer instructions. 54410488Snilay@cs.wisc.edusystem.cpu.commit.function_calls 85 # Number of function calls committed. 54511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::No_OpClass 641 11.37% 11.37% # Class of committed instruction 54611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntAlu 2959 52.46% 63.83% # Class of committed instruction 54711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntMult 2 0.04% 63.87% # Class of committed instruction 54811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.87% # Class of committed instruction 54911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Class of committed instruction 55011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction 55111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction 55211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction 55311687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.90% # Class of committed instruction 55411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction 55511687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.90% # Class of committed instruction 55611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction 55711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction 55811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction 55911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.90% # Class of committed instruction 56011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.90% # Class of committed instruction 56111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.90% # Class of committed instruction 56211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.90% # Class of committed instruction 56311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.90% # Class of committed instruction 56411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.90% # Class of committed instruction 56511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.90% # Class of committed instruction 56611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.90% # Class of committed instruction 56711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.90% # Class of committed instruction 56811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.90% # Class of committed instruction 56911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.90% # Class of committed instruction 57011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.90% # Class of committed instruction 57111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.90% # Class of committed instruction 57211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.90% # Class of committed instruction 57311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.90% # Class of committed instruction 57411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction 57511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction 57611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction 57711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction 57811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction 57911687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 58011687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 58110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 58210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 58311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::total 5640 # Class of committed instruction 58411680SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached 58511731Sjason@lowepower.comsystem.cpu.rob.rob_reads 24800 # The number of ROB reads 58611731Sjason@lowepower.comsystem.cpu.rob.rob_writes 22133 # The number of ROB writes 58711606Sandreas.sandberg@arm.comsystem.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself 58811731Sjason@lowepower.comsystem.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling 58911390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 4999 # Number of Instructions Simulated 59011390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated 59111680SCurtis.Dunham@arm.comsystem.cpu.cpi 9.764153 # CPI: Cycles Per Instruction 59211680SCurtis.Dunham@arm.comsystem.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads 59311680SCurtis.Dunham@arm.comsystem.cpu.ipc 0.102415 # IPC: Instructions Per Cycle 59411680SCurtis.Dunham@arm.comsystem.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads 59511731Sjason@lowepower.comsystem.cpu.int_regfile_reads 10560 # number of integer regfile reads 59611680SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 5141 # number of integer regfile writes 5978428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 5988428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 59911680SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_reads 161 # number of misc regfile reads 60011680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 60110628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 60211731Sjason@lowepower.comsystem.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use 60311731Sjason@lowepower.comsystem.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 60411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. 60511731Sjason@lowepower.comsystem.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. 60610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 60711731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor 60811680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy 60911680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy 61011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id 61111680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 61211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id 61311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id 61411731Sjason@lowepower.comsystem.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses 61511731Sjason@lowepower.comsystem.cpu.dcache.tags.data_accesses 5952 # Number of data accesses 61611680SCurtis.Dunham@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 61711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits 61811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits 61911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits 62011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits 62111731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 62211731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 62311731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 62411731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::total 2395 # number of overall hits 62511440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 62611440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses 62711680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses 62811680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 344 # number of WriteReq misses 62911680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses 63011680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses 63111680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses 63211680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 511 # number of overall misses 63311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 12709500 # number of ReadReq miss cycles 63411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::total 12709500 # number of ReadReq miss cycles 63511680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles 63611680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles 63711731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::cpu.data 46928999 # number of demand (read+write) miss cycles 63811731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles 63911731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles 64011731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles 64111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses) 64211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses) 64310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 64410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 64511731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses 64611731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses 64711731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses 64811731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses 64911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses 65011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses 65111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses 65211680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses 65311731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses 65411731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses 65511731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses 65611731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses 65711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency 65811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency 65911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency 66011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency 66111731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency 66211731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::total 91837.571429 # average overall miss latency 66311731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency 66411731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::total 91837.571429 # average overall miss latency 66511680SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked 66610628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 66711103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 66810628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 66911680SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked 67010628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 67111440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 67211440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 67311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 294 # number of WriteReq MSHR hits 67411680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 294 # number of WriteReq MSHR hits 67511680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 371 # number of demand (read+write) MSHR hits 67611680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 371 # number of demand (read+write) MSHR hits 67711680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 371 # number of overall MSHR hits 67811680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 371 # number of overall MSHR hits 67911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 68011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 68110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 68210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 68311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 68411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses 68511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 68611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses 68711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8094500 # number of ReadReq MSHR miss cycles 68811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 8094500 # number of ReadReq MSHR miss cycles 68911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles 69011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles 69111731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 # number of demand (read+write) MSHR miss cycles 69211731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles 69311731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles 69411731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles 69511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses 69611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses 69710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 69810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 69911731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses 70011731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses 70111731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses 70211731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses 70311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency 70411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency 70511680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency 70611680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency 70711731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency 70811731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency 70911731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency 71011731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency 71111680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 7129838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 17 # number of replacements 71311680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use 71411680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. 71511440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. 71611680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks. 7179838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 71811680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor 71911680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.078181 # Average percentage of cache occupancy 72011680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.078181 # Average percentage of cache occupancy 72111440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id 72211680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 72311680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id 72411440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id 72511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses 72611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.data_accesses 4432 # Number of data accesses 72711680SCurtis.Dunham@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 72811680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits 72911680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits 73011680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits 73111680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits 73211680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits 73311680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 1613 # number of overall hits 73411680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses 73511680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses 73611680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses 73711680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses 73811680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses 73911680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 437 # number of overall misses 74011680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 35529000 # number of ReadReq miss cycles 74111680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 35529000 # number of ReadReq miss cycles 74211680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 35529000 # number of demand (read+write) miss cycles 74311680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 35529000 # number of demand (read+write) miss cycles 74411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 35529000 # number of overall miss cycles 74511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 35529000 # number of overall miss cycles 74611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) 74711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) 74811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses 74911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses 75011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses 75111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses 75211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213171 # miss rate for ReadReq accesses 75311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.213171 # miss rate for ReadReq accesses 75411680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.213171 # miss rate for demand accesses 75511680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.213171 # miss rate for demand accesses 75611680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.213171 # miss rate for overall accesses 75711680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.213171 # miss rate for overall accesses 75811680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497 # average ReadReq miss latency 75911680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497 # average ReadReq miss latency 76011680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency 76111680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 81302.059497 # average overall miss latency 76211680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency 76311680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 81302.059497 # average overall miss latency 76410488Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7658428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76610488Snilay@cs.wisc.edusystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7678428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 76810488Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7698983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77011201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 17 # number of writebacks 77111201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 17 # number of writebacks 77211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits 77311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits 77411680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits 77511680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits 77611680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits 77711680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits 77811440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses 77911440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses 78011440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses 78111440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses 78211440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses 78311440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses 78411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles 78511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles 78611731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles 78711731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles 78811731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles 78911731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles 79011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses 79111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses 79211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses 79311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses 79411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses 79511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses 79611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency 79711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency 79811731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency 79911731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency 80011731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency 80111731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency 80211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 8039838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 80411731Sjason@lowepower.comsystem.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use 80510892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 80611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. 80711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. 8089838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 80911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor 81011731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor 81111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy 81211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy 81311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy 81411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id 81511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 81611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id 81711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id 81811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses 81911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses 82011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 82111201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits 82211201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits 82310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 82410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 8259348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 8269348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 8279348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 8289348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 82910488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 83010488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 83111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 329 # number of ReadCleanReq misses 83211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 329 # number of ReadCleanReq misses 83311390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses 83411390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses 83511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses 83611390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses 83711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses 83811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses 83911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses 84011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 469 # number of overall misses 84111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles 84211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles 84311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles 84411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles 84511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles 84611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles 84711731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles 84811731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles 84911731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles 85011731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles 85111731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles 85211731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles 85311201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) 85411201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) 85510488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 85610488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 85711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses) 85811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses) 85911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses) 86011390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses) 86111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses 86211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses 86311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses 86411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses 86511390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses 86611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses 8679348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8689348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 86911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990964 # miss rate for ReadCleanReq accesses 87011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990964 # miss rate for ReadCleanReq accesses 87110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 87210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 87311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses 8749348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 87511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses 87611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses 8779348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 87811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses 87911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency 88011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency 88111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency 88211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency 88311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency 88411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency 88511731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency 88611731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency 88711731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency 88811731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency 88911731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency 89011731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency 8919348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8929348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8939348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8949348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8959348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8969348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 89710488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 89810488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 89911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses 90011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses 90111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses 90211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses 90311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses 90411390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 90511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses 90611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses 90711390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 90811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses 90911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles 91011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles 91111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles 91211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles 91311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles 91411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles 91511731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles 91611731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles 91711731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles 91811731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles 91911731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles 92011731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles 9219348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 9229348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 92311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses 92411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses 92510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 92610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 92711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses 9289348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 92911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses 93011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses 9319348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 93211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses 93311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency 93411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency 93511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency 93611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency 93711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency 93811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency 93911731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency 94011731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency 94111731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency 94211731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency 94311731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency 94411731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency 94511440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 94611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 94711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 94811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 94911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 95011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 95111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 95211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 95311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution 95410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 95510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 95611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution 95711390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution 95811440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes) 95911390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) 96011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes) 96111440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) 96211390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) 96311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes) 96410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 96511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 96611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram 96711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram 96810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 96910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 97011440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram 97111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 97210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 97310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 97411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 97511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 97611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram 97711440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) 97811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 97911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) 98011680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 98111390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) 98210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 98311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter. 98411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 98511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 98611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 98711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 98811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 98911680SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 99011440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 419 # Transaction distribution 99110628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 50 # Transaction distribution 99210628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 50 # Transaction distribution 99311440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 419 # Transaction distribution 99411441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) 99511440SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 99611441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) 99711440SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) 99810628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 99911570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 100011440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 469 # Request fanout histogram 100110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 100210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 100310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 100411440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram 100510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 100610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 100710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 100810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 100911440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 469 # Request fanout histogram 101011731Sjason@lowepower.comsystem.membus.reqLayer0.occupancy 581000 # Layer occupancy (ticks) 101111680SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 101211680SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks) 101311680SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 10.2 # Layer utilization (%) 10146039SN/A 10156039SN/A---------- End Simulation Statistics ---------- 1016