stats.txt revision 11606
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 311440SCurtis.Dunham@arm.comsim_seconds 0.000023 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 22838000 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 22838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 76246 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 76230 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 348191953 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 252304 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 0.07 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 4999 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 4999 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 1711440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 1811390Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 1911440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 30016 # Number of bytes read from this memory 2011440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory 2111440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory 2211440SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory 2311390Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory 2411440SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 469 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.inst 921972152 # Total read bandwidth from this memory (bytes/s) 2611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 392328575 # Total read bandwidth from this memory (bytes/s) 2711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 1314300727 # Total read bandwidth from this memory (bytes/s) 2811606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu.inst 921972152 # Instruction read bandwidth from this memory (bytes/s) 2911606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 921972152 # Instruction read bandwidth from this memory (bytes/s) 3011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.inst 921972152 # Total bandwidth to/from this memory (bytes/s) 3111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 392328575 # Total bandwidth to/from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 1314300727 # Total bandwidth to/from this memory (bytes/s) 3311440SCurtis.Dunham@arm.comsystem.physmem.readReqs 469 # Number of read requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511440SCurtis.Dunham@arm.comsystem.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue 369978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711440SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM 389978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 399978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011440SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 30016 # Total read bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 429978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 439978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 449978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4510488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::0 29 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 0 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 1 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 0 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 7 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 3 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 13 # Per bank write bursts 5210488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::7 53 # Per bank write bursts 5310488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::8 59 # Per bank write bursts 5410488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::9 76 # Per bank write bursts 5510352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 43 # Per bank write bursts 5611440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 21 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 51 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 29 # Per bank write bursts 5911390Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::14 77 # Per bank write bursts 6010242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 7 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 789978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911606Sandreas.sandberg@arm.comsystem.physmem.totGap 22751500 # Total gap between requests 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611440SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 469 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see 9511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see 9611440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 9711440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see 9811440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 999322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation 19111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 259.047619 # Bytes accessed per row activation 19211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 178.738362 # Bytes accessed per row activation 19311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 250.145511 # Bytes accessed per row activation 19411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation 19511606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation 19611606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation 19711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 9 8.57% 86.67% # Bytes accessed per row activation 19811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation 19911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation 20011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::768-895 2 1.90% 94.29% # Bytes accessed per row activation 20111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation 20211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation 20311606Sandreas.sandberg@arm.comsystem.physmem.totQLat 4619250 # Total ticks spent queuing 20411606Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 13413000 # Total ticks spent from burst creation until serviced by the DRAM 20511440SCurtis.Dunham@arm.comsystem.physmem.totBusLat 2345000 # Total ticks spent in databus transfers 20611606Sandreas.sandberg@arm.comsystem.physmem.avgQLat 9849.15 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20811606Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 28599.15 # Average memory access latency per DRAM burst 20911606Sandreas.sandberg@arm.comsystem.physmem.avgRdBW 1314.30 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21111606Sandreas.sandberg@arm.comsystem.physmem.avgRdBWSys 1314.30 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21411606Sandreas.sandberg@arm.comsystem.physmem.busUtil 10.27 # Data bus utilization in percentage 21511606Sandreas.sandberg@arm.comsystem.physmem.busUtilRead 10.27 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21711440SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21911440SCurtis.Dunham@arm.comsystem.physmem.readRowHits 353 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22111440SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22311606Sandreas.sandberg@arm.comsystem.physmem.avgGap 48510.66 # Average gap between requests 22411440SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined 22510726Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) 22610726Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) 22711606Sandreas.sandberg@arm.comsystem.physmem_0.readEnergy 514800 # Energy for read commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23011606Sandreas.sandberg@arm.comsystem.physmem_0.actBackEnergy 9522135 # Energy for active background per rank (pJ) 23111606Sandreas.sandberg@arm.comsystem.physmem_0.preBackEnergy 1146750 # Energy for precharge background per rank (pJ) 23211606Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 12399450 # Total energy per rank (pJ) 23311606Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 783.164377 # Core power per rank (mW) 23411606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 1868000 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23711606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::ACT 13458250 # Time in different power states 23810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23911606Sandreas.sandberg@arm.comsystem.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ) 24011606Sandreas.sandberg@arm.comsystem.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ) 24111606Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24411606Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) 24511606Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) 24611606Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 14808930 # Total energy per rank (pJ) 24711606Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 935.350071 # Core power per rank (mW) 24811606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 200750 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25111606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 15221750 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25311606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 25411606Sandreas.sandberg@arm.comsystem.cpu.branchPred.lookups 2189 # Number of BP lookups 25511606Sandreas.sandberg@arm.comsystem.cpu.branchPred.condPredicted 1457 # Number of conditional branches predicted 25611440SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect 25711606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups 25811440SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 587 # Number of BTB hits 2599481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26011606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage 26111606Sandreas.sandberg@arm.comsystem.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target. 26211440SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 26311606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. 26411440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 2 # Number of indirect target hits. 26511606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectMisses 268 # Number of indirect misses. 26611440SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches. 26710628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2688428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2698428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2708428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2718428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2728428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2738428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2746039SN/Asystem.cpu.dtb.hits 0 # DTB hits 2756039SN/Asystem.cpu.dtb.misses 0 # DTB misses 2768428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2778428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2788428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2798428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2808428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2818428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2828428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2838428SN/Asystem.cpu.itb.hits 0 # DTB hits 2848428SN/Asystem.cpu.itb.misses 0 # DTB misses 2858428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 28610488Snilay@cs.wisc.edusystem.cpu.workload.num_syscalls 7 # Number of system calls 28711606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 22838000 # Cumulative time (in ticks) in various power states 28811606Sandreas.sandberg@arm.comsystem.cpu.numCycles 45677 # number of cpu cycles simulated 2898428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2908428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29111606Sandreas.sandberg@arm.comsystem.cpu.fetch.icacheStallCycles 9081 # Number of cycles fetch is stalled on an Icache miss 29211606Sandreas.sandberg@arm.comsystem.cpu.fetch.Insts 13012 # Number of instructions fetch has processed 29311606Sandreas.sandberg@arm.comsystem.cpu.fetch.Branches 2189 # Number of branches that fetch encountered 29411606Sandreas.sandberg@arm.comsystem.cpu.fetch.predictedBranches 840 # Number of branches that fetch has predicted taken 29511606Sandreas.sandberg@arm.comsystem.cpu.fetch.Cycles 4774 # Number of cycles fetch has run and was not squashing or blocked 29611440SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing 29711390Ssteve.reinhardt@amd.comsystem.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps 29811606Sandreas.sandberg@arm.comsystem.cpu.fetch.CacheLines 2050 # Number of cache lines fetched 29911606Sandreas.sandberg@arm.comsystem.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed 30011606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) 30111606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::mean 0.897689 # Number of instructions fetched each cycle (Total) 30211606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::stdev 2.187204 # Number of instructions fetched each cycle (Total) 3036291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 30411606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::0 11134 76.81% 76.81% # Number of instructions fetched each cycle (Total) 30511606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::1 1506 10.39% 87.20% # Number of instructions fetched each cycle (Total) 30611606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::2 111 0.77% 87.97% # Number of instructions fetched each cycle (Total) 30711606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::3 162 1.12% 89.09% # Number of instructions fetched each cycle (Total) 30811606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::4 279 1.92% 91.01% # Number of instructions fetched each cycle (Total) 30911606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::5 100 0.69% 91.70% # Number of instructions fetched each cycle (Total) 31011606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::6 142 0.98% 92.68% # Number of instructions fetched each cycle (Total) 31111606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::7 158 1.09% 93.77% # Number of instructions fetched each cycle (Total) 31211606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::8 903 6.23% 100.00% # Number of instructions fetched each cycle (Total) 3136291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3146291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3156291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 31611606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) 31711606Sandreas.sandberg@arm.comsystem.cpu.fetch.branchRate 0.047923 # Number of branch fetches per cycle 31811606Sandreas.sandberg@arm.comsystem.cpu.fetch.rate 0.284870 # Number of inst fetches per cycle 31911606Sandreas.sandberg@arm.comsystem.cpu.decode.IdleCycles 8449 # Number of cycles decode is idle 32011606Sandreas.sandberg@arm.comsystem.cpu.decode.BlockedCycles 2734 # Number of cycles decode is blocked 32111606Sandreas.sandberg@arm.comsystem.cpu.decode.RunCycles 2777 # Number of cycles decode is running 32211440SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking 32311440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing 32411606Sandreas.sandberg@arm.comsystem.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch 32511390Ssteve.reinhardt@amd.comsystem.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction 32611606Sandreas.sandberg@arm.comsystem.cpu.decode.DecodedInsts 12026 # Number of instructions handled by decode 32711440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode 32811440SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing 32911606Sandreas.sandberg@arm.comsystem.cpu.rename.IdleCycles 8600 # Number of cycles rename is idle 33011606Sandreas.sandberg@arm.comsystem.cpu.rename.BlockCycles 597 # Number of cycles rename is blocking 33111606Sandreas.sandberg@arm.comsystem.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst 33211606Sandreas.sandberg@arm.comsystem.cpu.rename.RunCycles 2748 # Number of cycles rename is running 33311606Sandreas.sandberg@arm.comsystem.cpu.rename.UnblockCycles 1172 # Number of cycles rename is unblocking 33411606Sandreas.sandberg@arm.comsystem.cpu.rename.RenamedInsts 11590 # Number of instructions processed by rename 33511440SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 33611103Snilay@cs.wisc.edusystem.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 33711606Sandreas.sandberg@arm.comsystem.cpu.rename.LQFullEvents 177 # Number of times rename has blocked due to LQ full 33811606Sandreas.sandberg@arm.comsystem.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full 33911606Sandreas.sandberg@arm.comsystem.cpu.rename.RenamedOperands 6955 # Number of destination operands rename has renamed 34011606Sandreas.sandberg@arm.comsystem.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made 34111606Sandreas.sandberg@arm.comsystem.cpu.rename.int_rename_lookups 13364 # Number of integer rename lookups 3429924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 34311390Ssteve.reinhardt@amd.comsystem.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed 34411606Sandreas.sandberg@arm.comsystem.cpu.rename.UndoneMaps 3663 # Number of HB maps that are undone due to squashing 34511440SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 13 # count of serializing insts renamed 34611440SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed 34711440SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 307 # count of insts added to the skid buffer 34811606Sandreas.sandberg@arm.comsystem.cpu.memDep0.insertedLoads 2472 # Number of loads inserted to the mem dependence unit. 34911440SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. 35011440SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. 35110488Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. 35211606Sandreas.sandberg@arm.comsystem.cpu.iq.iqInstsAdded 9034 # Number of instructions added to the IQ (excludes non-spec) 35311440SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ 35411606Sandreas.sandberg@arm.comsystem.cpu.iq.iqInstsIssued 8125 # Number of instructions issued 35511440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued 35611606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedInstsExamined 4044 # Number of squashed instructions iterated over during squash; mainly for profiling 35711606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 2026 # Number of squashed operands that are examined and possibly removed from graph 35811440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed 35911606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle 36011606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.560538 # Number of insts issued each cycle 36111606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.289389 # Number of insts issued each cycle 3628428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 36311606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::0 11167 77.04% 77.04% # Number of insts issued each cycle 36411606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::1 1340 9.24% 86.28% # Number of insts issued each cycle 36511606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::2 721 4.97% 91.26% # Number of insts issued each cycle 36611606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::3 460 3.17% 94.43% # Number of insts issued each cycle 36711606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::4 343 2.37% 96.80% # Number of insts issued each cycle 36811606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::5 283 1.95% 98.75% # Number of insts issued each cycle 36911606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::6 110 0.76% 99.51% # Number of insts issued each cycle 37011606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::7 52 0.36% 99.87% # Number of insts issued each cycle 37111103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle 3728428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3738428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3748428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 37511606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle 3768428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 37711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available 37811440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available 37911440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available 38011440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available 38111440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available 38211440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available 38311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available 38411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available 38511440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available 38611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available 38711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available 38811440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available 38911440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available 39011440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available 39111440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available 39211440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available 39311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available 39411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available 39511440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available 39611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available 39711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available 39811440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available 39911440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available 40011440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available 40111440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available 40211440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available 40311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available 40411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available 40511440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available 40611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 117 64.64% 68.51% # attempts to use FU when none available 40711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # attempts to use FU when none available 4088428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4098428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4108241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 41111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IntAlu 4784 58.88% 58.88% # Type of FU issued 41211440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued 41311440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued 41411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.97% # Type of FU issued 41511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.97% # Type of FU issued 41611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.97% # Type of FU issued 41711606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.97% # Type of FU issued 41811606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.97% # Type of FU issued 41911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.97% # Type of FU issued 42011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.97% # Type of FU issued 42111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.97% # Type of FU issued 42211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.97% # Type of FU issued 42311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.97% # Type of FU issued 42411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.97% # Type of FU issued 42511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.97% # Type of FU issued 42611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.97% # Type of FU issued 42711606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.97% # Type of FU issued 42811606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.97% # Type of FU issued 42911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.97% # Type of FU issued 43011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.97% # Type of FU issued 43111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.97% # Type of FU issued 43211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.97% # Type of FU issued 43311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.97% # Type of FU issued 43411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.97% # Type of FU issued 43511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.97% # Type of FU issued 43611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.97% # Type of FU issued 43711606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.97% # Type of FU issued 43811606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.97% # Type of FU issued 43911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.97% # Type of FU issued 44011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::MemRead 2273 27.98% 86.94% # Type of FU issued 44111440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued 4428241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4438241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 44411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::total 8125 # Type of FU issued 44511606Sandreas.sandberg@arm.comsystem.cpu.iq.rate 0.177879 # Inst issue rate 44611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 181 # FU busy when requested 44711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_busy_rate 0.022277 # FU busy rate (busy events/executed inst) 44811606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_reads 30941 # Number of integer instruction queue reads 44911606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_writes 13095 # Number of integer instruction queue writes 45011606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7347 # Number of integer instruction queue wakeup accesses 4518428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 4528428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 4538428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 45411606Sandreas.sandberg@arm.comsystem.cpu.iq.int_alu_accesses 8304 # Number of integer alu accesses 4558428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 45611440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores 4578428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 45811606Sandreas.sandberg@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1337 # Number of loads squashed 45911440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 46010242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 46111440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed 4628428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4638428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4648428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 46511440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 4668428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 46711440SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing 46811606Sandreas.sandberg@arm.comsystem.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking 46911606Sandreas.sandberg@arm.comsystem.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking 47011606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispatchedInsts 10646 # Number of instructions dispatched to IQ 47111606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispSquashedInsts 156 # Number of squashed instructions skipped by dispatch 47211606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispLoadInsts 2472 # Number of dispatched load instructions 47311440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions 47411440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions 47510352Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 47611606Sandreas.sandberg@arm.comsystem.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall 47710242Ssteve.reinhardt@amd.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 47811440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 47911606Sandreas.sandberg@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 339 # Number of branches that were predicted not taken incorrectly 48011606Sandreas.sandberg@arm.comsystem.cpu.iew.branchMispredicts 440 # Number of branch mispredicts detected at execute 48111606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecutedInsts 7799 # Number of executed instructions 48211606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed 48311606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute 4848428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 48511440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 1602 # number of nop insts executed 48611606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_refs 3179 # number of memory reference insts executed 48711606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_branches 1368 # Number of branches executed 48811440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 1049 # Number of stores executed 48911606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_rate 0.170742 # Inst execution rate 49011606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_sent 7444 # cumulative count of insts sent to commit 49111606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_count 7349 # cumulative count of insts written-back 49211606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_producers 2873 # num instructions producing a value 49311440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 4285 # num instructions consuming a value 49411606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_rate 0.160891 # insts written-back per cycle 49511606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_fanout 0.670478 # average fanout of values written-back 49611606Sandreas.sandberg@arm.comsystem.cpu.commit.commitSquashedInsts 4999 # The number of squashed insts skipped by commit 49710488Snilay@cs.wisc.edusystem.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 49811440SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted 49911606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::samples 13612 # Number of insts commited each cycle 50011606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.414340 # Number of insts commited each cycle 50111606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.226502 # Number of insts commited each cycle 5028428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 50311606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::0 11422 83.91% 83.91% # Number of insts commited each cycle 50411606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::1 884 6.49% 90.41% # Number of insts commited each cycle 50511606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::2 520 3.82% 94.23% # Number of insts commited each cycle 50611606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::3 254 1.87% 96.09% # Number of insts commited each cycle 50711606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::4 161 1.18% 97.27% # Number of insts commited each cycle 50811606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::5 165 1.21% 98.49% # Number of insts commited each cycle 50911606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::6 61 0.45% 98.93% # Number of insts commited each cycle 51011606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle 51111606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::8 104 0.76% 100.00% # Number of insts commited each cycle 5128428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5138428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5148428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 51511606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::total 13612 # Number of insts commited each cycle 51611390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedInsts 5640 # Number of instructions committed 51711390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed 5188428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 51911390Ssteve.reinhardt@amd.comsystem.cpu.commit.refs 2036 # Number of memory references committed 52011390Ssteve.reinhardt@amd.comsystem.cpu.commit.loads 1135 # Number of loads committed 5218428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 52211390Ssteve.reinhardt@amd.comsystem.cpu.commit.branches 886 # Number of branches committed 5238428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 52411390Ssteve.reinhardt@amd.comsystem.cpu.commit.int_insts 4955 # Number of committed integer instructions. 52510488Snilay@cs.wisc.edusystem.cpu.commit.function_calls 85 # Number of function calls committed. 52611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::No_OpClass 641 11.37% 11.37% # Class of committed instruction 52711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntAlu 2959 52.46% 63.83% # Class of committed instruction 52811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntMult 2 0.04% 63.87% # Class of committed instruction 52911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.87% # Class of committed instruction 53011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Class of committed instruction 53111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction 53211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction 53311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction 53411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction 53511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction 53611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction 53711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction 53811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.90% # Class of committed instruction 53911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.90% # Class of committed instruction 54011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.90% # Class of committed instruction 54111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.90% # Class of committed instruction 54211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.90% # Class of committed instruction 54311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.90% # Class of committed instruction 54411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.90% # Class of committed instruction 54511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.90% # Class of committed instruction 54611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.90% # Class of committed instruction 54711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.90% # Class of committed instruction 54811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.90% # Class of committed instruction 54911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.90% # Class of committed instruction 55011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.90% # Class of committed instruction 55111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.90% # Class of committed instruction 55211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.90% # Class of committed instruction 55311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction 55411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction 55511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction 55611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction 55711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction 55810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 55910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 56011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::total 5640 # Class of committed instruction 56111440SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached 56211606Sandreas.sandberg@arm.comsystem.cpu.rob.rob_reads 24134 # The number of ROB reads 56311606Sandreas.sandberg@arm.comsystem.cpu.rob.rob_writes 22169 # The number of ROB writes 56411606Sandreas.sandberg@arm.comsystem.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself 56511606Sandreas.sandberg@arm.comsystem.cpu.idleCycles 31182 # Total number of cycles that the CPU has spent unscheduled due to idling 56611390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 4999 # Number of Instructions Simulated 56711390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated 56811606Sandreas.sandberg@arm.comsystem.cpu.cpi 9.137227 # CPI: Cycles Per Instruction 56911606Sandreas.sandberg@arm.comsystem.cpu.cpi_total 9.137227 # CPI: Total CPI of All Threads 57011606Sandreas.sandberg@arm.comsystem.cpu.ipc 0.109442 # IPC: Instructions Per Cycle 57111606Sandreas.sandberg@arm.comsystem.cpu.ipc_total 0.109442 # IPC: Total IPC of All Threads 57211606Sandreas.sandberg@arm.comsystem.cpu.int_regfile_reads 10569 # number of integer regfile reads 57311606Sandreas.sandberg@arm.comsystem.cpu.int_regfile_writes 5149 # number of integer regfile writes 5748428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 5758428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 57611390Ssteve.reinhardt@amd.comsystem.cpu.misc_regfile_reads 160 # number of misc regfile reads 57711606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 57810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 57911606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 90.737808 # Cycle average of tags in use 58011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 58111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. 58211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. 58310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 58411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 90.737808 # Average occupied blocks per requestor 58511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.022153 # Average percentage of cache occupancy 58611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.022153 # Average percentage of cache occupancy 58711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id 58811606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id 58911606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id 59011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id 59111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses 59211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.data_accesses 5954 # Number of data accesses 59311606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 59411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits 59511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits 59610726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits 59710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits 59811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 59911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 60011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 60111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::total 2395 # number of overall hits 60211440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 60311440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses 60410726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses 60510726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses 60611440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses 60711440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses 60811440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses 60911440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 512 # number of overall misses 61011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 12256500 # number of ReadReq miss cycles 61111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 12256500 # number of ReadReq miss cycles 61211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 24340499 # number of WriteReq miss cycles 61311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 24340499 # number of WriteReq miss cycles 61411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 36596999 # number of demand (read+write) miss cycles 61511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 36596999 # number of demand (read+write) miss cycles 61611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 36596999 # number of overall miss cycles 61711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 36596999 # number of overall miss cycles 61811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses) 61911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses) 62010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 62110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 62211606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses 62311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses 62411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses 62511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses 62611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses 62711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses 62810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses 62910726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses 63011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.176127 # miss rate for demand accesses 63111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.176127 # miss rate for demand accesses 63211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.176127 # miss rate for overall accesses 63311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.176127 # miss rate for overall accesses 63411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73392.215569 # average ReadReq miss latency 63511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 73392.215569 # average ReadReq miss latency 63611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70552.171014 # average WriteReq miss latency 63711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 70552.171014 # average WriteReq miss latency 63811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency 63911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 71478.513672 # average overall miss latency 64011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency 64111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 71478.513672 # average overall miss latency 64211606Sandreas.sandberg@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 600 # number of cycles access was blocked 64310628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 64411103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 64510628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 64611606Sandreas.sandberg@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked 64710628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 64811440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 64911440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 65010726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits 65110726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits 65211440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 372 # number of demand (read+write) MSHR hits 65311440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits 65411440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 372 # number of overall MSHR hits 65511440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 372 # number of overall MSHR hits 65611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 65711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 65810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 65910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 66011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 66111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses 66211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 66311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses 66411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7898000 # number of ReadReq MSHR miss cycles 66511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7898000 # number of ReadReq MSHR miss cycles 66611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4132999 # number of WriteReq MSHR miss cycles 66711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4132999 # number of WriteReq MSHR miss cycles 66811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030999 # number of demand (read+write) MSHR miss cycles 66911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 12030999 # number of demand (read+write) MSHR miss cycles 67011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030999 # number of overall MSHR miss cycles 67111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 12030999 # number of overall MSHR miss cycles 67211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses 67311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses 67410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 67510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 67611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses 67711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses 67811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses 67911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses 68011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87755.555556 # average ReadReq mshr miss latency 68111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87755.555556 # average ReadReq mshr miss latency 68211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82659.980000 # average WriteReq mshr miss latency 68311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82659.980000 # average WriteReq mshr miss latency 68411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency 68511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency 68611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency 68711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency 68811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 6899838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 17 # number of replacements 69011606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 158.952170 # Cycle average of tags in use 69111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.total_refs 1612 # Total number of references to valid blocks. 69211440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. 69311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.avg_refs 4.855422 # Average number of references to valid blocks. 6949838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 69511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 158.952170 # Average occupied blocks per requestor 69611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.077613 # Average percentage of cache occupancy 69711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::total 0.077613 # Average percentage of cache occupancy 69811440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id 69911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id 70011606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id 70111440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id 70211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses 70311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.data_accesses 4432 # Number of data accesses 70411606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 70511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1612 # number of ReadReq hits 70611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::total 1612 # number of ReadReq hits 70711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1612 # number of demand (read+write) hits 70811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::total 1612 # number of demand (read+write) hits 70911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1612 # number of overall hits 71011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::total 1612 # number of overall hits 71111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses 71211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses 71311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses 71411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses 71511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses 71611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::total 438 # number of overall misses 71711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 33275000 # number of ReadReq miss cycles 71811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 33275000 # number of ReadReq miss cycles 71911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 33275000 # number of demand (read+write) miss cycles 72011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 33275000 # number of demand (read+write) miss cycles 72111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 33275000 # number of overall miss cycles 72211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 33275000 # number of overall miss cycles 72311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) 72411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) 72511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses 72611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses 72711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses 72811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses 72911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213659 # miss rate for ReadReq accesses 73011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.213659 # miss rate for ReadReq accesses 73111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.213659 # miss rate for demand accesses 73211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_rate::total 0.213659 # miss rate for demand accesses 73311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.213659 # miss rate for overall accesses 73411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_rate::total 0.213659 # miss rate for overall accesses 73511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75970.319635 # average ReadReq miss latency 73611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 75970.319635 # average ReadReq miss latency 73711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency 73811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 75970.319635 # average overall miss latency 73911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency 74011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 75970.319635 # average overall miss latency 74110488Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7428428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 74310488Snilay@cs.wisc.edusystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7448428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 74510488Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7468983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74711201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 17 # number of writebacks 74811201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 17 # number of writebacks 74911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 106 # number of ReadReq MSHR hits 75011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits 75111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 106 # number of demand (read+write) MSHR hits 75211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_hits::total 106 # number of demand (read+write) MSHR hits 75311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 106 # number of overall MSHR hits 75411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_hits::total 106 # number of overall MSHR hits 75511440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses 75611440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses 75711440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses 75811440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses 75911440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses 76011440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses 76111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26133000 # number of ReadReq MSHR miss cycles 76211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 26133000 # number of ReadReq MSHR miss cycles 76311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 26133000 # number of demand (read+write) MSHR miss cycles 76411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 26133000 # number of demand (read+write) MSHR miss cycles 76511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 26133000 # number of overall MSHR miss cycles 76611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 26133000 # number of overall MSHR miss cycles 76711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses 76811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses 76911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses 77011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses 77111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses 77211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses 77311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78713.855422 # average ReadReq mshr miss latency 77411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78713.855422 # average ReadReq mshr miss latency 77511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency 77611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency 77711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency 77811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency 77911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 7809838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 78111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 251.694203 # Cycle average of tags in use 78210892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 78311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. 78411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. 7859838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 78611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 160.892029 # Average occupied blocks per requestor 78711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 90.802174 # Average occupied blocks per requestor 78811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004910 # Average percentage of cache occupancy 78911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.002771 # Average percentage of cache occupancy 79011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.007681 # Average percentage of cache occupancy 79111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id 79211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 79311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id 79411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id 79511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses 79611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses 79711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 79811201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits 79911201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits 80010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 80110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 8029348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 8039348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 8049348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 8059348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 80610488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 80710488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 80811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 329 # number of ReadCleanReq misses 80911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 329 # number of ReadCleanReq misses 81011390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses 81111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses 81211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses 81311390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses 81411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses 81511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses 81611390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses 81711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 469 # number of overall misses 81811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4057000 # number of ReadExReq miss cycles 81911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 4057000 # number of ReadExReq miss cycles 82011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25602000 # number of ReadCleanReq miss cycles 82111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 25602000 # number of ReadCleanReq miss cycles 82211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7760000 # number of ReadSharedReq miss cycles 82311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 7760000 # number of ReadSharedReq miss cycles 82411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 25602000 # number of demand (read+write) miss cycles 82511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 11817000 # number of demand (read+write) miss cycles 82611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::total 37419000 # number of demand (read+write) miss cycles 82711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 25602000 # number of overall miss cycles 82811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 11817000 # number of overall miss cycles 82911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::total 37419000 # number of overall miss cycles 83011201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) 83111201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) 83210488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 83310488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 83411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses) 83511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses) 83611390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses) 83711390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses) 83811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses 83911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses 84011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses 84111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses 84211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses 84311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses 8449348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8459348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 84611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990964 # miss rate for ReadCleanReq accesses 84711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990964 # miss rate for ReadCleanReq accesses 84810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 84910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 85011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses 8519348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 85211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses 85311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses 8549348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 85511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses 85611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81140 # average ReadExReq miss latency 85711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 81140 # average ReadExReq miss latency 85811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77817.629179 # average ReadCleanReq miss latency 85911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77817.629179 # average ReadCleanReq miss latency 86011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86222.222222 # average ReadSharedReq miss latency 86111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86222.222222 # average ReadSharedReq miss latency 86211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency 86311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency 86411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 79784.648188 # average overall miss latency 86511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency 86611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency 86711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 79784.648188 # average overall miss latency 8689348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8699348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8709348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8719348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8729348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8739348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87410488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 87510488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 87611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses 87711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses 87811390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses 87911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses 88011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses 88111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 88211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses 88311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses 88411390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 88511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses 88611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3557000 # number of ReadExReq MSHR miss cycles 88711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3557000 # number of ReadExReq MSHR miss cycles 88811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22312000 # number of ReadCleanReq MSHR miss cycles 88911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22312000 # number of ReadCleanReq MSHR miss cycles 89011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6860000 # number of ReadSharedReq MSHR miss cycles 89111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6860000 # number of ReadSharedReq MSHR miss cycles 89211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22312000 # number of demand (read+write) MSHR miss cycles 89311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10417000 # number of demand (read+write) MSHR miss cycles 89411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 32729000 # number of demand (read+write) MSHR miss cycles 89511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22312000 # number of overall MSHR miss cycles 89611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10417000 # number of overall MSHR miss cycles 89711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 32729000 # number of overall MSHR miss cycles 8989348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 8999348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 90011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses 90111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses 90210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 90310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 90411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses 9059348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 90611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses 90711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses 9089348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 90911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses 91011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71140 # average ReadExReq mshr miss latency 91111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71140 # average ReadExReq mshr miss latency 91211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67817.629179 # average ReadCleanReq mshr miss latency 91311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67817.629179 # average ReadCleanReq mshr miss latency 91411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76222.222222 # average ReadSharedReq mshr miss latency 91511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76222.222222 # average ReadSharedReq mshr miss latency 91611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency 91711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency 91811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency 91911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency 92011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency 92111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency 92211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 92311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 92411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 92511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 92611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 92711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 92811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 92911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 93011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution 93110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 93210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 93311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution 93411390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution 93511440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes) 93611390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) 93711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes) 93811440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) 93911390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) 94011440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes) 94110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 94211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 94311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram 94411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram 94510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 94610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 94711440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram 94811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 94910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 95010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 95111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 95211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 95311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram 95411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) 95511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 95611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) 95710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 95811390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) 95910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 96011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter. 96111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 96211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 96311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 96411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 96511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 96611606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 96711440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 419 # Transaction distribution 96810628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 50 # Transaction distribution 96910628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 50 # Transaction distribution 97011440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 419 # Transaction distribution 97111441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) 97211440SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 97311441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) 97411440SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) 97510628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 97611570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 97711440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 469 # Request fanout histogram 97810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 97910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 98010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 98111440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram 98210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 98310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 98410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 98510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 98611440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 469 # Request fanout histogram 98711606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) 98811606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.utilization 2.5 # Layer utilization (%) 98911606Sandreas.sandberg@arm.comsystem.membus.respLayer1.occupancy 2494250 # Layer occupancy (ticks) 99011606Sandreas.sandberg@arm.comsystem.membus.respLayer1.utilization 10.9 # Layer utilization (%) 9916039SN/A 9926039SN/A---------- End Simulation Statistics ---------- 993