stats.txt revision 11530
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 311440SCurtis.Dunham@arm.comsim_seconds 0.000023 # Number of seconds simulated 411440SCurtis.Dunham@arm.comsim_ticks 22532000 # Number of ticks simulated 511440SCurtis.Dunham@arm.comfinal_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711530Sandreas.sandberg@arm.comhost_inst_rate 107418 # Simulator instruction rate (inst/s) 811530Sandreas.sandberg@arm.comhost_op_rate 107396 # Simulator op (including micro ops) rate (op/s) 911530Sandreas.sandberg@arm.comhost_tick_rate 483974405 # Simulator tick rate (ticks/s) 1011530Sandreas.sandberg@arm.comhost_mem_usage 292720 # Number of bytes of host memory used 1111502SCurtis.Dunham@arm.comhost_seconds 0.05 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 4999 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 4999 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611530Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 1711440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 1811390Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 1911440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 30016 # Number of bytes read from this memory 2011440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory 2111440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory 2211440SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory 2311390Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory 2411440SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 469 # Number of read requests responded to by this memory 2511440SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 934493165 # Total read bandwidth from this memory (bytes/s) 2611440SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 397656666 # Total read bandwidth from this memory (bytes/s) 2711440SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1332149831 # Total read bandwidth from this memory (bytes/s) 2811440SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 934493165 # Instruction read bandwidth from this memory (bytes/s) 2911440SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 934493165 # Instruction read bandwidth from this memory (bytes/s) 3011440SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 934493165 # Total bandwidth to/from this memory (bytes/s) 3111440SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 397656666 # Total bandwidth to/from this memory (bytes/s) 3211440SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 1332149831 # Total bandwidth to/from this memory (bytes/s) 3311440SCurtis.Dunham@arm.comsystem.physmem.readReqs 469 # Number of read requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511440SCurtis.Dunham@arm.comsystem.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue 369978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711440SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM 389978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 399978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011440SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 30016 # Total read bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 429978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 439978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 449978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4510488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::0 29 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 0 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 1 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 0 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 7 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 3 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 13 # Per bank write bursts 5210488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::7 53 # Per bank write bursts 5310488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::8 59 # Per bank write bursts 5410488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::9 76 # Per bank write bursts 5510352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 43 # Per bank write bursts 5611440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 21 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 51 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 29 # Per bank write bursts 5911390Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::14 77 # Per bank write bursts 6010242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 7 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 789978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911440SCurtis.Dunham@arm.comsystem.physmem.totGap 22446500 # Total gap between requests 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611440SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 469 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see 9511440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see 9611440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 9711440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see 9811440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 999322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation 19111440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 257.207547 # Bytes accessed per row activation 19211440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 176.154447 # Bytes accessed per row activation 19311440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 250.139569 # Bytes accessed per row activation 19411440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 32 30.19% 30.19% # Bytes accessed per row activation 19511440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 32 30.19% 60.38% # Bytes accessed per row activation 19611440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 19 17.92% 78.30% # Bytes accessed per row activation 19711440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 9 8.49% 86.79% # Bytes accessed per row activation 19811440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 4 3.77% 90.57% # Bytes accessed per row activation 19911440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation 20011440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 2 1.89% 94.34% # Bytes accessed per row activation 20111440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 6 5.66% 100.00% # Bytes accessed per row activation 20211440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation 20311440SCurtis.Dunham@arm.comsystem.physmem.totQLat 4611250 # Total ticks spent queuing 20411440SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 13405000 # Total ticks spent from burst creation until serviced by the DRAM 20511440SCurtis.Dunham@arm.comsystem.physmem.totBusLat 2345000 # Total ticks spent in databus transfers 20611440SCurtis.Dunham@arm.comsystem.physmem.avgQLat 9832.09 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20811440SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 28582.09 # Average memory access latency per DRAM burst 20911440SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1332.15 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21111440SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1332.15 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21411440SCurtis.Dunham@arm.comsystem.physmem.busUtil 10.41 # Data bus utilization in percentage 21511440SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 10.41 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21711440SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21911440SCurtis.Dunham@arm.comsystem.physmem.readRowHits 353 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22111440SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22311440SCurtis.Dunham@arm.comsystem.physmem.avgGap 47860.34 # Average gap between requests 22411440SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined 22510726Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) 22610726Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) 22711440SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23011440SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 9591390 # Energy for active background per rank (pJ) 23111440SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 1086000 # Energy for precharge background per rank (pJ) 23211440SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 12431355 # Total energy per rank (pJ) 23311440SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 785.179536 # Core power per rank (mW) 23411440SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 2005750 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23711440SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 13559250 # Time in different power states 23810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23911440SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 529200 # Energy for activate commands per rank (pJ) 24011440SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 288750 # Energy for precharge commands per rank (pJ) 24111440SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 2176200 # Energy for read commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24411103Snilay@cs.wisc.edusystem.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ) 24510892Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) 24611440SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 14828520 # Total energy per rank (pJ) 24711440SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 936.587399 # Core power per rank (mW) 24810892Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25111103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25311530Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 25411440SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 2183 # Number of BP lookups 25511440SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted 25611440SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect 25711440SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups 25811440SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 587 # Number of BTB hits 2599481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26011440SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 32.996065 # BTB Hit Percentage 26111440SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 250 # Number of times the RAS was used to get a target. 26211440SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 26311440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 269 # Number of indirect predictor lookups. 26411440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 2 # Number of indirect target hits. 26511440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 267 # Number of indirect misses. 26611440SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches. 26710628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2688428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2698428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2708428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2718428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2728428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2738428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2746039SN/Asystem.cpu.dtb.hits 0 # DTB hits 2756039SN/Asystem.cpu.dtb.misses 0 # DTB misses 2768428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2778428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2788428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2798428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2808428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2818428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2828428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2838428SN/Asystem.cpu.itb.hits 0 # DTB hits 2848428SN/Asystem.cpu.itb.misses 0 # DTB misses 2858428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 28610488Snilay@cs.wisc.edusystem.cpu.workload.num_syscalls 7 # Number of system calls 28711530Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 22532000 # Cumulative time (in ticks) in various power states 28811440SCurtis.Dunham@arm.comsystem.cpu.numCycles 45065 # number of cpu cycles simulated 2898428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2908428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29111440SCurtis.Dunham@arm.comsystem.cpu.fetch.icacheStallCycles 9068 # Number of cycles fetch is stalled on an Icache miss 29211440SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 12986 # Number of instructions fetch has processed 29311440SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 2183 # Number of branches that fetch encountered 29411440SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken 29511440SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 4746 # Number of cycles fetch has run and was not squashing or blocked 29611440SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing 29711390Ssteve.reinhardt@amd.comsystem.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps 29811440SCurtis.Dunham@arm.comsystem.cpu.fetch.CacheLines 2047 # Number of cache lines fetched 29911440SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed 30011440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::samples 14454 # Number of instructions fetched each cycle (Total) 30111440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::mean 0.898436 # Number of instructions fetched each cycle (Total) 30211440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::stdev 2.187928 # Number of instructions fetched each cycle (Total) 3036291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 30411440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::0 11097 76.77% 76.77% # Number of instructions fetched each cycle (Total) 30511440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 1507 10.43% 87.20% # Number of instructions fetched each cycle (Total) 30611440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 110 0.76% 87.96% # Number of instructions fetched each cycle (Total) 30711440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 162 1.12% 89.08% # Number of instructions fetched each cycle (Total) 30811440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::4 279 1.93% 91.01% # Number of instructions fetched each cycle (Total) 30911440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::5 99 0.68% 91.70% # Number of instructions fetched each cycle (Total) 31011440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::6 140 0.97% 92.67% # Number of instructions fetched each cycle (Total) 31111440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::7 158 1.09% 93.76% # Number of instructions fetched each cycle (Total) 31211440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::8 902 6.24% 100.00% # Number of instructions fetched each cycle (Total) 3136291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3146291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3156291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 31611440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::total 14454 # Number of instructions fetched each cycle (Total) 31711440SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.048441 # Number of branch fetches per cycle 31811440SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 0.288162 # Number of inst fetches per cycle 31911440SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 8443 # Number of cycles decode is idle 32011440SCurtis.Dunham@arm.comsystem.cpu.decode.BlockedCycles 2703 # Number of cycles decode is blocked 32111440SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 2773 # Number of cycles decode is running 32211440SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking 32311440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing 32411440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 182 # Number of times decode resolved a branch 32511390Ssteve.reinhardt@amd.comsystem.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction 32611440SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 12006 # Number of instructions handled by decode 32711440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode 32811440SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing 32911440SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 8593 # Number of cycles rename is idle 33011440SCurtis.Dunham@arm.comsystem.cpu.rename.BlockCycles 592 # Number of cycles rename is blocking 33111440SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst 33211440SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 2745 # Number of cycles rename is running 33311440SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 1156 # Number of cycles rename is unblocking 33411440SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 11571 # Number of instructions processed by rename 33511440SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 33611103Snilay@cs.wisc.edusystem.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 33711440SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 175 # Number of times rename has blocked due to LQ full 33810892Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full 33911440SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed 34011440SCurtis.Dunham@arm.comsystem.cpu.rename.RenameLookups 13573 # Number of register rename lookups that rename has made 34111440SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 13340 # Number of integer rename lookups 3429924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 34311390Ssteve.reinhardt@amd.comsystem.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed 34411440SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 3648 # Number of HB maps that are undone due to squashing 34511440SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 13 # count of serializing insts renamed 34611440SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed 34711440SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 307 # count of insts added to the skid buffer 34811440SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 2471 # Number of loads inserted to the mem dependence unit. 34911440SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. 35011440SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. 35110488Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. 35211440SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsAdded 9030 # Number of instructions added to the IQ (excludes non-spec) 35311440SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ 35411440SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsIssued 8122 # Number of instructions issued 35511440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued 35611440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsExamined 4040 # Number of squashed instructions iterated over during squash; mainly for profiling 35711440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 2024 # Number of squashed operands that are examined and possibly removed from graph 35811440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed 35911440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::samples 14454 # Number of insts issued each cycle 36011440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.561921 # Number of insts issued each cycle 36111440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.290505 # Number of insts issued each cycle 3628428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 36311440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::0 11129 77.00% 77.00% # Number of insts issued each cycle 36411440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::1 1334 9.23% 86.23% # Number of insts issued each cycle 36511440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::2 725 5.02% 91.24% # Number of insts issued each cycle 36611440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::3 461 3.19% 94.43% # Number of insts issued each cycle 36711440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 340 2.35% 96.78% # Number of insts issued each cycle 36811440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 284 1.96% 98.75% # Number of insts issued each cycle 36911440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 111 0.77% 99.52% # Number of insts issued each cycle 37011440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 51 0.35% 99.87% # Number of insts issued each cycle 37111103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle 3728428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3738428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3748428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 37511440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::total 14454 # Number of insts issued each cycle 3768428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 37711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available 37811440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available 37911440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available 38011440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available 38111440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available 38211440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available 38311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available 38411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available 38511440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available 38611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available 38711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available 38811440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available 38911440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available 39011440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available 39111440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available 39211440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available 39311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available 39411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available 39511440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available 39611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available 39711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available 39811440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available 39911440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available 40011440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available 40111440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available 40211440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available 40311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available 40411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available 40511440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available 40611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 117 64.64% 68.51% # attempts to use FU when none available 40711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # attempts to use FU when none available 4088428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4098428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4108241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 41111440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntAlu 4782 58.88% 58.88% # Type of FU issued 41211440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued 41311440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued 41411440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.96% # Type of FU issued 41511440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.96% # Type of FU issued 41611440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.96% # Type of FU issued 41711440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.96% # Type of FU issued 41811440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.96% # Type of FU issued 41911440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.96% # Type of FU issued 42011440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.96% # Type of FU issued 42111440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.96% # Type of FU issued 42211440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.96% # Type of FU issued 42311440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.96% # Type of FU issued 42411440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.96% # Type of FU issued 42511440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.96% # Type of FU issued 42611440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.96% # Type of FU issued 42711440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.96% # Type of FU issued 42811440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.96% # Type of FU issued 42911440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.96% # Type of FU issued 43011440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.96% # Type of FU issued 43111440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.96% # Type of FU issued 43211440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.96% # Type of FU issued 43311440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.96% # Type of FU issued 43411440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.96% # Type of FU issued 43511440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.96% # Type of FU issued 43611440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.96% # Type of FU issued 43711440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.96% # Type of FU issued 43811440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.96% # Type of FU issued 43911440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.96% # Type of FU issued 44011440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemRead 2272 27.97% 86.94% # Type of FU issued 44111440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued 4428241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4438241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 44411440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::total 8122 # Type of FU issued 44511440SCurtis.Dunham@arm.comsystem.cpu.iq.rate 0.180229 # Inst issue rate 44611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 181 # FU busy when requested 44711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_rate 0.022285 # FU busy rate (busy events/executed inst) 44811440SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_reads 30894 # Number of integer instruction queue reads 44911440SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_writes 13087 # Number of integer instruction queue writes 45011440SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7350 # Number of integer instruction queue wakeup accesses 4518428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 4528428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 4538428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 45411440SCurtis.Dunham@arm.comsystem.cpu.iq.int_alu_accesses 8301 # Number of integer alu accesses 4558428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 45611440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores 4578428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 45811440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1336 # Number of loads squashed 45911440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 46010242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 46111440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed 4628428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4638428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4648428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 46511440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 4668428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 46711440SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing 46811440SCurtis.Dunham@arm.comsystem.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking 46911440SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking 47011440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispatchedInsts 10642 # Number of instructions dispatched to IQ 47111440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch 47211440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 2471 # Number of dispatched load instructions 47311440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions 47411440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions 47510352Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 47611440SCurtis.Dunham@arm.comsystem.cpu.iew.iewLSQFullEvents 57 # Number of times the LSQ has become full, causing a stall 47710242Ssteve.reinhardt@amd.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 47811440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 47911440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly 48011440SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute 48111440SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecutedInsts 7800 # Number of executed instructions 48211440SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 2128 # Number of load instructions executed 48311440SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute 4848428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 48511440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 1602 # number of nop insts executed 48611440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 3177 # number of memory reference insts executed 48711440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 1369 # Number of branches executed 48811440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 1049 # Number of stores executed 48911440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_rate 0.173083 # Inst execution rate 49011440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_sent 7447 # cumulative count of insts sent to commit 49111440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_count 7352 # cumulative count of insts written-back 49211440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 2874 # num instructions producing a value 49311440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 4285 # num instructions consuming a value 49411440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_rate 0.163142 # insts written-back per cycle 49511440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_fanout 0.670712 # average fanout of values written-back 49611440SCurtis.Dunham@arm.comsystem.cpu.commit.commitSquashedInsts 4995 # The number of squashed insts skipped by commit 49710488Snilay@cs.wisc.edusystem.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 49811440SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted 49911440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 13572 # Number of insts commited each cycle 50011440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.415561 # Number of insts commited each cycle 50111440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.228101 # Number of insts commited each cycle 5028428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 50311440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 11381 83.86% 83.86% # Number of insts commited each cycle 50411440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 886 6.53% 90.38% # Number of insts commited each cycle 50511440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 519 3.82% 94.21% # Number of insts commited each cycle 50611440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 254 1.87% 96.08% # Number of insts commited each cycle 50711440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 162 1.19% 97.27% # Number of insts commited each cycle 50811440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 163 1.20% 98.47% # Number of insts commited each cycle 50911440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 62 0.46% 98.93% # Number of insts commited each cycle 51011440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 41 0.30% 99.23% # Number of insts commited each cycle 51111440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 104 0.77% 100.00% # Number of insts commited each cycle 5128428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5138428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5148428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 51511440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 13572 # Number of insts commited each cycle 51611390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedInsts 5640 # Number of instructions committed 51711390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed 5188428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 51911390Ssteve.reinhardt@amd.comsystem.cpu.commit.refs 2036 # Number of memory references committed 52011390Ssteve.reinhardt@amd.comsystem.cpu.commit.loads 1135 # Number of loads committed 5218428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 52211390Ssteve.reinhardt@amd.comsystem.cpu.commit.branches 886 # Number of branches committed 5238428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 52411390Ssteve.reinhardt@amd.comsystem.cpu.commit.int_insts 4955 # Number of committed integer instructions. 52510488Snilay@cs.wisc.edusystem.cpu.commit.function_calls 85 # Number of function calls committed. 52611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::No_OpClass 641 11.37% 11.37% # Class of committed instruction 52711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntAlu 2959 52.46% 63.83% # Class of committed instruction 52811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntMult 2 0.04% 63.87% # Class of committed instruction 52911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.87% # Class of committed instruction 53011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Class of committed instruction 53111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction 53211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction 53311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction 53411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction 53511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction 53611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction 53711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction 53811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.90% # Class of committed instruction 53911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.90% # Class of committed instruction 54011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.90% # Class of committed instruction 54111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.90% # Class of committed instruction 54211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.90% # Class of committed instruction 54311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.90% # Class of committed instruction 54411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.90% # Class of committed instruction 54511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.90% # Class of committed instruction 54611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.90% # Class of committed instruction 54711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.90% # Class of committed instruction 54811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.90% # Class of committed instruction 54911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.90% # Class of committed instruction 55011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.90% # Class of committed instruction 55111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.90% # Class of committed instruction 55211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.90% # Class of committed instruction 55311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction 55411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction 55511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction 55611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction 55711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction 55810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 55910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 56011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::total 5640 # Class of committed instruction 56111440SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached 56211440SCurtis.Dunham@arm.comsystem.cpu.rob.rob_reads 24090 # The number of ROB reads 56311440SCurtis.Dunham@arm.comsystem.cpu.rob.rob_writes 22160 # The number of ROB writes 56411440SCurtis.Dunham@arm.comsystem.cpu.timesIdled 263 # Number of times that the entire CPU went into an idle state and unscheduled itself 56511440SCurtis.Dunham@arm.comsystem.cpu.idleCycles 30611 # Total number of cycles that the CPU has spent unscheduled due to idling 56611390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 4999 # Number of Instructions Simulated 56711390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated 56811440SCurtis.Dunham@arm.comsystem.cpu.cpi 9.014803 # CPI: Cycles Per Instruction 56911440SCurtis.Dunham@arm.comsystem.cpu.cpi_total 9.014803 # CPI: Total CPI of All Threads 57011440SCurtis.Dunham@arm.comsystem.cpu.ipc 0.110929 # IPC: Instructions Per Cycle 57111440SCurtis.Dunham@arm.comsystem.cpu.ipc_total 0.110929 # IPC: Total IPC of All Threads 57211440SCurtis.Dunham@arm.comsystem.cpu.int_regfile_reads 10573 # number of integer regfile reads 57311440SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 5151 # number of integer regfile writes 5748428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 5758428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 57611390Ssteve.reinhardt@amd.comsystem.cpu.misc_regfile_reads 160 # number of misc regfile reads 57711530Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 57810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 57911440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use 58011440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. 58111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. 58211440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 17.092857 # Average number of references to valid blocks. 58310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 58411440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 90.625823 # Average occupied blocks per requestor 58511440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.022125 # Average percentage of cache occupancy 58611440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.022125 # Average percentage of cache occupancy 58711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id 58811440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 58911440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id 59011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id 59111440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses 59211440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 5950 # Number of data accesses 59311530Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 59411440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits 59511440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits 59610726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits 59710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits 59811440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits 59911440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits 60011440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits 60111440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 2393 # number of overall hits 60211440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 60311440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses 60410726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses 60510726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses 60611440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses 60711440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses 60811440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses 60911440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 512 # number of overall misses 61011440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11867500 # number of ReadReq miss cycles 61111440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11867500 # number of ReadReq miss cycles 61211440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 24012499 # number of WriteReq miss cycles 61311440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 24012499 # number of WriteReq miss cycles 61411440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 35879999 # number of demand (read+write) miss cycles 61511440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 35879999 # number of demand (read+write) miss cycles 61611440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 35879999 # number of overall miss cycles 61711440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 35879999 # number of overall miss cycles 61811440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2004 # number of ReadReq accesses(hits+misses) 61911440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 2004 # number of ReadReq accesses(hits+misses) 62010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 62110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 62211440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses 62311440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses 62411440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses 62511440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses 62611440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083333 # miss rate for ReadReq accesses 62711440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.083333 # miss rate for ReadReq accesses 62810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses 62910726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses 63011440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.176248 # miss rate for demand accesses 63111440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.176248 # miss rate for demand accesses 63211440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.176248 # miss rate for overall accesses 63311440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.176248 # miss rate for overall accesses 63411440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71062.874251 # average ReadReq miss latency 63511440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 71062.874251 # average ReadReq miss latency 63611440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69601.446377 # average WriteReq miss latency 63711440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 69601.446377 # average WriteReq miss latency 63811440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency 63911440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 70078.123047 # average overall miss latency 64011440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency 64111440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 70078.123047 # average overall miss latency 64211440SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked 64310628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 64411103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 64510628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 64611440SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked 64710628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 64811440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 64911440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 65010726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits 65110726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits 65211440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 372 # number of demand (read+write) MSHR hits 65311440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits 65411440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 372 # number of overall MSHR hits 65511440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 372 # number of overall MSHR hits 65611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 65711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 65810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 65910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 66011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 66111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses 66211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 66311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses 66411440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7550000 # number of ReadReq MSHR miss cycles 66511440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7550000 # number of ReadReq MSHR miss cycles 66611440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4082999 # number of WriteReq MSHR miss cycles 66711440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4082999 # number of WriteReq MSHR miss cycles 66811440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 11632999 # number of demand (read+write) MSHR miss cycles 66911440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 11632999 # number of demand (read+write) MSHR miss cycles 67011440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 11632999 # number of overall MSHR miss cycles 67111440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 11632999 # number of overall MSHR miss cycles 67211440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044910 # mshr miss rate for ReadReq accesses 67311440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044910 # mshr miss rate for ReadReq accesses 67410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 67510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 67611440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for demand accesses 67711440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048193 # mshr miss rate for demand accesses 67811440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for overall accesses 67911440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048193 # mshr miss rate for overall accesses 68011440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency 68111440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency 68211440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency 68311440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency 68411440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 68511440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency 68611440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 68711440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency 68811530Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 6899838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 17 # number of replacements 69011440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use 69111440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. 69211440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. 69311440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks. 6949838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 69511440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor 69611440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy 69711440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.077529 # Average percentage of cache occupancy 69811440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id 69911440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 70011440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 70111440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id 70211440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses 70311440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 4426 # Number of data accesses 70411530Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 70511440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits 70611440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits 70711440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits 70811440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits 70911440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits 71011440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 1610 # number of overall hits 71111440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses 71211440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses 71311440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses 71411440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses 71511440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses 71611440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 437 # number of overall misses 71711440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 32774000 # number of ReadReq miss cycles 71811440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 32774000 # number of ReadReq miss cycles 71911440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 32774000 # number of demand (read+write) miss cycles 72011440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 32774000 # number of demand (read+write) miss cycles 72111440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 32774000 # number of overall miss cycles 72211440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 32774000 # number of overall miss cycles 72311440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2047 # number of ReadReq accesses(hits+misses) 72411440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 2047 # number of ReadReq accesses(hits+misses) 72511440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2047 # number of demand (read+write) accesses 72611440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 2047 # number of demand (read+write) accesses 72711440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2047 # number of overall (read+write) accesses 72811440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 2047 # number of overall (read+write) accesses 72911440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213483 # miss rate for ReadReq accesses 73011440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.213483 # miss rate for ReadReq accesses 73111440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.213483 # miss rate for demand accesses 73211440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.213483 # miss rate for demand accesses 73311440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.213483 # miss rate for overall accesses 73411440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.213483 # miss rate for overall accesses 73511440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74997.711670 # average ReadReq miss latency 73611440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 74997.711670 # average ReadReq miss latency 73711440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency 73811440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 74997.711670 # average overall miss latency 73911440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency 74011440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 74997.711670 # average overall miss latency 74110488Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7428428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 74310488Snilay@cs.wisc.edusystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7448428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 74510488Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7468983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74711201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 17 # number of writebacks 74811201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 17 # number of writebacks 74911440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits 75011440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits 75111440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits 75211440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits 75311440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits 75411440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits 75511440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses 75611440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses 75711440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses 75811440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses 75911440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses 76011440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses 76111440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26055500 # number of ReadReq MSHR miss cycles 76211440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 26055500 # number of ReadReq MSHR miss cycles 76311440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 26055500 # number of demand (read+write) MSHR miss cycles 76411440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 26055500 # number of demand (read+write) MSHR miss cycles 76511440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 26055500 # number of overall MSHR miss cycles 76611440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 26055500 # number of overall MSHR miss cycles 76711440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for ReadReq accesses 76811440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.162189 # mshr miss rate for ReadReq accesses 76911440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for demand accesses 77011440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.162189 # mshr miss rate for demand accesses 77111440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses 77211440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses 77311440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency 77411440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency 77511440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 77611440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency 77711440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 77811440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency 77911530Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 7809838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 78111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use 78210892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 78311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. 78411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. 7859838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 78611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor 78711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor 78811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004905 # Average percentage of cache occupancy 78911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001748 # Average percentage of cache occupancy 79011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006653 # Average percentage of cache occupancy 79111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id 79211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id 79311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id 79411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id 79511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses 79611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses 79711530Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 79811201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits 79911201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits 80010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 80110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 8029348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 8039348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 8049348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 8059348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 80610488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 80710488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 80811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 329 # number of ReadCleanReq misses 80911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 329 # number of ReadCleanReq misses 81011390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses 81111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses 81211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses 81311390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses 81411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses 81511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses 81611390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses 81711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 469 # number of overall misses 81811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007000 # number of ReadExReq miss cycles 81911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 4007000 # number of ReadExReq miss cycles 82011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25524500 # number of ReadCleanReq miss cycles 82111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 25524500 # number of ReadCleanReq miss cycles 82211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7412000 # number of ReadSharedReq miss cycles 82311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 7412000 # number of ReadSharedReq miss cycles 82411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 25524500 # number of demand (read+write) miss cycles 82511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 11419000 # number of demand (read+write) miss cycles 82611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 36943500 # number of demand (read+write) miss cycles 82711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 25524500 # number of overall miss cycles 82811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 11419000 # number of overall miss cycles 82911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 36943500 # number of overall miss cycles 83011201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) 83111201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) 83210488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 83310488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 83411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses) 83511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses) 83611390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses) 83711390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses) 83811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses 83911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses 84011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses 84111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses 84211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses 84311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses 8449348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8459348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 84611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990964 # miss rate for ReadCleanReq accesses 84711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990964 # miss rate for ReadCleanReq accesses 84810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 84910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 85011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses 8519348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 85211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses 85311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses 8549348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 85511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses 85611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80140 # average ReadExReq miss latency 85711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 80140 # average ReadExReq miss latency 85811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77582.066869 # average ReadCleanReq miss latency 85911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77582.066869 # average ReadCleanReq miss latency 86011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82355.555556 # average ReadSharedReq miss latency 86111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82355.555556 # average ReadSharedReq miss latency 86211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency 86311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency 86411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 78770.788913 # average overall miss latency 86511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency 86611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency 86711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 78770.788913 # average overall miss latency 8689348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8699348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8709348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8719348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8729348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8739348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87410488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 87510488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 87611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses 87711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses 87811390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses 87911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses 88011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses 88111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 88211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses 88311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses 88411390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 88511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses 88611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507000 # number of ReadExReq MSHR miss cycles 88711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507000 # number of ReadExReq MSHR miss cycles 88811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22234500 # number of ReadCleanReq MSHR miss cycles 88911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22234500 # number of ReadCleanReq MSHR miss cycles 89011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6512000 # number of ReadSharedReq MSHR miss cycles 89111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6512000 # number of ReadSharedReq MSHR miss cycles 89211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22234500 # number of demand (read+write) MSHR miss cycles 89311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles 89411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 32253500 # number of demand (read+write) MSHR miss cycles 89511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22234500 # number of overall MSHR miss cycles 89611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles 89711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 32253500 # number of overall MSHR miss cycles 8989348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 8999348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 90011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses 90111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses 90210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 90310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 90411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses 9059348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 90611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses 90711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses 9089348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 90911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses 91011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70140 # average ReadExReq mshr miss latency 91111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70140 # average ReadExReq mshr miss latency 91211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67582.066869 # average ReadCleanReq mshr miss latency 91311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67582.066869 # average ReadCleanReq mshr miss latency 91411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72355.555556 # average ReadSharedReq mshr miss latency 91511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72355.555556 # average ReadSharedReq mshr miss latency 91611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency 91711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency 91811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency 91911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency 92011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency 92111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency 92211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 92311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 92411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 92511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 92611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 92711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 92811530Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 92911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 93011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution 93110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 93210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 93311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution 93411390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution 93511440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes) 93611390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) 93711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes) 93811440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) 93911390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) 94011440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes) 94110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 94211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram 94311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram 94410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 94510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 94611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram 94711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 94810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 94910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 95011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 95111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 95211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram 95311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) 95411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 95511440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) 95610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 95711390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) 95810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 95911530Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states 96011440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 419 # Transaction distribution 96110628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 50 # Transaction distribution 96210628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 50 # Transaction distribution 96311440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 419 # Transaction distribution 96411441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) 96511440SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 96611441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) 96711440SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) 96810628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 96911440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 469 # Request fanout histogram 97010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 97110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 97210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 97311440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram 97410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 97510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 97610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 97710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 97811440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 469 # Request fanout histogram 97911440SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks) 98010726Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.6 # Layer utilization (%) 98111440SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 2494000 # Layer occupancy (ticks) 98211103Snilay@cs.wisc.edusystem.membus.respLayer1.utilization 11.1 # Layer utilization (%) 9836039SN/A 9846039SN/A---------- End Simulation Statistics ---------- 985