stats.txt revision 11103
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 310892Sandreas.hansson@arm.comsim_seconds 0.000022 # Number of seconds simulated 411103Snilay@cs.wisc.edusim_ticks 22451000 # Number of ticks simulated 511103Snilay@cs.wisc.edufinal_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711103Snilay@cs.wisc.eduhost_inst_rate 41665 # Simulator instruction rate (inst/s) 811103Snilay@cs.wisc.eduhost_op_rate 41658 # Simulator op (including micro ops) rate (op/s) 911103Snilay@cs.wisc.eduhost_tick_rate 187549895 # Simulator tick rate (ticks/s) 1011103Snilay@cs.wisc.eduhost_mem_usage 287968 # Number of bytes of host memory used 1111103Snilay@cs.wisc.eduhost_seconds 0.12 # Real time elapsed on the host 1210488Snilay@cs.wisc.edusim_insts 4986 # Number of instructions simulated 1310488Snilay@cs.wisc.edusim_ops 4986 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 20992 # Number of bytes read from this memory 1710488Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 1811103Snilay@cs.wisc.edusystem.physmem.bytes_read::total 30016 # Number of bytes read from this memory 1911103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 20992 # Number of instructions bytes read from this memory 2011103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 20992 # Number of instructions bytes read from this memory 2111103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory 2210488Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 2311103Snilay@cs.wisc.edusystem.physmem.num_reads::total 469 # Number of read requests responded to by this memory 2411103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 935014031 # Total read bandwidth from this memory (bytes/s) 2511103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data 401942007 # Total read bandwidth from this memory (bytes/s) 2611103Snilay@cs.wisc.edusystem.physmem.bw_read::total 1336956038 # Total read bandwidth from this memory (bytes/s) 2711103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 935014031 # Instruction read bandwidth from this memory (bytes/s) 2811103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 935014031 # Instruction read bandwidth from this memory (bytes/s) 2911103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 935014031 # Total bandwidth to/from this memory (bytes/s) 3011103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data 401942007 # Total bandwidth to/from this memory (bytes/s) 3111103Snilay@cs.wisc.edusystem.physmem.bw_total::total 1336956038 # Total bandwidth to/from this memory (bytes/s) 3211103Snilay@cs.wisc.edusystem.physmem.readReqs 469 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3411103Snilay@cs.wisc.edusystem.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3611103Snilay@cs.wisc.edusystem.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3911103Snilay@cs.wisc.edusystem.physmem.bytesReadSys 30016 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4410488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::0 29 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 0 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 1 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 0 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 7 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 3 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 13 # Per bank write bursts 5110488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::7 53 # Per bank write bursts 5210488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::8 59 # Per bank write bursts 5310488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::9 76 # Per bank write bursts 5410352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 43 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 20 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 51 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 29 # Per bank write bursts 5811103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::14 78 # Per bank write bursts 5910242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 7 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7811103Snilay@cs.wisc.edusystem.physmem.totGap 22364000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8511103Snilay@cs.wisc.edusystem.physmem.readPktSize::6 469 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9311103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see 9410726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see 9511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 9611103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 9711103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 989322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation 19011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation 19111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::gmean 180.926322 # Bytes accessed per row activation 19211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::stdev 251.694944 # Bytes accessed per row activation 19311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::0-127 29 27.88% 27.88% # Bytes accessed per row activation 19411103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::128-255 32 30.77% 58.65% # Bytes accessed per row activation 19511103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::256-383 20 19.23% 77.88% # Bytes accessed per row activation 19611103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::384-511 9 8.65% 86.54% # Bytes accessed per row activation 19711103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::512-639 4 3.85% 90.38% # Bytes accessed per row activation 19811103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation 19911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation 20011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation 20111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation 20211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation 20311103Snilay@cs.wisc.edusystem.physmem.totQLat 4505500 # Total ticks spent queuing 20411103Snilay@cs.wisc.edusystem.physmem.totMemAccLat 13299250 # Total ticks spent from burst creation until serviced by the DRAM 20511103Snilay@cs.wisc.edusystem.physmem.totBusLat 2345000 # Total ticks spent in databus transfers 20611103Snilay@cs.wisc.edusystem.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20811103Snilay@cs.wisc.edusystem.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst 20911103Snilay@cs.wisc.edusystem.physmem.avgRdBW 1336.96 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21111103Snilay@cs.wisc.edusystem.physmem.avgRdBWSys 1336.96 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21411103Snilay@cs.wisc.edusystem.physmem.busUtil 10.44 # Data bus utilization in percentage 21511103Snilay@cs.wisc.edusystem.physmem.busUtilRead 10.44 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21711103Snilay@cs.wisc.edusystem.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21911103Snilay@cs.wisc.edusystem.physmem.readRowHits 355 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22111103Snilay@cs.wisc.edusystem.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22311103Snilay@cs.wisc.edusystem.physmem.avgGap 47684.43 # Average gap between requests 22411103Snilay@cs.wisc.edusystem.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined 22510726Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) 22610726Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) 22711103Snilay@cs.wisc.edusystem.physmem_0.readEnergy 530400 # Energy for read commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23011103Snilay@cs.wisc.edusystem.physmem_0.actBackEnergy 9542655 # Energy for active background per rank (pJ) 23111103Snilay@cs.wisc.edusystem.physmem_0.preBackEnergy 1130250 # Energy for precharge background per rank (pJ) 23211103Snilay@cs.wisc.edusystem.physmem_0.totalEnergy 12419070 # Total energy per rank (pJ) 23311103Snilay@cs.wisc.edusystem.physmem_0.averagePower 784.279760 # Core power per rank (mW) 23411103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::IDLE 1840500 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23711103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::ACT 13487750 # Time in different power states 23810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23911103Snilay@cs.wisc.edusystem.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) 24011103Snilay@cs.wisc.edusystem.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) 24111103Snilay@cs.wisc.edusystem.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24411103Snilay@cs.wisc.edusystem.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ) 24510892Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) 24611103Snilay@cs.wisc.edusystem.physmem_1.totalEnergy 14797350 # Total energy per rank (pJ) 24711103Snilay@cs.wisc.edusystem.physmem_1.averagePower 934.618664 # Core power per rank (mW) 24810892Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25111103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25311103Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 2031 # Number of BP lookups 25411103Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 1362 # Number of conditional branches predicted 25511103Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 402 # Number of conditional branches incorrect 25610892Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups 25711103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 605 # Number of BTB hits 2589481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25911103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 36.867764 # BTB Hit Percentage 26011103Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 242 # Number of times the RAS was used to get a target. 26111103Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions. 26210628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2638428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2648428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2658428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2668428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2678428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2688428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2696039SN/Asystem.cpu.dtb.hits 0 # DTB hits 2706039SN/Asystem.cpu.dtb.misses 0 # DTB misses 2718428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2728428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2738428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2748428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2758428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2768428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2778428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2788428SN/Asystem.cpu.itb.hits 0 # DTB hits 2798428SN/Asystem.cpu.itb.misses 0 # DTB misses 2808428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 28110488Snilay@cs.wisc.edusystem.cpu.workload.num_syscalls 7 # Number of system calls 28211103Snilay@cs.wisc.edusystem.cpu.numCycles 44903 # number of cpu cycles simulated 2838428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2848428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 28511103Snilay@cs.wisc.edusystem.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss 28611103Snilay@cs.wisc.edusystem.cpu.fetch.Insts 12328 # Number of instructions fetch has processed 28711103Snilay@cs.wisc.edusystem.cpu.fetch.Branches 2031 # Number of branches that fetch encountered 28811103Snilay@cs.wisc.edusystem.cpu.fetch.predictedBranches 847 # Number of branches that fetch has predicted taken 28911103Snilay@cs.wisc.edusystem.cpu.fetch.Cycles 4817 # Number of cycles fetch has run and was not squashing or blocked 29011103Snilay@cs.wisc.edusystem.cpu.fetch.SquashCycles 822 # Number of cycles fetch has spent squashing 29111103Snilay@cs.wisc.edusystem.cpu.fetch.PendingTrapStallCycles 190 # Number of stall cycles due to pending traps 29211103Snilay@cs.wisc.edusystem.cpu.fetch.CacheLines 1979 # Number of cache lines fetched 29311103Snilay@cs.wisc.edusystem.cpu.fetch.IcacheSquashes 255 # Number of outstanding Icache misses that were squashed 29411103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::samples 14261 # Number of instructions fetched each cycle (Total) 29511103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::mean 0.864456 # Number of instructions fetched each cycle (Total) 29611103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::stdev 2.133927 # Number of instructions fetched each cycle (Total) 2976291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 29811103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::0 10999 77.13% 77.13% # Number of instructions fetched each cycle (Total) 29911103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::1 1480 10.38% 87.50% # Number of instructions fetched each cycle (Total) 30011103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::2 118 0.83% 88.33% # Number of instructions fetched each cycle (Total) 30111103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::3 169 1.19% 89.52% # Number of instructions fetched each cycle (Total) 30211103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::4 282 1.98% 91.49% # Number of instructions fetched each cycle (Total) 30311103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::5 102 0.72% 92.21% # Number of instructions fetched each cycle (Total) 30411103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::6 134 0.94% 93.15% # Number of instructions fetched each cycle (Total) 30511103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::7 153 1.07% 94.22% # Number of instructions fetched each cycle (Total) 30611103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::8 824 5.78% 100.00% # Number of instructions fetched each cycle (Total) 3076291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3086291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3096291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 31011103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total) 31111103Snilay@cs.wisc.edusystem.cpu.fetch.branchRate 0.045231 # Number of branch fetches per cycle 31211103Snilay@cs.wisc.edusystem.cpu.fetch.rate 0.274547 # Number of inst fetches per cycle 31311103Snilay@cs.wisc.edusystem.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle 31411103Snilay@cs.wisc.edusystem.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked 31511103Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 2707 # Number of cycles decode is running 31611103Snilay@cs.wisc.edusystem.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking 31711103Snilay@cs.wisc.edusystem.cpu.decode.SquashCycles 371 # Number of cycles decode is squashing 31811103Snilay@cs.wisc.edusystem.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch 31911103Snilay@cs.wisc.edusystem.cpu.decode.BranchMispred 41 # Number of times decode detected a branch misprediction 32011103Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 11351 # Number of instructions handled by decode 32111103Snilay@cs.wisc.edusystem.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode 32211103Snilay@cs.wisc.edusystem.cpu.rename.SquashCycles 371 # Number of cycles rename is squashing 32311103Snilay@cs.wisc.edusystem.cpu.rename.IdleCycles 8518 # Number of cycles rename is idle 32411103Snilay@cs.wisc.edusystem.cpu.rename.BlockCycles 542 # Number of cycles rename is blocking 32510892Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst 32611103Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 2675 # Number of cycles rename is running 32711103Snilay@cs.wisc.edusystem.cpu.rename.UnblockCycles 1159 # Number of cycles rename is unblocking 32811103Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 10918 # Number of instructions processed by rename 32910352Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 33011103Snilay@cs.wisc.edusystem.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 33111103Snilay@cs.wisc.edusystem.cpu.rename.LQFullEvents 179 # Number of times rename has blocked due to LQ full 33210892Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full 33311103Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 6512 # Number of destination operands rename has renamed 33411103Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 12905 # Number of register rename lookups that rename has made 33511103Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 12683 # Number of integer rename lookups 3369924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 33710488Snilay@cs.wisc.edusystem.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed 33811103Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 3230 # Number of HB maps that are undone due to squashing 33910892Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 14 # count of serializing insts renamed 34010892Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 34111103Snilay@cs.wisc.edusystem.cpu.rename.skidInsts 314 # count of insts added to the skid buffer 34211103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedLoads 2295 # Number of loads inserted to the mem dependence unit. 34311103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit. 3448428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 34510488Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. 34611103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsAdded 8632 # Number of instructions added to the IQ (excludes non-spec) 34710488Snilay@cs.wisc.edusystem.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ 34811103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsIssued 7937 # Number of instructions issued 34911103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued 35011103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsExamined 3656 # Number of squashed instructions iterated over during squash; mainly for profiling 35111103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedOperandsExamined 1608 # Number of squashed operands that are examined and possibly removed from graph 3529729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 35311103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::samples 14261 # Number of insts issued each cycle 35411103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::mean 0.556553 # Number of insts issued each cycle 35511103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::stdev 1.276985 # Number of insts issued each cycle 3568428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 35711103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::0 10981 77.00% 77.00% # Number of insts issued each cycle 35811103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::1 1321 9.26% 86.26% # Number of insts issued each cycle 35911103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::2 733 5.14% 91.40% # Number of insts issued each cycle 36011103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::3 439 3.08% 94.48% # Number of insts issued each cycle 36111103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::4 350 2.45% 96.94% # Number of insts issued each cycle 36211103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::5 277 1.94% 98.88% # Number of insts issued each cycle 36311103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::6 91 0.64% 99.52% # Number of insts issued each cycle 36411103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::7 50 0.35% 99.87% # Number of insts issued each cycle 36511103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle 3668428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3678428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3688428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 36911103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::total 14261 # Number of insts issued each cycle 3708428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 37111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntAlu 6 3.41% 3.41% # attempts to use FU when none available 37211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntMult 0 0.00% 3.41% # attempts to use FU when none available 37311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.41% # attempts to use FU when none available 37411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.41% # attempts to use FU when none available 37511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.41% # attempts to use FU when none available 37611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.41% # attempts to use FU when none available 37711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.41% # attempts to use FU when none available 37811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.41% # attempts to use FU when none available 37911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.41% # attempts to use FU when none available 38011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.41% # attempts to use FU when none available 38111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.41% # attempts to use FU when none available 38211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.41% # attempts to use FU when none available 38311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.41% # attempts to use FU when none available 38411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.41% # attempts to use FU when none available 38511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.41% # attempts to use FU when none available 38611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.41% # attempts to use FU when none available 38711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.41% # attempts to use FU when none available 38811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.41% # attempts to use FU when none available 38911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.41% # attempts to use FU when none available 39011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.41% # attempts to use FU when none available 39111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.41% # attempts to use FU when none available 39211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.41% # attempts to use FU when none available 39311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.41% # attempts to use FU when none available 39411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.41% # attempts to use FU when none available 39511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.41% # attempts to use FU when none available 39611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.41% # attempts to use FU when none available 39711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.41% # attempts to use FU when none available 39811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.41% # attempts to use FU when none available 39911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available 40011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemRead 112 63.64% 67.05% # attempts to use FU when none available 40111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemWrite 58 32.95% 100.00% # attempts to use FU when none available 4028428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4038428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4048241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 40511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntAlu 4719 59.46% 59.46% # Type of FU issued 40611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntMult 4 0.05% 59.51% # Type of FU issued 40711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntDiv 1 0.01% 59.52% # Type of FU issued 40811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.54% # Type of FU issued 40911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued 41011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued 41111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued 41211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued 41311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued 41411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued 41511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued 41611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued 41711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued 41811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued 41911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued 42011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued 42111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued 42211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued 42311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued 42411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued 42511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued 42611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued 42711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued 42811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued 42911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued 43011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued 43111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued 43211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued 43311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued 43411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemRead 2143 27.00% 86.54% # Type of FU issued 43511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Type of FU issued 4368241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4378241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 43811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::total 7937 # Type of FU issued 43911103Snilay@cs.wisc.edusystem.cpu.iq.rate 0.176759 # Inst issue rate 44011103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_cnt 176 # FU busy when requested 44111103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst) 44211103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads 44311103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_writes 12306 # Number of integer instruction queue writes 44411103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 7277 # Number of integer instruction queue wakeup accesses 4458428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 4468428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 4478428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 44811103Snilay@cs.wisc.edusystem.cpu.iq.int_alu_accesses 8111 # Number of integer alu accesses 4498428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 45011103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores 4518428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 45211103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed 45311103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 45410242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 45511103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedStores 258 # Number of stores squashed 4568428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4578428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4588428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 45911103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked 4608428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 46111103Snilay@cs.wisc.edusystem.cpu.iew.iewSquashCycles 371 # Number of cycles IEW is squashing 46211103Snilay@cs.wisc.edusystem.cpu.iew.iewBlockCycles 425 # Number of cycles IEW is blocking 46311103Snilay@cs.wisc.edusystem.cpu.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking 46411103Snilay@cs.wisc.edusystem.cpu.iew.iewDispatchedInsts 10126 # Number of instructions dispatched to IQ 46511103Snilay@cs.wisc.edusystem.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch 46611103Snilay@cs.wisc.edusystem.cpu.iew.iewDispLoadInsts 2295 # Number of dispatched load instructions 46711103Snilay@cs.wisc.edusystem.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions 46810488Snilay@cs.wisc.edusystem.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions 46910352Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 47011103Snilay@cs.wisc.edusystem.cpu.iew.iewLSQFullEvents 89 # Number of times the LSQ has become full, causing a stall 47110242Ssteve.reinhardt@amd.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 47210892Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly 47311103Snilay@cs.wisc.edusystem.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly 47411103Snilay@cs.wisc.edusystem.cpu.iew.branchMispredicts 419 # Number of branch mispredicts detected at execute 47511103Snilay@cs.wisc.edusystem.cpu.iew.iewExecutedInsts 7671 # Number of executed instructions 47611103Snilay@cs.wisc.edusystem.cpu.iew.iewExecLoadInsts 2045 # Number of load instructions executed 47711103Snilay@cs.wisc.edusystem.cpu.iew.iewExecSquashedInsts 266 # Number of squashed instructions skipped in execute 4788428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 47911103Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 1483 # number of nop insts executed 48011103Snilay@cs.wisc.edusystem.cpu.iew.exec_refs 3098 # number of memory reference insts executed 48111103Snilay@cs.wisc.edusystem.cpu.iew.exec_branches 1353 # Number of branches executed 48210892Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1053 # Number of stores executed 48311103Snilay@cs.wisc.edusystem.cpu.iew.exec_rate 0.170835 # Inst execution rate 48411103Snilay@cs.wisc.edusystem.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit 48511103Snilay@cs.wisc.edusystem.cpu.iew.wb_count 7279 # cumulative count of insts written-back 48611103Snilay@cs.wisc.edusystem.cpu.iew.wb_producers 2832 # num instructions producing a value 48711103Snilay@cs.wisc.edusystem.cpu.iew.wb_consumers 4198 # num instructions consuming a value 4888428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 48911103Snilay@cs.wisc.edusystem.cpu.iew.wb_rate 0.162105 # insts written-back per cycle 49011103Snilay@cs.wisc.edusystem.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back 4918428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 49211103Snilay@cs.wisc.edusystem.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit 49310488Snilay@cs.wisc.edusystem.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 49411103Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 362 # The number of times a branch was mispredicted 49511103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::samples 13468 # Number of insts commited each cycle 49611103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::mean 0.417508 # Number of insts commited each cycle 49711103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::stdev 1.246465 # Number of insts commited each cycle 4988428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 49911103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::0 11324 84.08% 84.08% # Number of insts commited each cycle 50011103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::1 857 6.36% 90.44% # Number of insts commited each cycle 50111103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::2 503 3.73% 94.18% # Number of insts commited each cycle 50211103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::3 247 1.83% 96.01% # Number of insts commited each cycle 50311103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::4 153 1.14% 97.15% # Number of insts commited each cycle 50411103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::5 168 1.25% 98.40% # Number of insts commited each cycle 50511103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::6 61 0.45% 98.85% # Number of insts commited each cycle 50611103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::7 39 0.29% 99.14% # Number of insts commited each cycle 50711103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::8 116 0.86% 100.00% # Number of insts commited each cycle 5088428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5098428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5108428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 51111103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::total 13468 # Number of insts commited each cycle 51210488Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 5623 # Number of instructions committed 51310488Snilay@cs.wisc.edusystem.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed 5148428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 51510488Snilay@cs.wisc.edusystem.cpu.commit.refs 2033 # Number of memory references committed 51610488Snilay@cs.wisc.edusystem.cpu.commit.loads 1132 # Number of loads committed 5178428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 51810488Snilay@cs.wisc.edusystem.cpu.commit.branches 883 # Number of branches committed 5198428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 52010488Snilay@cs.wisc.edusystem.cpu.commit.int_insts 4942 # Number of committed integer instructions. 52110488Snilay@cs.wisc.edusystem.cpu.commit.function_calls 85 # Number of function calls committed. 52210488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction 52310488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction 52410488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction 52510488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction 52610488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction 52710488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction 52810488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction 52910488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction 53010488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction 53110488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction 53210488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction 53310488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction 53410488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction 53510488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction 53610488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction 53710488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction 53810488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction 53910488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction 54010488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction 54110488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction 54210488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction 54310488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction 54410488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction 54510488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction 54610488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction 54710488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction 54810488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction 54910488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction 55010488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction 55110488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction 55210488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction 55310488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction 55410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 55510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 55610488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 5623 # Class of committed instruction 55711103Snilay@cs.wisc.edusystem.cpu.commit.bw_lim_events 116 # number cycles where commit BW limit reached 55811103Snilay@cs.wisc.edusystem.cpu.rob.rob_reads 23467 # The number of ROB reads 55911103Snilay@cs.wisc.edusystem.cpu.rob.rob_writes 21056 # The number of ROB writes 56011103Snilay@cs.wisc.edusystem.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself 56111103Snilay@cs.wisc.edusystem.cpu.idleCycles 30642 # Total number of cycles that the CPU has spent unscheduled due to idling 56210488Snilay@cs.wisc.edusystem.cpu.committedInsts 4986 # Number of Instructions Simulated 56310488Snilay@cs.wisc.edusystem.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated 56411103Snilay@cs.wisc.edusystem.cpu.cpi 9.005816 # CPI: Cycles Per Instruction 56511103Snilay@cs.wisc.edusystem.cpu.cpi_total 9.005816 # CPI: Total CPI of All Threads 56611103Snilay@cs.wisc.edusystem.cpu.ipc 0.111039 # IPC: Instructions Per Cycle 56711103Snilay@cs.wisc.edusystem.cpu.ipc_total 0.111039 # IPC: Total IPC of All Threads 56811103Snilay@cs.wisc.edusystem.cpu.int_regfile_reads 10418 # number of integer regfile reads 56911103Snilay@cs.wisc.edusystem.cpu.int_regfile_writes 5064 # number of integer regfile writes 5708428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 5718428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 57211103Snilay@cs.wisc.edusystem.cpu.misc_regfile_reads 158 # number of misc regfile reads 57310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 57411103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tagsinuse 90.670819 # Cycle average of tags in use 57511103Snilay@cs.wisc.edusystem.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks. 57610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 57711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks. 57810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 57911103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_blocks::cpu.data 90.670819 # Average occupied blocks per requestor 58011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_percent::cpu.data 0.022136 # Average percentage of cache occupancy 58111103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_percent::total 0.022136 # Average percentage of cache occupancy 58210628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 58311103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 58411103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id 58510628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 58611103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tag_accesses 5765 # Number of tag accesses 58711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.data_accesses 5765 # Number of data accesses 58811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1746 # number of ReadReq hits 58911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1746 # number of ReadReq hits 59010726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits 59110726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits 59211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 2302 # number of demand (read+write) hits 59311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 2302 # number of demand (read+write) hits 59411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 2302 # number of overall hits 59511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 2302 # number of overall hits 59611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses 59711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses 59810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses 59910726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses 60011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses 60111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses 60211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses 60311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 510 # number of overall misses 60411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11734000 # number of ReadReq miss cycles 60511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 11734000 # number of ReadReq miss cycles 60611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 24014999 # number of WriteReq miss cycles 60711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 24014999 # number of WriteReq miss cycles 60811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 35748999 # number of demand (read+write) miss cycles 60911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 35748999 # number of demand (read+write) miss cycles 61011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 35748999 # number of overall miss cycles 61111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 35748999 # number of overall miss cycles 61211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1911 # number of ReadReq accesses(hits+misses) 61311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1911 # number of ReadReq accesses(hits+misses) 61410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 61510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 61611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2812 # number of demand (read+write) accesses 61711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2812 # number of demand (read+write) accesses 61811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2812 # number of overall (read+write) accesses 61911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2812 # number of overall (read+write) accesses 62011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086342 # miss rate for ReadReq accesses 62111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.086342 # miss rate for ReadReq accesses 62210726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses 62310726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses 62411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.181366 # miss rate for demand accesses 62511103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.181366 # miss rate for demand accesses 62611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.181366 # miss rate for overall accesses 62711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.181366 # miss rate for overall accesses 62811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71115.151515 # average ReadReq miss latency 62911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 71115.151515 # average ReadReq miss latency 63011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754 # average WriteReq miss latency 63111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754 # average WriteReq miss latency 63211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency 63311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 70096.076471 # average overall miss latency 63411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency 63511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 70096.076471 # average overall miss latency 63611103Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 587 # number of cycles access was blocked 63710628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 63811103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 63910628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 64011103Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 58.700000 # average number of cycles each access was blocked 64110628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 64210628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 64310628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 64411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits 64511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 64610726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits 64710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits 64811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits 64911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits 65011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits 65111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits 65210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 65310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 65410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 65510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 65610628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 65710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 65810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 65910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 66011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7594500 # number of ReadReq MSHR miss cycles 66111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7594500 # number of ReadReq MSHR miss cycles 66211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4083499 # number of WriteReq MSHR miss cycles 66311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4083499 # number of WriteReq MSHR miss cycles 66411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 11677999 # number of demand (read+write) MSHR miss cycles 66511103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 11677999 # number of demand (read+write) MSHR miss cycles 66611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 11677999 # number of overall MSHR miss cycles 66711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 11677999 # number of overall MSHR miss cycles 66811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047619 # mshr miss rate for ReadReq accesses 66911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047619 # mshr miss rate for ReadReq accesses 67010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 67110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 67211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for demand accesses 67311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.050142 # mshr miss rate for demand accesses 67411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for overall accesses 67511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.050142 # mshr miss rate for overall accesses 67611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83456.043956 # average ReadReq mshr miss latency 67711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83456.043956 # average ReadReq mshr miss latency 67811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81669.980000 # average WriteReq mshr miss latency 67911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81669.980000 # average WriteReq mshr miss latency 68011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency 68111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency 68211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency 68311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency 68410628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 6859838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 17 # number of replacements 68611103Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 156.398029 # Cycle average of tags in use 68711103Snilay@cs.wisc.edusystem.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks. 68811103Snilay@cs.wisc.edusystem.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks. 68911103Snilay@cs.wisc.edusystem.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks. 6909838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 69111103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 156.398029 # Average occupied blocks per requestor 69211103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.076366 # Average percentage of cache occupancy 69311103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.076366 # Average percentage of cache occupancy 69411103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id 69511103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id 69611103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id 69711103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id 69811103Snilay@cs.wisc.edusystem.cpu.icache.tags.tag_accesses 4289 # Number of tag accesses 69911103Snilay@cs.wisc.edusystem.cpu.icache.tags.data_accesses 4289 # Number of data accesses 70011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 1547 # number of ReadReq hits 70111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 1547 # number of ReadReq hits 70211103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 1547 # number of demand (read+write) hits 70311103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 1547 # number of demand (read+write) hits 70411103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 1547 # number of overall hits 70511103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 1547 # number of overall hits 70611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses 70711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses 70811103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses 70911103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses 71011103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses 71111103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 432 # number of overall misses 71211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::cpu.inst 32419500 # number of ReadReq miss cycles 71311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::total 32419500 # number of ReadReq miss cycles 71411103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::cpu.inst 32419500 # number of demand (read+write) miss cycles 71511103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::total 32419500 # number of demand (read+write) miss cycles 71611103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::cpu.inst 32419500 # number of overall miss cycles 71711103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::total 32419500 # number of overall miss cycles 71811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses) 71911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses) 72011103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses 72111103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses 72211103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses 72311103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses 72411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218292 # miss rate for ReadReq accesses 72511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.218292 # miss rate for ReadReq accesses 72611103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.218292 # miss rate for demand accesses 72711103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses 72811103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses 72911103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses 73011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75045.138889 # average ReadReq miss latency 73111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 75045.138889 # average ReadReq miss latency 73211103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency 73311103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::total 75045.138889 # average overall miss latency 73411103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency 73511103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::total 75045.138889 # average overall miss latency 73610488Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7378428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 73810488Snilay@cs.wisc.edusystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7398428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 74010488Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7418983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7428428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 7438428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 74411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits 74511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits 74611103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits 74711103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits 74811103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits 74911103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits 75011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 331 # number of ReadReq MSHR misses 75111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses 75211103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 331 # number of demand (read+write) MSHR misses 75311103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses 75411103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses 75511103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses 75611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25901500 # number of ReadReq MSHR miss cycles 75711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 25901500 # number of ReadReq MSHR miss cycles 75811103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 25901500 # number of demand (read+write) MSHR miss cycles 75911103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::total 25901500 # number of demand (read+write) MSHR miss cycles 76011103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 25901500 # number of overall MSHR miss cycles 76111103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::total 25901500 # number of overall MSHR miss cycles 76211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses 76311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses 76411103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses 76511103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses 76611103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses 76711103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses 76811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78252.265861 # average ReadReq mshr miss latency 76911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78252.265861 # average ReadReq mshr miss latency 77011103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency 77111103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency 77211103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency 77311103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency 7748428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7759838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 77611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tagsinuse 215.838012 # Cycle average of tags in use 77710892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 77811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. 77911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. 7809838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 78111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.inst 158.321641 # Average occupied blocks per requestor 78211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.data 57.516370 # Average occupied blocks per requestor 78311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy 78411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy 78511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy 78611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id 78710892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 78811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id 78911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id 79011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses 79111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses 79210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 79310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 7949348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 7959348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 7969348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 7979348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 79810488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 79910488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 80011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 328 # number of ReadCleanReq misses 80111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::total 328 # number of ReadCleanReq misses 80210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 91 # number of ReadSharedReq misses 80310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 91 # number of ReadSharedReq misses 80411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 328 # number of demand (read+write) misses 80510488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 80611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses 80711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 328 # number of overall misses 80810488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 80911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::total 469 # number of overall misses 81011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles 81111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles 81211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25373500 # number of ReadCleanReq miss cycles 81311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::total 25373500 # number of ReadCleanReq miss cycles 81411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles 81511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles 81611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.inst 25373500 # number of demand (read+write) miss cycles 81711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles 81811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::total 36836000 # number of demand (read+write) miss cycles 81911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.inst 25373500 # number of overall miss cycles 82011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles 82111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::total 36836000 # number of overall miss cycles 82210488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 82310488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 82411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses) 82511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::total 331 # number of ReadCleanReq accesses(hits+misses) 82610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 91 # number of ReadSharedReq accesses(hits+misses) 82710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 91 # number of ReadSharedReq accesses(hits+misses) 82811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.inst 331 # number of demand (read+write) accesses 82910488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 83011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses 83111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.inst 331 # number of overall (read+write) accesses 83210488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 83311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses 8349348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8359348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 83611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990937 # miss rate for ReadCleanReq accesses 83711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990937 # miss rate for ReadCleanReq accesses 83810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 83910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 84011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.990937 # miss rate for demand accesses 8419348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 84211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses 84311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.990937 # miss rate for overall accesses 8449348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 84511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses 84611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency 84711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency 84811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77358.231707 # average ReadCleanReq miss latency 84911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77358.231707 # average ReadCleanReq miss latency 85011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency 85111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency 85211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency 85311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency 85411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::total 78541.577825 # average overall miss latency 85511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency 85611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency 85711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::total 78541.577825 # average overall miss latency 8589348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8599348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8609348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8619348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8629348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8639348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8649348SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8659348SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 86610488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 86710488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 86811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 328 # number of ReadCleanReq MSHR misses 86911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 328 # number of ReadCleanReq MSHR misses 87010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 91 # number of ReadSharedReq MSHR misses 87110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 91 # number of ReadSharedReq MSHR misses 87211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.inst 328 # number of demand (read+write) MSHR misses 87310488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 87411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses 87511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.inst 328 # number of overall MSHR misses 87610488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 87711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses 87811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles 87911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles 88011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22093500 # number of ReadCleanReq MSHR miss cycles 88111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22093500 # number of ReadCleanReq MSHR miss cycles 88211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles 88311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles 88411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22093500 # number of demand (read+write) MSHR miss cycles 88511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles 88611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::total 32146000 # number of demand (read+write) MSHR miss cycles 88711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22093500 # number of overall MSHR miss cycles 88811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles 88911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::total 32146000 # number of overall MSHR miss cycles 8909348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 8919348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 89211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses 89311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990937 # mshr miss rate for ReadCleanReq accesses 89410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 89510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 89611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for demand accesses 8979348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 89811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses 89911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for overall accesses 9009348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 90111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses 90211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency 90311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency 90411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67358.231707 # average ReadCleanReq mshr miss latency 90511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67358.231707 # average ReadCleanReq mshr miss latency 90611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency 90711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency 90811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency 90911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency 91011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency 91111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency 91211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency 91311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency 9149348SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 91511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 91610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution 91710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 91810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 91911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution 92010892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 91 # Transaction distribution 92111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes) 92210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 92311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes) 92411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21184 # Cumulative packet size per connected master and slave (bytes) 92510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 92611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) 92710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 92811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram 92910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 93010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 93110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 93210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 93311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::1 489 100.00% 100.00% # Request fanout histogram 93410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 93510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 93610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 93710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 93811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram 93911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 94010892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 94111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks) 94210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 94310892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 94410892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 94511103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadResp 419 # Transaction distribution 94610628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 50 # Transaction distribution 94710628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 50 # Transaction distribution 94811103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadSharedReq 419 # Transaction distribution 94911103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) 95011103Snilay@cs.wisc.edusystem.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 95111103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) 95211103Snilay@cs.wisc.edusystem.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) 95310628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 95411103Snilay@cs.wisc.edusystem.membus.snoop_fanout::samples 469 # Request fanout histogram 95510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 95610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 95710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 95811103Snilay@cs.wisc.edusystem.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram 95910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 96010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 96110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 96210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 96311103Snilay@cs.wisc.edusystem.membus.snoop_fanout::total 469 # Request fanout histogram 96411103Snilay@cs.wisc.edusystem.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks) 96510726Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.6 # Layer utilization (%) 96611103Snilay@cs.wisc.edusystem.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks) 96711103Snilay@cs.wisc.edusystem.membus.respLayer1.utilization 11.1 # Layer utilization (%) 9686039SN/A 9696039SN/A---------- End Simulation Statistics ---------- 970