stats.txt revision 10628
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 310488Snilay@cs.wisc.edusim_seconds 0.000021 # Number of seconds simulated 410488Snilay@cs.wisc.edusim_ticks 21163500 # Number of ticks simulated 510488Snilay@cs.wisc.edufinal_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710628Sandreas.hansson@arm.comhost_inst_rate 81533 # Simulator instruction rate (inst/s) 810628Sandreas.hansson@arm.comhost_op_rate 81515 # Simulator op (including micro ops) rate (op/s) 910628Sandreas.hansson@arm.comhost_tick_rate 345921870 # Simulator tick rate (ticks/s) 1010628Sandreas.hansson@arm.comhost_mem_usage 292088 # Number of bytes of host memory used 1110628Sandreas.hansson@arm.comhost_seconds 0.06 # Real time elapsed on the host 1210488Snilay@cs.wisc.edusim_insts 4986 # Number of instructions simulated 1310488Snilay@cs.wisc.edusim_ops 4986 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610488Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 21120 # Number of bytes read from this memory 1710488Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 1810488Snilay@cs.wisc.edusystem.physmem.bytes_read::total 30144 # Number of bytes read from this memory 1910488Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 21120 # Number of instructions bytes read from this memory 2010488Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 21120 # Number of instructions bytes read from this memory 2110488Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory 2210488Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 2310488Snilay@cs.wisc.edusystem.physmem.num_reads::total 471 # Number of read requests responded to by this memory 2410488Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 997944574 # Total read bandwidth from this memory (bytes/s) 2510488Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data 426394500 # Total read bandwidth from this memory (bytes/s) 2610488Snilay@cs.wisc.edusystem.physmem.bw_read::total 1424339074 # Total read bandwidth from this memory (bytes/s) 2710488Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 997944574 # Instruction read bandwidth from this memory (bytes/s) 2810488Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 997944574 # Instruction read bandwidth from this memory (bytes/s) 2910488Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 997944574 # Total bandwidth to/from this memory (bytes/s) 3010488Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data 426394500 # Total bandwidth to/from this memory (bytes/s) 3110488Snilay@cs.wisc.edusystem.physmem.bw_total::total 1424339074 # Total bandwidth to/from this memory (bytes/s) 3210488Snilay@cs.wisc.edusystem.physmem.readReqs 471 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3410488Snilay@cs.wisc.edusystem.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3610488Snilay@cs.wisc.edusystem.physmem.bytesReadDRAM 30144 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3910488Snilay@cs.wisc.edusystem.physmem.bytesReadSys 30144 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4410488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::0 29 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 0 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 1 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 0 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 7 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 3 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 13 # Per bank write bursts 5110488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::7 53 # Per bank write bursts 5210488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::8 59 # Per bank write bursts 5310488Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::9 76 # Per bank write bursts 5410352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 43 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 20 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 51 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 29 # Per bank write bursts 5810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 80 # Per bank write bursts 5910242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 7 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810488Snilay@cs.wisc.edusystem.physmem.totGap 21083000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8510488Snilay@cs.wisc.edusystem.physmem.readPktSize::6 471 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310488Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see 9410488Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see 9510488Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see 9610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 9710220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 989322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation 19010488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::mean 262.095238 # Bytes accessed per row activation 19110488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::gmean 179.705030 # Bytes accessed per row activation 19210488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::stdev 253.763121 # Bytes accessed per row activation 19310488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation 19410488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::128-255 34 32.38% 60.95% # Bytes accessed per row activation 19510488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::256-383 17 16.19% 77.14% # Bytes accessed per row activation 19610488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::384-511 10 9.52% 86.67% # Bytes accessed per row activation 19710488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation 19810488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::640-767 1 0.95% 91.43% # Bytes accessed per row activation 19910488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::768-895 2 1.90% 93.33% # Bytes accessed per row activation 20010488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::896-1023 2 1.90% 95.24% # Bytes accessed per row activation 20110488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation 20210488Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation 20310488Snilay@cs.wisc.edusystem.physmem.totQLat 5392000 # Total ticks spent queuing 20410488Snilay@cs.wisc.edusystem.physmem.totMemAccLat 14223250 # Total ticks spent from burst creation until serviced by the DRAM 20510488Snilay@cs.wisc.edusystem.physmem.totBusLat 2355000 # Total ticks spent in databus transfers 20610488Snilay@cs.wisc.edusystem.physmem.avgQLat 11447.98 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20810488Snilay@cs.wisc.edusystem.physmem.avgMemAccLat 30197.98 # Average memory access latency per DRAM burst 20910488Snilay@cs.wisc.edusystem.physmem.avgRdBW 1424.34 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21110488Snilay@cs.wisc.edusystem.physmem.avgRdBWSys 1424.34 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21410488Snilay@cs.wisc.edusystem.physmem.busUtil 11.13 # Data bus utilization in percentage 21510488Snilay@cs.wisc.edusystem.physmem.busUtilRead 11.13 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710488Snilay@cs.wisc.edusystem.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21910488Snilay@cs.wisc.edusystem.physmem.readRowHits 356 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22110488Snilay@cs.wisc.edusystem.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22310488Snilay@cs.wisc.edusystem.physmem.avgGap 44762.21 # Average gap between requests 22410488Snilay@cs.wisc.edusystem.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined 22510628Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) 22610628Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) 22710628Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23010628Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) 23110628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) 23210628Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) 23310628Sandreas.hansson@arm.comsystem.physmem_0.averagePower 790.660351 # Core power per rank (mW) 23410628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23710628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states 23810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23910628Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) 24010628Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) 24110628Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24410628Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) 24510628Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) 24610628Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) 24710628Sandreas.hansson@arm.comsystem.physmem_1.averagePower 944.255803 # Core power per rank (mW) 24810628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25110628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25310488Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 2146 # Number of BP lookups 25410488Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted 25510488Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect 25610488Snilay@cs.wisc.edusystem.cpu.branchPred.BTBLookups 1636 # Number of BTB lookups 25710488Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 528 # Number of BTB hits 2589481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25910488Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage 26010488Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. 26110488Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. 26210628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2638428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2648428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2658428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2668428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2678428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2688428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2696039SN/Asystem.cpu.dtb.hits 0 # DTB hits 2706039SN/Asystem.cpu.dtb.misses 0 # DTB misses 2718428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2728428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2738428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2748428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2758428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2768428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2778428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2788428SN/Asystem.cpu.itb.hits 0 # DTB hits 2798428SN/Asystem.cpu.itb.misses 0 # DTB misses 2808428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 28110488Snilay@cs.wisc.edusystem.cpu.workload.num_syscalls 7 # Number of system calls 28210488Snilay@cs.wisc.edusystem.cpu.numCycles 42328 # number of cpu cycles simulated 2838428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2848428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 28510488Snilay@cs.wisc.edusystem.cpu.fetch.icacheStallCycles 8967 # Number of cycles fetch is stalled on an Icache miss 28610488Snilay@cs.wisc.edusystem.cpu.fetch.Insts 13064 # Number of instructions fetch has processed 28710488Snilay@cs.wisc.edusystem.cpu.fetch.Branches 2146 # Number of branches that fetch encountered 28810488Snilay@cs.wisc.edusystem.cpu.fetch.predictedBranches 812 # Number of branches that fetch has predicted taken 28910488Snilay@cs.wisc.edusystem.cpu.fetch.Cycles 4771 # Number of cycles fetch has run and was not squashing or blocked 29010488Snilay@cs.wisc.edusystem.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing 29110352Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps 29210488Snilay@cs.wisc.edusystem.cpu.fetch.CacheLines 2037 # Number of cache lines fetched 29310488Snilay@cs.wisc.edusystem.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed 29410488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::samples 14376 # Number of instructions fetched each cycle (Total) 29510488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::mean 0.908737 # Number of instructions fetched each cycle (Total) 29610488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::stdev 2.207470 # Number of instructions fetched each cycle (Total) 2976291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 29810488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::0 11035 76.76% 76.76% # Number of instructions fetched each cycle (Total) 29910488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::1 1473 10.25% 87.01% # Number of instructions fetched each cycle (Total) 30010488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::2 126 0.88% 87.88% # Number of instructions fetched each cycle (Total) 30110488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::3 160 1.11% 89.00% # Number of instructions fetched each cycle (Total) 30210488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::4 283 1.97% 90.96% # Number of instructions fetched each cycle (Total) 30310488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::5 90 0.63% 91.59% # Number of instructions fetched each cycle (Total) 30410488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::6 137 0.95% 92.54% # Number of instructions fetched each cycle (Total) 30510488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::7 121 0.84% 93.38% # Number of instructions fetched each cycle (Total) 30610488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::8 951 6.62% 100.00% # Number of instructions fetched each cycle (Total) 3076291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3086291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3096291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 31010488Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::total 14376 # Number of instructions fetched each cycle (Total) 31110488Snilay@cs.wisc.edusystem.cpu.fetch.branchRate 0.050699 # Number of branch fetches per cycle 31210488Snilay@cs.wisc.edusystem.cpu.fetch.rate 0.308637 # Number of inst fetches per cycle 31310488Snilay@cs.wisc.edusystem.cpu.decode.IdleCycles 8549 # Number of cycles decode is idle 31410488Snilay@cs.wisc.edusystem.cpu.decode.BlockedCycles 2515 # Number of cycles decode is blocked 31510488Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 2791 # Number of cycles decode is running 31610488Snilay@cs.wisc.edusystem.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking 31710488Snilay@cs.wisc.edusystem.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing 31810488Snilay@cs.wisc.edusystem.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch 31910488Snilay@cs.wisc.edusystem.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 32010488Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 12032 # Number of instructions handled by decode 32110488Snilay@cs.wisc.edusystem.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode 32210488Snilay@cs.wisc.edusystem.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing 32310488Snilay@cs.wisc.edusystem.cpu.rename.IdleCycles 8711 # Number of cycles rename is idle 32410352Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking 32510488Snilay@cs.wisc.edusystem.cpu.rename.serializeStallCycles 944 # count of cycles rename stalled for serializing inst 32610488Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 2743 # Number of cycles rename is running 32710488Snilay@cs.wisc.edusystem.cpu.rename.UnblockCycles 1081 # Number of cycles rename is unblocking 32810488Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 11544 # Number of instructions processed by rename 32910352Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 33010352Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full 33110488Snilay@cs.wisc.edusystem.cpu.rename.LQFullEvents 196 # Number of times rename has blocked due to LQ full 33210352Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full 33310488Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 6963 # Number of destination operands rename has renamed 33410488Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made 33510488Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 13345 # Number of integer rename lookups 3369924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 33710488Snilay@cs.wisc.edusystem.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed 33810488Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 3681 # Number of HB maps that are undone due to squashing 33910488Snilay@cs.wisc.edusystem.cpu.rename.serializingInsts 13 # count of serializing insts renamed 34010488Snilay@cs.wisc.edusystem.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed 34110488Snilay@cs.wisc.edusystem.cpu.rename.skidInsts 298 # count of insts added to the skid buffer 34210488Snilay@cs.wisc.edusystem.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. 34310488Snilay@cs.wisc.edusystem.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. 3448428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 34510488Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. 34610488Snilay@cs.wisc.edusystem.cpu.iq.iqInstsAdded 9029 # Number of instructions added to the IQ (excludes non-spec) 34710488Snilay@cs.wisc.edusystem.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ 34810488Snilay@cs.wisc.edusystem.cpu.iq.iqInstsIssued 8280 # Number of instructions issued 34910488Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued 35010488Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsExamined 3419 # Number of squashed instructions iterated over during squash; mainly for profiling 35110488Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedOperandsExamined 1838 # Number of squashed operands that are examined and possibly removed from graph 3529729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 35310488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::samples 14376 # Number of insts issued each cycle 35410488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::mean 0.575960 # Number of insts issued each cycle 35510488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::stdev 1.325471 # Number of insts issued each cycle 3568428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 35710488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::0 11054 76.89% 76.89% # Number of insts issued each cycle 35810488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::1 1314 9.14% 86.03% # Number of insts issued each cycle 35910488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::2 739 5.14% 91.17% # Number of insts issued each cycle 36010488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::3 413 2.87% 94.05% # Number of insts issued each cycle 36110488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::4 345 2.40% 96.45% # Number of insts issued each cycle 36210488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::5 315 2.19% 98.64% # Number of insts issued each cycle 36310488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::6 104 0.72% 99.36% # Number of insts issued each cycle 36410488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::7 66 0.46% 99.82% # Number of insts issued each cycle 36510488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle 3668428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3678428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3688428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 36910488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::total 14376 # Number of insts issued each cycle 3708428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 37110488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntAlu 8 4.06% 4.06% # attempts to use FU when none available 37210488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntMult 0 0.00% 4.06% # attempts to use FU when none available 37310488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntDiv 0 0.00% 4.06% # attempts to use FU when none available 37410488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatAdd 0 0.00% 4.06% # attempts to use FU when none available 37510488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 4.06% # attempts to use FU when none available 37610488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 4.06% # attempts to use FU when none available 37710488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 4.06% # attempts to use FU when none available 37810488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 4.06% # attempts to use FU when none available 37910488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.06% # attempts to use FU when none available 38010488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 4.06% # attempts to use FU when none available 38110488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.06% # attempts to use FU when none available 38210488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAlu 0 0.00% 4.06% # attempts to use FU when none available 38310488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 4.06% # attempts to use FU when none available 38410488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 4.06% # attempts to use FU when none available 38510488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 4.06% # attempts to use FU when none available 38610488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMult 0 0.00% 4.06% # attempts to use FU when none available 38710488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.06% # attempts to use FU when none available 38810488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShift 0 0.00% 4.06% # attempts to use FU when none available 38910488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.06% # attempts to use FU when none available 39010488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.06% # attempts to use FU when none available 39110488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.06% # attempts to use FU when none available 39210488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.06% # attempts to use FU when none available 39310488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.06% # attempts to use FU when none available 39410488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.06% # attempts to use FU when none available 39510488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.06% # attempts to use FU when none available 39610488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.06% # attempts to use FU when none available 39710488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.06% # attempts to use FU when none available 39810488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.06% # attempts to use FU when none available 39910488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.06% # attempts to use FU when none available 40010488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemRead 131 66.50% 70.56% # attempts to use FU when none available 40110488Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemWrite 58 29.44% 100.00% # attempts to use FU when none available 4028428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4038428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4048241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 40510488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntAlu 4865 58.76% 58.76% # Type of FU issued 40610488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued 40710488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued 40810488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued 40910488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued 41010488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued 41110488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued 41210488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued 41310488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued 41410488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued 41510488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued 41610488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued 41710488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued 41810488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued 41910488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued 42010488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued 42110488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued 42210488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued 42310488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued 42410488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued 42510488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued 42610488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued 42710488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued 42810488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued 42910488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued 43010488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued 43110488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued 43210488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued 43310488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued 43410488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemRead 2336 28.21% 87.05% # Type of FU issued 43510488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemWrite 1072 12.95% 100.00% # Type of FU issued 4368241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4378241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 43810488Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::total 8280 # Type of FU issued 43910488Snilay@cs.wisc.edusystem.cpu.iq.rate 0.195615 # Inst issue rate 44010488Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_cnt 197 # FU busy when requested 44110488Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_rate 0.023792 # FU busy rate (busy events/executed inst) 44210488Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_reads 31160 # Number of integer instruction queue reads 44310488Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_writes 12466 # Number of integer instruction queue writes 44410488Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 7466 # Number of integer instruction queue wakeup accesses 4458428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 4468428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 4478428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 44810488Snilay@cs.wisc.edusystem.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses 4498428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 45010488Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores 4518428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 45210488Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed 45310488Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed 45410242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 45510488Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed 4568428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4578428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4588428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 45910352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 4608428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 46110488Snilay@cs.wisc.edusystem.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing 46210488Snilay@cs.wisc.edusystem.cpu.iew.iewBlockCycles 475 # Number of cycles IEW is blocking 46310488Snilay@cs.wisc.edusystem.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking 46410488Snilay@cs.wisc.edusystem.cpu.iew.iewDispatchedInsts 10593 # Number of instructions dispatched to IQ 46510488Snilay@cs.wisc.edusystem.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch 46610488Snilay@cs.wisc.edusystem.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions 46710488Snilay@cs.wisc.edusystem.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions 46810488Snilay@cs.wisc.edusystem.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions 46910352Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 47010488Snilay@cs.wisc.edusystem.cpu.iew.iewLSQFullEvents 13 # Number of times the LSQ has become full, causing a stall 47110242Ssteve.reinhardt@amd.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 47210488Snilay@cs.wisc.edusystem.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly 47310488Snilay@cs.wisc.edusystem.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly 47410488Snilay@cs.wisc.edusystem.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute 47510488Snilay@cs.wisc.edusystem.cpu.iew.iewExecutedInsts 7957 # Number of executed instructions 47610488Snilay@cs.wisc.edusystem.cpu.iew.iewExecLoadInsts 2194 # Number of load instructions executed 47710488Snilay@cs.wisc.edusystem.cpu.iew.iewExecSquashedInsts 323 # Number of squashed instructions skipped in execute 4788428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 47910488Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 1553 # number of nop insts executed 48010488Snilay@cs.wisc.edusystem.cpu.iew.exec_refs 3252 # number of memory reference insts executed 48110488Snilay@cs.wisc.edusystem.cpu.iew.exec_branches 1379 # Number of branches executed 48210488Snilay@cs.wisc.edusystem.cpu.iew.exec_stores 1058 # Number of stores executed 48310488Snilay@cs.wisc.edusystem.cpu.iew.exec_rate 0.187984 # Inst execution rate 48410488Snilay@cs.wisc.edusystem.cpu.iew.wb_sent 7571 # cumulative count of insts sent to commit 48510488Snilay@cs.wisc.edusystem.cpu.iew.wb_count 7468 # cumulative count of insts written-back 48610488Snilay@cs.wisc.edusystem.cpu.iew.wb_producers 2915 # num instructions producing a value 48710488Snilay@cs.wisc.edusystem.cpu.iew.wb_consumers 4399 # num instructions consuming a value 4888428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 48910488Snilay@cs.wisc.edusystem.cpu.iew.wb_rate 0.176432 # insts written-back per cycle 49010488Snilay@cs.wisc.edusystem.cpu.iew.wb_fanout 0.662651 # average fanout of values written-back 4918428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 49210488Snilay@cs.wisc.edusystem.cpu.commit.commitSquashedInsts 4969 # The number of squashed insts skipped by commit 49310488Snilay@cs.wisc.edusystem.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 49410488Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 386 # The number of times a branch was mispredicted 49510488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::samples 13506 # Number of insts commited each cycle 49610488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::mean 0.416333 # Number of insts commited each cycle 49710488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::stdev 1.231872 # Number of insts commited each cycle 4988428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 49910488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::0 11333 83.91% 83.91% # Number of insts commited each cycle 50010488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::1 875 6.48% 90.39% # Number of insts commited each cycle 50110488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::2 515 3.81% 94.20% # Number of insts commited each cycle 50210488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::3 250 1.85% 96.05% # Number of insts commited each cycle 50310488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::4 149 1.10% 97.16% # Number of insts commited each cycle 50410488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::5 177 1.31% 98.47% # Number of insts commited each cycle 50510488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::6 64 0.47% 98.94% # Number of insts commited each cycle 50610488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle 50710488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::8 102 0.76% 100.00% # Number of insts commited each cycle 5088428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5098428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5108428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 51110488Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::total 13506 # Number of insts commited each cycle 51210488Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 5623 # Number of instructions committed 51310488Snilay@cs.wisc.edusystem.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed 5148428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 51510488Snilay@cs.wisc.edusystem.cpu.commit.refs 2033 # Number of memory references committed 51610488Snilay@cs.wisc.edusystem.cpu.commit.loads 1132 # Number of loads committed 5178428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 51810488Snilay@cs.wisc.edusystem.cpu.commit.branches 883 # Number of branches committed 5198428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 52010488Snilay@cs.wisc.edusystem.cpu.commit.int_insts 4942 # Number of committed integer instructions. 52110488Snilay@cs.wisc.edusystem.cpu.commit.function_calls 85 # Number of function calls committed. 52210488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction 52310488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction 52410488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction 52510488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction 52610488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction 52710488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction 52810488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction 52910488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction 53010488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction 53110488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction 53210488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction 53310488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction 53410488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction 53510488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction 53610488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction 53710488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction 53810488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction 53910488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction 54010488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction 54110488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction 54210488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction 54310488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction 54410488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction 54510488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction 54610488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction 54710488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction 54810488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction 54910488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction 55010488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction 55110488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction 55210488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction 55310488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction 55410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 55510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 55610488Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 5623 # Class of committed instruction 55710488Snilay@cs.wisc.edusystem.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached 5588428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 55910488Snilay@cs.wisc.edusystem.cpu.rob.rob_reads 23983 # The number of ROB reads 56010488Snilay@cs.wisc.edusystem.cpu.rob.rob_writes 22065 # The number of ROB writes 56110488Snilay@cs.wisc.edusystem.cpu.timesIdled 275 # Number of times that the entire CPU went into an idle state and unscheduled itself 56210488Snilay@cs.wisc.edusystem.cpu.idleCycles 27952 # Total number of cycles that the CPU has spent unscheduled due to idling 56310488Snilay@cs.wisc.edusystem.cpu.committedInsts 4986 # Number of Instructions Simulated 56410488Snilay@cs.wisc.edusystem.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated 56510488Snilay@cs.wisc.edusystem.cpu.cpi 8.489370 # CPI: Cycles Per Instruction 56610488Snilay@cs.wisc.edusystem.cpu.cpi_total 8.489370 # CPI: Total CPI of All Threads 56710488Snilay@cs.wisc.edusystem.cpu.ipc 0.117794 # IPC: Instructions Per Cycle 56810488Snilay@cs.wisc.edusystem.cpu.ipc_total 0.117794 # IPC: Total IPC of All Threads 56910488Snilay@cs.wisc.edusystem.cpu.int_regfile_reads 10767 # number of integer regfile reads 57010488Snilay@cs.wisc.edusystem.cpu.int_regfile_writes 5247 # number of integer regfile writes 5718428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 5728428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 57310352Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 164 # number of misc regfile reads 57410628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 57510628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use 57610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. 57710628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 57810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. 57910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 58010628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor 58110628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy 58210628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy 58310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 58410628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 58510628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id 58610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 58710628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses 58810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 6061 # Number of data accesses 58910628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits 59010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits 59110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits 59210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits 59310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits 59410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits 59510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits 59610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2445 # number of overall hits 59710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses 59810628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses 59910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses 60010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses 60110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses 60210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses 60310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses 60410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 515 # number of overall misses 60510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles 60610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles 60710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles 60810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles 60910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles 61010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles 61110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles 61210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles 61310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) 61410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) 61510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 61610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 61710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses 61810628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses 61910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses 62010628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses 62110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses 62210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses 62310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses 62410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses 62510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses 62610628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses 62710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses 62810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses 62910628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency 63010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency 63110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency 63210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency 63310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency 63410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency 63510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency 63610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency 63710628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked 63810628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 63910628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 64010628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 64110628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked 64210628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 64310628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 64410628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 64510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits 64610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits 64710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits 64810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits 64910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits 65010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits 65110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits 65210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits 65310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 65410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 65510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 65610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 65710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 65810628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 65910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 66010628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 66110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles 66210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles 66310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles 66410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles 66510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles 66610628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles 66710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles 66810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles 66910628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses 67010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses 67110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 67210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 67310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses 67410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses 67510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses 67610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses 67710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency 67810628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency 67910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency 68010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency 68110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency 68210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency 68310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency 68410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency 68510628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 6869838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 17 # number of replacements 68710488Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use 68810488Snilay@cs.wisc.edusystem.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. 68910488Snilay@cs.wisc.edusystem.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. 69010488Snilay@cs.wisc.edusystem.cpu.icache.tags.avg_refs 4.783784 # Average number of references to valid blocks. 6919838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 69210488Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 158.344728 # Average occupied blocks per requestor 69310488Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.077317 # Average percentage of cache occupancy 69410488Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.077317 # Average percentage of cache occupancy 69510488Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id 69610488Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id 69710488Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id 69810488Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id 69910488Snilay@cs.wisc.edusystem.cpu.icache.tags.tag_accesses 4407 # Number of tag accesses 70010488Snilay@cs.wisc.edusystem.cpu.icache.tags.data_accesses 4407 # Number of data accesses 70110488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 1593 # number of ReadReq hits 70210488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 1593 # number of ReadReq hits 70310488Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 1593 # number of demand (read+write) hits 70410488Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 1593 # number of demand (read+write) hits 70510488Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 1593 # number of overall hits 70610488Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 1593 # number of overall hits 70710488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::cpu.inst 444 # number of ReadReq misses 70810488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 444 # number of ReadReq misses 70910488Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::cpu.inst 444 # number of demand (read+write) misses 71010488Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 444 # number of demand (read+write) misses 71110488Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::cpu.inst 444 # number of overall misses 71210488Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 444 # number of overall misses 71310488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::cpu.inst 30764750 # number of ReadReq miss cycles 71410488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::total 30764750 # number of ReadReq miss cycles 71510488Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::cpu.inst 30764750 # number of demand (read+write) miss cycles 71610488Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::total 30764750 # number of demand (read+write) miss cycles 71710488Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::cpu.inst 30764750 # number of overall miss cycles 71810488Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::total 30764750 # number of overall miss cycles 71910488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 2037 # number of ReadReq accesses(hits+misses) 72010488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 2037 # number of ReadReq accesses(hits+misses) 72110488Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 2037 # number of demand (read+write) accesses 72210488Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 2037 # number of demand (read+write) accesses 72310488Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 2037 # number of overall (read+write) accesses 72410488Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 2037 # number of overall (read+write) accesses 72510488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217968 # miss rate for ReadReq accesses 72610488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.217968 # miss rate for ReadReq accesses 72710488Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.217968 # miss rate for demand accesses 72810488Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.217968 # miss rate for demand accesses 72910488Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.217968 # miss rate for overall accesses 73010488Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.217968 # miss rate for overall accesses 73110488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69289.977477 # average ReadReq miss latency 73210488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 69289.977477 # average ReadReq miss latency 73310488Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency 73410488Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::total 69289.977477 # average overall miss latency 73510488Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency 73610488Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::total 69289.977477 # average overall miss latency 73710488Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7388428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 73910488Snilay@cs.wisc.edusystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7408428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 74110488Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7428983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7438428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 7448428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 74510488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 111 # number of ReadReq MSHR hits 74610488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits 74710488Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::cpu.inst 111 # number of demand (read+write) MSHR hits 74810488Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::total 111 # number of demand (read+write) MSHR hits 74910488Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::cpu.inst 111 # number of overall MSHR hits 75010488Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::total 111 # number of overall MSHR hits 75110488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses 75210488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses 75310488Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses 75410488Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses 75510488Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses 75610488Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses 75710488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24043500 # number of ReadReq MSHR miss cycles 75810488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 24043500 # number of ReadReq MSHR miss cycles 75910488Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 24043500 # number of demand (read+write) MSHR miss cycles 76010488Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::total 24043500 # number of demand (read+write) MSHR miss cycles 76110488Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 24043500 # number of overall MSHR miss cycles 76210488Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::total 24043500 # number of overall MSHR miss cycles 76310488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for ReadReq accesses 76410488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.163476 # mshr miss rate for ReadReq accesses 76510488Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for demand accesses 76610488Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.163476 # mshr miss rate for demand accesses 76710488Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for overall accesses 76810488Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.163476 # mshr miss rate for overall accesses 76910488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72202.702703 # average ReadReq mshr miss latency 77010488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72202.702703 # average ReadReq mshr miss latency 77110488Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency 77210488Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency 77310488Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency 77410488Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency 7758428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7769838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 77710488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tagsinuse 218.292920 # Cycle average of tags in use 7789838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 77910488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. 78010488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. 7819838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 78210488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.inst 160.335208 # Average occupied blocks per requestor 78310488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.data 57.957712 # Average occupied blocks per requestor 78410488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004893 # Average percentage of cache occupancy 78510488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy 78610488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::total 0.006662 # Average percentage of cache occupancy 78710488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id 78810488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 78910488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 79010488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id 79110488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses 79210488Snilay@cs.wisc.edusystem.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses 7939348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 7949348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 7959348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 7969348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 7979348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 7989348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 79910488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.inst 330 # number of ReadReq misses 80010352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 80110488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::total 421 # number of ReadReq misses 80210488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 80310488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 80410488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 330 # number of demand (read+write) misses 80510488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 80610488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::total 471 # number of demand (read+write) misses 80710488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses 80810488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 80910488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::total 471 # number of overall misses 81010488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23680500 # number of ReadReq miss cycles 81110488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216500 # number of ReadReq miss cycles 81210488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::total 30897000 # number of ReadReq miss cycles 81310488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3981500 # number of ReadExReq miss cycles 81410488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::total 3981500 # number of ReadExReq miss cycles 81510488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.inst 23680500 # number of demand (read+write) miss cycles 81610488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.data 11198000 # number of demand (read+write) miss cycles 81710488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::total 34878500 # number of demand (read+write) miss cycles 81810488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.inst 23680500 # number of overall miss cycles 81910488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.data 11198000 # number of overall miss cycles 82010488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::total 34878500 # number of overall miss cycles 82110488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.inst 333 # number of ReadReq accesses(hits+misses) 82210352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 82310488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) 82410488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 82510488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 82610488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.inst 333 # number of demand (read+write) accesses 82710488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 82810488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::total 474 # number of demand (read+write) accesses 82910488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.inst 333 # number of overall (read+write) accesses 83010488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 83110488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::total 474 # number of overall (read+write) accesses 83210488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.990991 # miss rate for ReadReq accesses 8339348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 83410488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.992925 # miss rate for ReadReq accesses 8359348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8369348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 83710488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.990991 # miss rate for demand accesses 8389348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 83910488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::total 0.993671 # miss rate for demand accesses 84010488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses 8419348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 84210488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses 84310488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71759.090909 # average ReadReq miss latency 84410488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79302.197802 # average ReadReq miss latency 84510488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 73389.548694 # average ReadReq miss latency 84610488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79630 # average ReadExReq miss latency 84710488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 79630 # average ReadExReq miss latency 84810488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency 84910488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency 85010488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::total 74052.016985 # average overall miss latency 85110488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency 85210488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency 85310488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::total 74052.016985 # average overall miss latency 8549348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8559348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8569348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8579348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8589348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8599348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8609348SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8619348SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 86210488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses 86310352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 86410488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses 86510488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 86610488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 86710488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses 86810488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 86910488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::total 471 # number of demand (read+write) MSHR misses 87010488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses 87110488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 87210488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses 87310488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19517000 # number of ReadReq MSHR miss cycles 87410488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6096000 # number of ReadReq MSHR miss cycles 87510488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 25613000 # number of ReadReq MSHR miss cycles 87610488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3359000 # number of ReadExReq MSHR miss cycles 87710488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3359000 # number of ReadExReq MSHR miss cycles 87810488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19517000 # number of demand (read+write) MSHR miss cycles 87910488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9455000 # number of demand (read+write) MSHR miss cycles 88010488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::total 28972000 # number of demand (read+write) MSHR miss cycles 88110488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19517000 # number of overall MSHR miss cycles 88210488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9455000 # number of overall MSHR miss cycles 88310488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::total 28972000 # number of overall MSHR miss cycles 88410488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses 8859348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 88610488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses 8879348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 8889348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 88910488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for demand accesses 8909348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 89110488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 # mshr miss rate for demand accesses 89210488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses 8939348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 89410488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses 89510488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59142.424242 # average ReadReq mshr miss latency 89610488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66989.010989 # average ReadReq mshr miss latency 89710488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60838.479810 # average ReadReq mshr miss latency 89810488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67180 # average ReadExReq mshr miss latency 89910488Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67180 # average ReadExReq mshr miss latency 90010488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency 90110488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency 90210488Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency 90310488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency 90410488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency 90510488Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency 9069348SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 90710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution 90810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution 90910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 91010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 91110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) 91210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 91310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) 91410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) 91510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 91610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) 91710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 91810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram 91910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 92010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 92110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 92210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 92310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram 92410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 92510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 92610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 92710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 92810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram 92910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) 93010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 93110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) 93210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 93310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) 93410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 93510628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 421 # Transaction distribution 93610628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 421 # Transaction distribution 93710628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 50 # Transaction distribution 93810628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 50 # Transaction distribution 93910628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) 94010628Sandreas.hansson@arm.comsystem.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) 94110628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) 94210628Sandreas.hansson@arm.comsystem.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) 94310628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 94410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 471 # Request fanout histogram 94510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 94610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 94710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 94810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram 94910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 95010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 95110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 95210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 95310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 471 # Request fanout histogram 95410628Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) 95510628Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 95610628Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) 95710628Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 20.9 # Layer utilization (%) 9586039SN/A 9596039SN/A---------- End Simulation Statistics ---------- 960