stats.txt revision 10409
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39729Sandreas.hansson@arm.comsim_seconds 0.000022 # Number of seconds simulated 410352Sandreas.hansson@arm.comsim_ticks 21611500 # Number of ticks simulated 510352Sandreas.hansson@arm.comfinal_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710409Sandreas.hansson@arm.comhost_inst_rate 87050 # Simulator instruction rate (inst/s) 810409Sandreas.hansson@arm.comhost_op_rate 87030 # Simulator op (including micro ops) rate (op/s) 910409Sandreas.hansson@arm.comhost_tick_rate 364707967 # Simulator tick rate (ticks/s) 1010409Sandreas.hansson@arm.comhost_mem_usage 288672 # Number of bytes of host memory used 1110409Sandreas.hansson@arm.comhost_seconds 0.06 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5156 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5156 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory 1710352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 30656 # Number of bytes read from this memory 1910352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory 2010352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory 2110352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory 2210352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 2310352Sandreas.hansson@arm.comsystem.physmem.num_reads::total 479 # Number of read requests responded to by this memory 2410352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 997987183 # Total read bandwidth from this memory (bytes/s) 2510352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 420516854 # Total read bandwidth from this memory (bytes/s) 2610352Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1418504037 # Total read bandwidth from this memory (bytes/s) 2710352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 997987183 # Instruction read bandwidth from this memory (bytes/s) 2810352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 997987183 # Instruction read bandwidth from this memory (bytes/s) 2910352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 997987183 # Total bandwidth to/from this memory (bytes/s) 3010352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 420516854 # Total bandwidth to/from this memory (bytes/s) 3110352Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1418504037 # Total bandwidth to/from this memory (bytes/s) 3210352Sandreas.hansson@arm.comsystem.physmem.readReqs 479 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3410352Sandreas.hansson@arm.comsystem.physmem.readBursts 479 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3610352Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 30656 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3910352Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 30656 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 30 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 0 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 1 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 0 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 7 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 3 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 13 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 54 # Per bank write bursts 5210352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 64 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 77 # Per bank write bursts 5410352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 43 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 20 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 51 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 29 # Per bank write bursts 5810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 80 # Per bank write bursts 5910242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 7 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810352Sandreas.hansson@arm.comsystem.physmem.totGap 21538500 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8510352Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 479 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see 9410242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see 9510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see 9610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 9710220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 989322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation 19010352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 255.412844 # Bytes accessed per row activation 19110352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 174.780194 # Bytes accessed per row activation 19210352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 251.892291 # Bytes accessed per row activation 19310352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 32 29.36% 29.36% # Bytes accessed per row activation 19410352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 38 34.86% 64.22% # Bytes accessed per row activation 19510352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 15 13.76% 77.98% # Bytes accessed per row activation 19610352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 11 10.09% 88.07% # Bytes accessed per row activation 19710352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 3 2.75% 90.83% # Bytes accessed per row activation 19810352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 3 2.75% 93.58% # Bytes accessed per row activation 19910352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 2 1.83% 95.41% # Bytes accessed per row activation 20010352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation 20110352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation 20210409Sandreas.hansson@arm.comsystem.physmem.totQLat 5601000 # Total ticks spent queuing 20310409Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 14582250 # Total ticks spent from burst creation until serviced by the DRAM 20410352Sandreas.hansson@arm.comsystem.physmem.totBusLat 2395000 # Total ticks spent in databus transfers 20510409Sandreas.hansson@arm.comsystem.physmem.avgQLat 11693.11 # Average queueing delay per DRAM burst 2069978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20710409Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 30443.11 # Average memory access latency per DRAM burst 20810352Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1418.50 # Average DRAM read bandwidth in MiByte/s 2099978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21010352Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1418.50 # Average system read bandwidth in MiByte/s 2119978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21310352Sandreas.hansson@arm.comsystem.physmem.busUtil 11.08 # Data bus utilization in percentage 21410352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 11.08 # Data bus utilization in percentage for reads 2159978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21610352Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing 2179978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21810352Sandreas.hansson@arm.comsystem.physmem.readRowHits 360 # Number of row buffer hits during reads 2199312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22010352Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads 2219312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22210352Sandreas.hansson@arm.comsystem.physmem.avgGap 44965.55 # Average gap between requests 22310352Sandreas.hansson@arm.comsystem.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined 22410220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 11000 # Time in different power states 22510220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 520000 # Time in different power states 22610220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 22710352Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 15315250 # Time in different power states 22810220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 22910352Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 428 # Transaction distribution 23010352Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 428 # Transaction distribution 2319729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 51 # Transaction distribution 2329729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 51 # Transaction distribution 23310352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 958 # Packet count per connected master and slave (bytes) 23410352Sandreas.hansson@arm.comsystem.membus.pkt_count::total 958 # Packet count per connected master and slave (bytes) 23510409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) 23610409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) 23710409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 23810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 479 # Request fanout histogram 23910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 24010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 24110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 24210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 479 100.00% 100.00% # Request fanout histogram 24310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 24410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 24510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 24610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 24710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 479 # Request fanout histogram 24810352Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) 2499797Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 25010409Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4492250 # Layer occupancy (ticks) 25110352Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 20.8 # Layer utilization (%) 25210036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 25310352Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2196 # Number of BP lookups 25410352Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1454 # Number of conditional branches predicted 25510352Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 435 # Number of conditional branches incorrect 25610352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 1700 # Number of BTB lookups 25710352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 564 # Number of BTB hits 2589481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25910352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 33.176471 # BTB Hit Percentage 26010352Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 277 # Number of times the RAS was used to get a target. 26110352Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 69 # Number of incorrect RAS predictions. 2628428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2638428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2648428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2658428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2668428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2678428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2686039SN/Asystem.cpu.dtb.hits 0 # DTB hits 2696039SN/Asystem.cpu.dtb.misses 0 # DTB misses 2708428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2718428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2728428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2738428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2748428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2758428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2768428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2778428SN/Asystem.cpu.itb.hits 0 # DTB hits 2788428SN/Asystem.cpu.itb.misses 0 # DTB misses 2798428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 2808428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 28110352Sandreas.hansson@arm.comsystem.cpu.numCycles 43224 # number of cpu cycles simulated 2828428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2838428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 28410352Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 9138 # Number of cycles fetch is stalled on an Icache miss 28510352Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 13312 # Number of instructions fetch has processed 28610352Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2196 # Number of branches that fetch encountered 28710352Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken 28810352Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked 28910352Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing 29010352Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps 29110352Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2068 # Number of cache lines fetched 29210352Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed 29310352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14703 # Number of instructions fetched each cycle (Total) 29410352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.905393 # Number of instructions fetched each cycle (Total) 29510352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.198604 # Number of instructions fetched each cycle (Total) 2966291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 29710352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 11282 76.73% 76.73% # Number of instructions fetched each cycle (Total) 29810352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 1513 10.29% 87.02% # Number of instructions fetched each cycle (Total) 29910352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 130 0.88% 87.91% # Number of instructions fetched each cycle (Total) 30010352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 159 1.08% 88.99% # Number of instructions fetched each cycle (Total) 30110352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 291 1.98% 90.97% # Number of instructions fetched each cycle (Total) 30210352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 99 0.67% 91.64% # Number of instructions fetched each cycle (Total) 30310352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 152 1.03% 92.67% # Number of instructions fetched each cycle (Total) 30410352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 125 0.85% 93.53% # Number of instructions fetched each cycle (Total) 30510352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 952 6.47% 100.00% # Number of instructions fetched each cycle (Total) 3066291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3076291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3086291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 30910352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14703 # Number of instructions fetched each cycle (Total) 31010352Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.050805 # Number of branch fetches per cycle 31110352Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.307977 # Number of inst fetches per cycle 31210352Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8679 # Number of cycles decode is idle 31310352Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 2634 # Number of cycles decode is blocked 31410352Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2860 # Number of cycles decode is running 31510352Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking 31610352Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 400 # Number of cycles decode is squashing 31710352Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 179 # Number of times decode resolved a branch 31810352Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction 31910352Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 12297 # Number of instructions handled by decode 32010352Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 180 # Number of squashed instructions handled by decode 32110352Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 400 # Number of cycles rename is squashing 32210352Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 8850 # Number of cycles rename is idle 32310352Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking 32410352Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 975 # count of cycles rename stalled for serializing inst 32510352Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2807 # Number of cycles rename is running 32610352Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 1169 # Number of cycles rename is unblocking 32710352Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 11801 # Number of instructions processed by rename 32810352Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 32910352Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full 33010352Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 281 # Number of times rename has blocked due to LQ full 33110352Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full 33210352Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 7107 # Number of destination operands rename has renamed 33310352Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 13927 # Number of register rename lookups that rename has made 33410352Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 13678 # Number of integer rename lookups 3359924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 3369150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 33710352Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 3709 # Number of HB maps that are undone due to squashing 3389797Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 16 # count of serializing insts renamed 3399797Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 34010352Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 307 # count of insts added to the skid buffer 34110352Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2543 # Number of loads inserted to the mem dependence unit. 34210352Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1213 # Number of stores inserted to the mem dependence unit. 3438428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 3448428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 34510352Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 9299 # Number of instructions added to the IQ (excludes non-spec) 3469729Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 34710352Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8548 # Number of instructions issued 34810352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued 34910352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 3486 # Number of squashed instructions iterated over during squash; mainly for profiling 35010352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 1874 # Number of squashed operands that are examined and possibly removed from graph 3519729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 35210352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14703 # Number of insts issued each cycle 35310352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.581378 # Number of insts issued each cycle 35410352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.331585 # Number of insts issued each cycle 3558428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 35610352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 11282 76.73% 76.73% # Number of insts issued each cycle 35710352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1346 9.15% 85.89% # Number of insts issued each cycle 35810352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 761 5.18% 91.06% # Number of insts issued each cycle 35910352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 427 2.90% 93.97% # Number of insts issued each cycle 36010352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 364 2.48% 96.44% # Number of insts issued each cycle 36110352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 316 2.15% 98.59% # Number of insts issued each cycle 36210352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 114 0.78% 99.37% # Number of insts issued each cycle 36310352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 65 0.44% 99.81% # Number of insts issued each cycle 36410352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle 3658428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3668428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3678428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 36810352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14703 # Number of insts issued each cycle 3698428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 37010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 8 3.96% 3.96% # attempts to use FU when none available 37110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.96% # attempts to use FU when none available 37210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.96% # attempts to use FU when none available 37310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.96% # attempts to use FU when none available 37410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.96% # attempts to use FU when none available 37510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.96% # attempts to use FU when none available 37610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.96% # attempts to use FU when none available 37710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.96% # attempts to use FU when none available 37810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.96% # attempts to use FU when none available 37910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.96% # attempts to use FU when none available 38010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.96% # attempts to use FU when none available 38110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.96% # attempts to use FU when none available 38210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.96% # attempts to use FU when none available 38310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.96% # attempts to use FU when none available 38410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.96% # attempts to use FU when none available 38510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.96% # attempts to use FU when none available 38610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.96% # attempts to use FU when none available 38710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.96% # attempts to use FU when none available 38810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.96% # attempts to use FU when none available 38910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.96% # attempts to use FU when none available 39010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.96% # attempts to use FU when none available 39110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.96% # attempts to use FU when none available 39210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.96% # attempts to use FU when none available 39310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.96% # attempts to use FU when none available 39410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.96% # attempts to use FU when none available 39510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.96% # attempts to use FU when none available 39610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.96% # attempts to use FU when none available 39710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.96% # attempts to use FU when none available 39810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.96% # attempts to use FU when none available 39910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 135 66.83% 70.79% # attempts to use FU when none available 40010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 59 29.21% 100.00% # attempts to use FU when none available 4018428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4028428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4038241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 40410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5034 58.89% 58.89% # Type of FU issued 40510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 5 0.06% 58.95% # Type of FU issued 40610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued 40710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued 40810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued 40910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued 41010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued 41110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued 41210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued 41310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued 41410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued 41510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued 41610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued 41710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued 41810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued 41910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued 42010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued 42110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued 42210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued 42310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued 42410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued 42510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued 42610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued 42710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued 42810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued 42910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued 43010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued 43110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued 43210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued 43310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2396 28.03% 87.03% # Type of FU issued 43410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1109 12.97% 100.00% # Type of FU issued 4358241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4368241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 43710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8548 # Type of FU issued 43810352Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.197761 # Inst issue rate 43910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 202 # FU busy when requested 44010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.023631 # FU busy rate (busy events/executed inst) 44110352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 32026 # Number of integer instruction queue reads 44210352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 12803 # Number of integer instruction queue writes 44310352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7708 # Number of integer instruction queue wakeup accesses 4448428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 4458428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 4468428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 44710352Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 8748 # Number of integer alu accesses 4488428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 44910352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 86 # Number of loads that had data forwarded from stores 4508428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 45110352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1380 # Number of loads squashed 45210352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 45310242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 45410352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 288 # Number of stores squashed 4558428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4568428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4578428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 45810352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 4598428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 46010352Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 400 # Number of cycles IEW is squashing 46110352Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 479 # Number of cycles IEW is blocking 46210352Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking 46310352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 10879 # Number of instructions dispatched to IQ 46410352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch 46510352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2543 # Number of dispatched load instructions 46610352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1213 # Number of dispatched store instructions 4679729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 46810352Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 46910352Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 47010242Ssteve.reinhardt@amd.comsystem.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 47110352Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly 47210352Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly 47310352Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 464 # Number of branch mispredicts detected at execute 47410352Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 8213 # Number of executed instructions 47510352Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2257 # Number of load instructions executed 47610352Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 335 # Number of squashed instructions skipped in execute 4778428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 47810352Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1568 # number of nop insts executed 47910352Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3348 # number of memory reference insts executed 48010352Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1425 # Number of branches executed 48110352Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1091 # Number of stores executed 48210352Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.190010 # Inst execution rate 48310352Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 7817 # cumulative count of insts sent to commit 48410352Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 7710 # cumulative count of insts written-back 48510352Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 2989 # num instructions producing a value 48610352Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 4523 # num instructions consuming a value 4878428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 48810352Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.178373 # insts written-back per cycle 48910352Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.660845 # average fanout of values written-back 4908428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 49110352Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 5063 # The number of squashed insts skipped by commit 4928428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 49310352Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 392 # The number of times a branch was mispredicted 49410352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13824 # Number of insts commited each cycle 49510352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.420501 # Number of insts commited each cycle 49610352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.238844 # Number of insts commited each cycle 4978428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 49810352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 11590 83.84% 83.84% # Number of insts commited each cycle 49910352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 886 6.41% 90.25% # Number of insts commited each cycle 50010352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 537 3.88% 94.13% # Number of insts commited each cycle 50110352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 260 1.88% 96.01% # Number of insts commited each cycle 50210352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 148 1.07% 97.08% # Number of insts commited each cycle 50310352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 189 1.37% 98.45% # Number of insts commited each cycle 50410352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 68 0.49% 98.94% # Number of insts commited each cycle 50510352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 40 0.29% 99.23% # Number of insts commited each cycle 50610352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 106 0.77% 100.00% # Number of insts commited each cycle 5078428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5088428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5098428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 51010352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13824 # Number of insts commited each cycle 5119150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5813 # Number of instructions committed 5129150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 5138428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5149150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2088 # Number of memory references committed 5159150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1163 # Number of loads committed 5168428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 5179150SAli.Saidi@ARM.comsystem.cpu.commit.branches 915 # Number of branches committed 5188428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 5199150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 5111 # Number of committed integer instructions. 5208428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 52110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction 52210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction 52310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction 52410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction 52510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction 52610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction 52710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction 52810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction 52910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction 53010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction 53110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction 53210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction 53310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction 53410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction 53510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction 53610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction 53710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction 53810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction 53910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction 54010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction 54110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction 54210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction 54310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction 54410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction 54510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction 54610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction 54710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction 54810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction 54910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction 55010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction 55110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction 55210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction 55310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 55410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 55510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 5813 # Class of committed instruction 55610352Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 5578428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 55810352Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 24581 # The number of ROB reads 55910352Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 22642 # The number of ROB writes 56010352Sandreas.hansson@arm.comsystem.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself 56110352Sandreas.hansson@arm.comsystem.cpu.idleCycles 28521 # Total number of cycles that the CPU has spent unscheduled due to idling 5629150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5156 # Number of Instructions Simulated 5639150SAli.Saidi@ARM.comsystem.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 56410352Sandreas.hansson@arm.comsystem.cpu.cpi 8.383243 # CPI: Cycles Per Instruction 56510352Sandreas.hansson@arm.comsystem.cpu.cpi_total 8.383243 # CPI: Total CPI of All Threads 56610352Sandreas.hansson@arm.comsystem.cpu.ipc 0.119286 # IPC: Instructions Per Cycle 56710352Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.119286 # IPC: Total IPC of All Threads 56810352Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 11114 # number of integer regfile reads 56910352Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 5412 # number of integer regfile writes 5708428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 5718428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 57210352Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 164 # number of misc regfile reads 57310352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 431 # Transaction distribution 57410352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 431 # Transaction distribution 5759729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 5769729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 57710352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 680 # Packet count per connected master and slave (bytes) 57810352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 57910352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 58010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) 58110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 58210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 58310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 58410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram 58510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 58610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 58710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 58810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 58910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram 59010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 59110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 59210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 59310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 59410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram 59510352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) 5969729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 59710352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 575000 # Layer occupancy (ticks) 59810352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 59910352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) 60010352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 6019838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 17 # number of replacements 60210409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 161.371303 # Cycle average of tags in use 60310352Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1615 # Total number of references to valid blocks. 60410352Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 340 # Sample count of references to valid blocks. 60510352Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 4.750000 # Average number of references to valid blocks. 6069838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 60710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 161.371303 # Average occupied blocks per requestor 60810409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.078795 # Average percentage of cache occupancy 60910409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.078795 # Average percentage of cache occupancy 61010352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 323 # Occupied blocks per task id 61110352Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 61210352Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id 61310352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.157715 # Percentage of cache occupancy per task id 61410352Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 4476 # Number of tag accesses 61510352Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 4476 # Number of data accesses 61610352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1615 # number of ReadReq hits 61710352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1615 # number of ReadReq hits 61810352Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1615 # number of demand (read+write) hits 61910352Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1615 # number of demand (read+write) hits 62010352Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1615 # number of overall hits 62110352Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1615 # number of overall hits 62210352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses 62310352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses 62410352Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses 62510352Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses 62610352Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses 62710352Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 453 # number of overall misses 62810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 31446500 # number of ReadReq miss cycles 62910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 31446500 # number of ReadReq miss cycles 63010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 31446500 # number of demand (read+write) miss cycles 63110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 31446500 # number of demand (read+write) miss cycles 63210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 31446500 # number of overall miss cycles 63310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 31446500 # number of overall miss cycles 63410352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) 63510352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) 63610352Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses 63710352Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses 63810352Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses 63910352Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses 64010352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219052 # miss rate for ReadReq accesses 64110352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.219052 # miss rate for ReadReq accesses 64210352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.219052 # miss rate for demand accesses 64310352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.219052 # miss rate for demand accesses 64410352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.219052 # miss rate for overall accesses 64510352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.219052 # miss rate for overall accesses 64610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69418.322296 # average ReadReq miss latency 64710409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 69418.322296 # average ReadReq miss latency 64810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency 64910409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 69418.322296 # average overall miss latency 65010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency 65110409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 69418.322296 # average overall miss latency 65210352Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked 6538428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6549322Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 6558428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 65610352Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked 6578983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6588428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6598428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 6609978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits 6619978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits 6629978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits 6639978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits 6649978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 6659978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 66610352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses 66710352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses 66810352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses 66910352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses 67010352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses 67110352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses 67210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24622500 # number of ReadReq MSHR miss cycles 67310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 24622500 # number of ReadReq MSHR miss cycles 67410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 24622500 # number of demand (read+write) MSHR miss cycles 67510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 24622500 # number of demand (read+write) MSHR miss cycles 67610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 24622500 # number of overall MSHR miss cycles 67710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 24622500 # number of overall MSHR miss cycles 67810352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for ReadReq accesses 67910352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.164410 # mshr miss rate for ReadReq accesses 68010352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for demand accesses 68110352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.164410 # mshr miss rate for demand accesses 68210352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for overall accesses 68310352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.164410 # mshr miss rate for overall accesses 68410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72419.117647 # average ReadReq mshr miss latency 68510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72419.117647 # average ReadReq mshr miss latency 68610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency 68710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency 68810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency 68910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency 6908428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6919838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 69210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 222.296900 # Cycle average of tags in use 6939838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 69410352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 428 # Sample count of references to valid blocks. 69510352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.007009 # Average number of references to valid blocks. 6969838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 69710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 163.611488 # Average occupied blocks per requestor 69810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 58.685412 # Average occupied blocks per requestor 69910352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004993 # Average percentage of cache occupancy 70010352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001791 # Average percentage of cache occupancy 70110352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006784 # Average percentage of cache occupancy 70210352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 428 # Occupied blocks per task id 70310352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 70410352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id 70510352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.013062 # Percentage of cache occupancy per task id 70610352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 4335 # Number of tag accesses 70710352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 4335 # Number of data accesses 7089348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 7099348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 7109348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 7119348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 7129348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 7139348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 71410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses 71510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 71610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 428 # number of ReadReq misses 7179348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 7189348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 71910352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses 72010352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 72110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 479 # number of demand (read+write) misses 72210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses 72310352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 72410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 479 # number of overall misses 72510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24252500 # number of ReadReq miss cycles 72610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7286250 # number of ReadReq miss cycles 72710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 31538750 # number of ReadReq miss cycles 72810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4056000 # number of ReadExReq miss cycles 72910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 4056000 # number of ReadExReq miss cycles 73010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 24252500 # number of demand (read+write) miss cycles 73110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 11342250 # number of demand (read+write) miss cycles 73210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 35594750 # number of demand (read+write) miss cycles 73310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 24252500 # number of overall miss cycles 73410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 11342250 # number of overall miss cycles 73510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 35594750 # number of overall miss cycles 73610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) 73710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 73810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 431 # number of ReadReq accesses(hits+misses) 7399348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 7409348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 74110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses 74210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 74310352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 482 # number of demand (read+write) accesses 74410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 340 # number of overall (read+write) accesses 74510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 74610352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 482 # number of overall (read+write) accesses 74710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991176 # miss rate for ReadReq accesses 7489348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 74910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.993039 # miss rate for ReadReq accesses 7509348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 7519348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 75210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991176 # miss rate for demand accesses 7539348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 75410352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.993776 # miss rate for demand accesses 75510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991176 # miss rate for overall accesses 7569348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 75710352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.993776 # miss rate for overall accesses 75810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71965.875371 # average ReadReq miss latency 75910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80068.681319 # average ReadReq miss latency 76010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 73688.668224 # average ReadReq miss latency 76110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79529.411765 # average ReadExReq miss latency 76210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 79529.411765 # average ReadExReq miss latency 76310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency 76410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 79875 # average overall miss latency 76510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 74310.542797 # average overall miss latency 76610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency 76710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 79875 # average overall miss latency 76810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 74310.542797 # average overall miss latency 7699348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7709348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7719348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 7729348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 7739348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7749348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7759348SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7769348SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 77710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses 77810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 77910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 7809348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 7819348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 78210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses 78310352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 78410352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 479 # number of demand (read+write) MSHR misses 78510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses 78610352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 78710352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 479 # number of overall MSHR misses 78810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19997500 # number of ReadReq MSHR miss cycles 78910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6166250 # number of ReadReq MSHR miss cycles 79010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 26163750 # number of ReadReq MSHR miss cycles 79110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3421500 # number of ReadExReq MSHR miss cycles 79210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3421500 # number of ReadExReq MSHR miss cycles 79310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19997500 # number of demand (read+write) MSHR miss cycles 79410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9587750 # number of demand (read+write) MSHR miss cycles 79510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 29585250 # number of demand (read+write) MSHR miss cycles 79610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19997500 # number of overall MSHR miss cycles 79710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9587750 # number of overall MSHR miss cycles 79810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 29585250 # number of overall MSHR miss cycles 79910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for ReadReq accesses 8009348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 80110352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993039 # mshr miss rate for ReadReq accesses 8029348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 8039348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 80410352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for demand accesses 8059348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 80610352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993776 # mshr miss rate for demand accesses 80710352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for overall accesses 8089348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 80910352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993776 # mshr miss rate for overall accesses 81010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59339.762611 # average ReadReq mshr miss latency 81110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67760.989011 # average ReadReq mshr miss latency 81210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61130.257009 # average ReadReq mshr miss latency 81310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67088.235294 # average ReadExReq mshr miss latency 81410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67088.235294 # average ReadExReq mshr miss latency 81510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency 81610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency 81710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency 81810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency 81910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency 82010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency 8219348SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 8229838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 82310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 92.429669 # Cycle average of tags in use 82410352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2508 # Total number of references to valid blocks. 82510352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 82610352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 17.661972 # Average number of references to valid blocks. 8279838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 82810409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 92.429669 # Average occupied blocks per requestor 82910352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.022566 # Average percentage of cache occupancy 83010352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.022566 # Average percentage of cache occupancy 83110352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 83210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 83310352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id 83410352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id 83510352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 6220 # Number of tag accesses 83610352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 6220 # Number of data accesses 83710352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1945 # number of ReadReq hits 83810352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1945 # number of ReadReq hits 8399729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 8409729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 84110352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2508 # number of demand (read+write) hits 84210352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2508 # number of demand (read+write) hits 84310352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2508 # number of overall hits 84410352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2508 # number of overall hits 84510352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses 84610352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses 8479729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 8489729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 84910352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 531 # number of demand (read+write) misses 85010352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 531 # number of demand (read+write) misses 85110352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 531 # number of overall misses 85210352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 531 # number of overall misses 85310409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11707000 # number of ReadReq miss cycles 85410409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11707000 # number of ReadReq miss cycles 85510409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 23264249 # number of WriteReq miss cycles 85610409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 23264249 # number of WriteReq miss cycles 85710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 34971249 # number of demand (read+write) miss cycles 85810409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 34971249 # number of demand (read+write) miss cycles 85910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 34971249 # number of overall miss cycles 86010409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 34971249 # number of overall miss cycles 86110352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2114 # number of ReadReq accesses(hits+misses) 86210352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 2114 # number of ReadReq accesses(hits+misses) 8638835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 8648835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 86510352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 3039 # number of demand (read+write) accesses 86610352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 3039 # number of demand (read+write) accesses 86710352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 3039 # number of overall (read+write) accesses 86810352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 3039 # number of overall (read+write) accesses 86910352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079943 # miss rate for ReadReq accesses 87010352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.079943 # miss rate for ReadReq accesses 8719729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 8729729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 87310352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.174729 # miss rate for demand accesses 87410352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.174729 # miss rate for demand accesses 87510352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.174729 # miss rate for overall accesses 87610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.174729 # miss rate for overall accesses 87710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349 # average ReadReq miss latency 87810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349 # average ReadReq miss latency 87910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215 # average WriteReq miss latency 88010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215 # average WriteReq miss latency 88110409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency 88210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 65859.225989 # average overall miss latency 88310409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency 88410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 65859.225989 # average overall miss latency 88510352Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked 8868428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8879322Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 8888428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 88910352Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked 8908983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8918428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8928428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 89310352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 89410352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 8959729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 8969729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 89710352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 389 # number of demand (read+write) MSHR hits 89810352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 389 # number of demand (read+write) MSHR hits 89910352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 389 # number of overall MSHR hits 90010352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 389 # number of overall MSHR hits 90110352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 90210352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 9038835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 9048835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 90510352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 90610352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 90710352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 90810352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 90910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7380750 # number of ReadReq MSHR miss cycles 91010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7380750 # number of ReadReq MSHR miss cycles 91110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4107999 # number of WriteReq MSHR miss cycles 91210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4107999 # number of WriteReq MSHR miss cycles 91310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 11488749 # number of demand (read+write) MSHR miss cycles 91410409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 11488749 # number of demand (read+write) MSHR miss cycles 91510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 11488749 # number of overall MSHR miss cycles 91610409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 11488749 # number of overall MSHR miss cycles 91710352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043046 # mshr miss rate for ReadReq accesses 91810352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses 9198835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 9209055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 92110352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for demand accesses 92210352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.046726 # mshr miss rate for demand accesses 92310352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for overall accesses 92410352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.046726 # mshr miss rate for overall accesses 92510409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average ReadReq mshr miss latency 92610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857 # average ReadReq mshr miss latency 92710409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80549 # average WriteReq mshr miss latency 92810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80549 # average WriteReq mshr miss latency 92910409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency 93010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency 93110409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency 93210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency 9338428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 9346039SN/A 9356039SN/A---------- End Simulation Statistics ---------- 936