stats.txt revision 10220
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39729Sandreas.hansson@arm.comsim_seconds 0.000022 # Number of seconds simulated 410220Sandreas.hansson@arm.comsim_ticks 21843500 # Number of ticks simulated 510220Sandreas.hansson@arm.comfinal_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710220Sandreas.hansson@arm.comhost_inst_rate 63396 # Simulator instruction rate (inst/s) 810220Sandreas.hansson@arm.comhost_op_rate 63384 # Simulator op (including micro ops) rate (op/s) 910220Sandreas.hansson@arm.comhost_tick_rate 268482897 # Simulator tick rate (ticks/s) 1010220Sandreas.hansson@arm.comhost_mem_usage 267540 # Number of bytes of host memory used 1110220Sandreas.hansson@arm.comhost_seconds 0.08 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5156 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5156 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 179490Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 189797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 30528 # Number of bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 209797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 219797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 229490Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 239797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 477 # Number of read requests responded to by this memory 2410220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s) 2510220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s) 2610220Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s) 2710220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s) 2810220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s) 2910220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s) 3010220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s) 3110220Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s) 329978Sandreas.hansson@arm.comsystem.physmem.readReqs 477 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 369978Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 399978Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 30528 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 30 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 0 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 1 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 0 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 7 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 3 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 13 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 54 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 63 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 77 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 44 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 20 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 51 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 29 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 77 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 8 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810220Sandreas.hansson@arm.comsystem.physmem.totGap 21764000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 477 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see 9410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see 959978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 9610220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 9710220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 989322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation 19010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation 19110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation 19210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation 19310220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation 19410220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation 19510220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation 19610220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation 19710220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation 19810220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation 19910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation 20010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation 20110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation 20210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation 20310220Sandreas.hansson@arm.comsystem.physmem.totQLat 4715500 # Total ticks spent queuing 20410220Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM 2059978Sandreas.hansson@arm.comsystem.physmem.totBusLat 2385000 # Total ticks spent in databus transfers 20610220Sandreas.hansson@arm.comsystem.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20810220Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst 20910220Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21110220Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21410220Sandreas.hansson@arm.comsystem.physmem.busUtil 10.92 # Data bus utilization in percentage 21510220Sandreas.hansson@arm.comsystem.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710148Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21910148Sandreas.hansson@arm.comsystem.physmem.readRowHits 357 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22110148Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22310220Sandreas.hansson@arm.comsystem.physmem.avgGap 45626.83 # Average gap between requests 22410148Sandreas.hansson@arm.comsystem.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined 22510220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 11000 # Time in different power states 22610220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 520000 # Time in different power states 22710220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 22810220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 15319000 # Time in different power states 22910220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 23010220Sandreas.hansson@arm.comsystem.membus.throughput 1397578227 # Throughput (bytes/s) 2319797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 426 # Transaction distribution 2329797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 426 # Transaction distribution 2339729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 51 # Transaction distribution 2349729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 51 # Transaction distribution 2359838Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) 2369838Sandreas.hansson@arm.comsystem.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) 2379838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) 2389838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) 2399797Sandreas.hansson@arm.comsystem.membus.data_through_bus 30528 # Total data (bytes) 2409729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 24110220Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks) 2429797Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 24310220Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks) 24410220Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 20.5 # Layer utilization (%) 24510036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2469978Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2174 # Number of BP lookups 2479797Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted 2489729Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect 2499978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups 2509978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 492 # Number of BTB hits 2519481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2529978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage 2539797Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. 2549797Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. 2558428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2568428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2578428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2588428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2598428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2608428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2616039SN/Asystem.cpu.dtb.hits 0 # DTB hits 2626039SN/Asystem.cpu.dtb.misses 0 # DTB misses 2638428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2648428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2658428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2668428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2678428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2688428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2698428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2708428SN/Asystem.cpu.itb.hits 0 # DTB hits 2718428SN/Asystem.cpu.itb.misses 0 # DTB misses 2728428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 2738428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 27410220Sandreas.hansson@arm.comsystem.cpu.numCycles 43688 # number of cpu cycles simulated 2758428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2768428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 27710148Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss 2789978Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 13183 # Number of instructions fetch has processed 2799978Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2174 # Number of branches that fetch encountered 2809978Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken 2819978Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked 2829978Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing 28310220Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked 2849322Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 2859978Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1965 # Number of cache lines fetched 2869978Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed 28710220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total) 28810220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total) 28910220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total) 2906291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 29110220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total) 29210220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total) 29310220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total) 29410220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total) 29510148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total) 29610148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total) 29710148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total) 29810148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total) 29910148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total) 3006291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3016291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3026291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 30310220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total) 30410220Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle 30510220Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle 30610148Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle 30710220Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked 3089988Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 3025 # Number of cycles decode is running 3099729Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking 3109978Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing 3119978Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch 3129797Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 3139988Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode 3149490Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode 3159978Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing 31610148Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle 31710220Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking 31810220Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst 3199988Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 2898 # Number of cycles rename is running 3209729Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking 3219988Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename 3229729Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 3239490Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 3249729Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full 3259988Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed 3269988Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made 3279988Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups 3289924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 3299150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 3309988Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing 3319797Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 16 # count of serializing insts renamed 3329797Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 3339797Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 328 # count of insts added to the skid buffer 3349978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit. 3359729Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. 3368428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 3378428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 3389978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) 3399729Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 3409978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8293 # Number of instructions issued 3419797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued 3429978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling 3439978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph 3449729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 34510220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle 34610220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle 34710220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle 3488428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 34910220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle 35010220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle 35110220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle 35210220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle 35310148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle 35410148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle 35510148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle 3569978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle 3579729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle 3588428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3598428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3608428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 36110220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle 3628428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3639797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available 3649797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available 3659797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available 3669797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available 3679797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available 3689797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available 3699797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available 3709797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available 3719797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 3729797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available 3739797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available 3749797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available 3759797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available 3769797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available 3779797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available 3789797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available 3799797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available 3809797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available 3819797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available 3829797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available 3839797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available 3849797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available 3859797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available 3869797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available 3879797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available 3889797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available 3899797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available 3909797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available 3919797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 3929797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available 3939797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available 3948428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3958428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3968241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 3979978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued 3989978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued 3999978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued 4009978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued 4019978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued 4029978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued 4039978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued 4049978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued 4059978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued 4069978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued 4079978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued 4089978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued 4099978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued 4109978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued 4119978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued 4129978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued 4139978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued 4149978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued 4159978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued 4169978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued 4179978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued 4189978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued 4199978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued 4209978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued 4219978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued 4229978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued 4239978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued 4249978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued 4259978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued 4269978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued 4279978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued 4288241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4298241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4309978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8293 # Type of FU issued 43110220Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.189823 # Inst issue rate 4329797Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 160 # FU busy when requested 4339978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) 43410220Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads 4359978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes 4369978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses 4378428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 4388428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 4398428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 4409978Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses 4418428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 4429729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores 4438428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4449978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed 4459322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 4469490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 4479729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed 4488428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4498428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4508428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 4519978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked 4528428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4539978Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing 4549797Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking 4559797Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 4569978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ 4579988Snilay@cs.wisc.edusystem.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch 4589978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions 4599729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions 4609729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 4619797Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 4629322Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4639490Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 4649797Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 4659797Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly 4669797Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute 4679978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions 4689978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed 4699797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute 4708428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4719978Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1512 # number of nop insts executed 4729978Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3186 # number of memory reference insts executed 4739978Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1344 # Number of branches executed 4749797Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1079 # Number of stores executed 47510220Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.181102 # Inst execution rate 4769978Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit 4779978Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 7455 # cumulative count of insts written-back 4789797Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 2921 # num instructions producing a value 4799797Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 4197 # num instructions consuming a value 4808428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 48110220Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.170642 # insts written-back per cycle 4829797Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back 4838428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4849978Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit 4858428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 4869797Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted 48710220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle 48810220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle 48910220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle 4908428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 49110220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle 49210148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle 49310148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle 49410148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle 49510148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle 49610148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle 4979797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle 4989797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle 4999729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle 5008428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5018428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5028428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 50310220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle 5049150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5813 # Number of instructions committed 5059150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 5068428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5079150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2088 # Number of memory references committed 5089150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1163 # Number of loads committed 5098428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 5109150SAli.Saidi@ARM.comsystem.cpu.commit.branches 915 # Number of branches committed 5118428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 5129150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 5111 # Number of committed integer instructions. 5138428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 51410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction 51510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction 51610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction 51710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction 51810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction 51910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction 52010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction 52110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction 52210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction 52310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction 52410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction 52510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction 52610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction 52710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction 52810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction 52910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction 53010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction 53110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction 53210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction 53310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction 53410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction 53510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction 53610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction 53710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction 53810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction 53910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction 54010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction 54110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction 54210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction 54310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction 54410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction 54510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction 54610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 54710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 54810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 5813 # Class of committed instruction 5499729Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 5508428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 55110220Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 24239 # The number of ROB reads 5529978Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 22333 # The number of ROB writes 55310220Sandreas.hansson@arm.comsystem.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself 55410220Sandreas.hansson@arm.comsystem.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling 5559150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5156 # Number of Instructions Simulated 5569150SAli.Saidi@ARM.comsystem.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 5579150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 5156 # Number of Instructions Simulated 55810220Sandreas.hansson@arm.comsystem.cpu.cpi 8.473235 # CPI: Cycles Per Instruction 55910220Sandreas.hansson@arm.comsystem.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads 56010220Sandreas.hansson@arm.comsystem.cpu.ipc 0.118019 # IPC: Instructions Per Cycle 56110220Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads 5629978Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 10743 # number of integer regfile reads 5639978Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 5234 # number of integer regfile writes 5648428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 5658428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 5669729Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 148 # number of misc regfile reads 56710220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s) 5689797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution 5699797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution 5709729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 5719729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 5729838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) 5739838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 5749838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 5759838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) 5769838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 5779838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) 5789797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) 5799729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 5809797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 5819729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 58210220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks) 5839797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 58410220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) 5859978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 5869838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 17 # number of replacements 58710220Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use 5889978Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. 5899838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. 5909978Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. 5919838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 59210220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor 59310220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy 59410220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy 59510036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id 59610036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id 59710036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 59810036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id 59910036SAli.Saidi@ARM.comsystem.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses 60010036SAli.Saidi@ARM.comsystem.cpu.icache.tags.data_accesses 4268 # Number of data accesses 6019978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits 6029978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits 6039978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits 6049978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits 6059978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits 6069978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1514 # number of overall hits 6079978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses 6089978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses 6099978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses 6109978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses 6119978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses 6129978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 451 # number of overall misses 61310220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles 61410220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles 61510220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles 61610220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles 61710220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles 61810220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles 6199978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) 6209978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) 6219978Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses 6229978Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses 6239978Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses 6249978Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses 6259978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses 6269978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses 6279978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses 6289978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses 6299978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses 6309978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses 63110220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency 63210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency 63310220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency 63410220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency 63510220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency 63610220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency 6379797Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked 6388428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6399322Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 6408428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 6419797Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked 6428983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6438428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6448428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 6459978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits 6469978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits 6479978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits 6489978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits 6499978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 6509978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 6519797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 6529797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 6539797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 6549797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 6559797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 6569797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses 65710220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles 65810220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles 65910220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles 66010220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles 66110220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles 66210220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles 6639978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses 6649978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses 6659978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses 6669978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses 6679978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses 6689978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses 66910220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency 67010220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency 67110220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency 67210220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency 67310220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency 67410220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency 6758428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6769838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 67710220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use 6789838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 6799838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 6809838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 6819838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 68210220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor 68310220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor 68410148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy 68510148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy 68610220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy 68710036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id 68810148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 68910148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 69010036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id 69110036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses 69210036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses 6939348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 6949348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 6959348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 6969348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 6979348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 6989348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 6999797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 7009490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 7019797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 426 # number of ReadReq misses 7029348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 7039348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 7049797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 7059490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 7069797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses 7079797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 7089490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 7099797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 477 # number of overall misses 71010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles 71110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles 71210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles 71310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles 71410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles 71510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles 71610220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles 71710220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles 71810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles 71910220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles 72010220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles 7219797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 7229490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 7239797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) 7249348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 7259348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 7269797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 7279490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 7289797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses 7299797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses 7309490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 7319797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 480 # number of overall (read+write) accesses 7329797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses 7339348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 7349797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.993007 # miss rate for ReadReq accesses 7359348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 7369348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 7379797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses 7389348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 7399797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses 7409797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 7419348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 7429797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses 74310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency 74410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency 74510220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency 74610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency 74710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency 74810220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency 74910220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency 75010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency 75110220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency 75210220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency 75310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency 7549348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7559348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7569348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 7579348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 7589348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7599348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7609348SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7619348SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 7629797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 7639490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 7649797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses 7659348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 7669348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 7679797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 7689490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 7699797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses 7709797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 7719490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 7729797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses 77310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles 77410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles 77510220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles 77610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles 77710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles 77810220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles 77910220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles 78010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles 78110220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles 78210220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles 78310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles 7849797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses 7859348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 7869797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses 7879348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 7889348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 7899797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses 7909348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 7919797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses 7929797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses 7939348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 7949797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses 79510220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency 79610220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency 79710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency 79810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency 79910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency 80010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency 80110220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency 80210220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency 80310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency 80410220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency 80510220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency 8069348SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 8079838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 80810220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use 8099838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 8109838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 8119838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. 8129838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 81310220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor 81410220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy 81510220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy 81610036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 81710036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 81810036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 81910036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id 82010036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses 82110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.data_accesses 5952 # Number of data accesses 8229797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits 8239797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits 8249729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 8259729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 8269797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 8279797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 8289797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 8299797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2395 # number of overall hits 8309797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 8319797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 8329729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 8339729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 8349797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses 8359797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses 8369797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses 8379797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 510 # number of overall misses 83810220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles 83910220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles 84010220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles 84110220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles 84210220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles 84310220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles 84410220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles 84510220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles 8469797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) 8479797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) 8488835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 8498835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 8509797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses 8519797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses 8529797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses 8539797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses 8549797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses 8559797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses 8569729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 8579729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 8589797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses 8599797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses 8609797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses 8619797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses 86210220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency 86310220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency 86410220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency 86510220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency 86610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency 86710220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency 86810220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency 86910220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency 87010220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked 8718428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8729322Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 8738428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 87410220Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked 8758983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8768428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8778428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8789797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 8799797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 8809729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 8819729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 8829797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits 8839797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits 8849797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits 8859797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits 8869490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 8879490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 8888835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 8898835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 8909490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 8919490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 8929490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 8939490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 89410220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles 89510220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles 89610220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles 89710220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles 89810220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles 89910220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles 90010220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles 90110220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles 9029797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses 9039797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses 9048835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 9059055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 9069797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses 9079797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses 9089797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses 9099797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses 91010220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency 91110220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency 91210220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency 91310220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency 91410220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency 91510220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency 91610220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency 91710220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency 9188428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 9196039SN/A 9206039SN/A---------- End Simulation Statistics ---------- 921