stats.txt revision 10148
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 39729Sandreas.hansson@arm.comsim_seconds 0.000022 # Number of seconds simulated 410148Sandreas.hansson@arm.comsim_ticks 21918500 # Number of ticks simulated 510148Sandreas.hansson@arm.comfinal_tick 21918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710148Sandreas.hansson@arm.comhost_inst_rate 56826 # Simulator instruction rate (inst/s) 810148Sandreas.hansson@arm.comhost_op_rate 56817 # Simulator op (including micro ops) rate (op/s) 910148Sandreas.hansson@arm.comhost_tick_rate 241494238 # Simulator tick rate (ticks/s) 1010148Sandreas.hansson@arm.comhost_mem_usage 266500 # Number of bytes of host memory used 1110148Sandreas.hansson@arm.comhost_seconds 0.09 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5156 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5156 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 179490Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 189797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 30528 # Number of bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 209797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 219797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 229490Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 239797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 477 # Number of read requests responded to by this memory 2410148Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 978169127 # Total read bandwidth from this memory (bytes/s) 2510148Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 414626913 # Total read bandwidth from this memory (bytes/s) 2610148Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1392796040 # Total read bandwidth from this memory (bytes/s) 2710148Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 978169127 # Instruction read bandwidth from this memory (bytes/s) 2810148Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 978169127 # Instruction read bandwidth from this memory (bytes/s) 2910148Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 978169127 # Total bandwidth to/from this memory (bytes/s) 3010148Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 414626913 # Total bandwidth to/from this memory (bytes/s) 3110148Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1392796040 # Total bandwidth to/from this memory (bytes/s) 329978Sandreas.hansson@arm.comsystem.physmem.readReqs 477 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 369978Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 399978Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 30528 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 30 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 0 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 1 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 0 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 7 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 3 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 13 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 54 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 63 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 77 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 44 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 20 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 51 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 29 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 77 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 8 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810148Sandreas.hansson@arm.comsystem.physmem.totGap 21839000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 477 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see 949978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see 959978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 969978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 979978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 989322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation 19010148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation 19110148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 168.540369 # Bytes accessed per row activation 19210148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 250.647056 # Bytes accessed per row activation 19310148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 26 29.89% 29.89% # Bytes accessed per row activation 19410148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 32 36.78% 66.67% # Bytes accessed per row activation 19510148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 13 14.94% 81.61% # Bytes accessed per row activation 19610148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 6 6.90% 88.51% # Bytes accessed per row activation 19710148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2 2.30% 90.80% # Bytes accessed per row activation 19810148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1 1.15% 91.95% # Bytes accessed per row activation 19910148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 2 2.30% 94.25% # Bytes accessed per row activation 20010148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 5 5.75% 100.00% # Bytes accessed per row activation 20110148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation 20210148Sandreas.hansson@arm.comsystem.physmem.totQLat 2715000 # Total ticks spent queuing 20310148Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 13776250 # Total ticks spent from burst creation until serviced by the DRAM 2049978Sandreas.hansson@arm.comsystem.physmem.totBusLat 2385000 # Total ticks spent in databus transfers 20510148Sandreas.hansson@arm.comsystem.physmem.totBankLat 8676250 # Total ticks spent accessing banks 20610148Sandreas.hansson@arm.comsystem.physmem.avgQLat 5691.82 # Average queueing delay per DRAM burst 20710148Sandreas.hansson@arm.comsystem.physmem.avgBankLat 18189.20 # Average bank access latency per DRAM burst 2089978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20910148Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 28881.03 # Average memory access latency per DRAM burst 21010148Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1392.80 # Average DRAM read bandwidth in MiByte/s 2119978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21210148Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1392.80 # Average system read bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2149978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21510148Sandreas.hansson@arm.comsystem.physmem.busUtil 10.88 # Data bus utilization in percentage 21610148Sandreas.hansson@arm.comsystem.physmem.busUtilRead 10.88 # Data bus utilization in percentage for reads 2179978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21810148Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing 2199978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22010148Sandreas.hansson@arm.comsystem.physmem.readRowHits 357 # Number of row buffer hits during reads 2219312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22210148Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads 2239312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22410148Sandreas.hansson@arm.comsystem.physmem.avgGap 45784.07 # Average gap between requests 22510148Sandreas.hansson@arm.comsystem.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined 2269978Sandreas.hansson@arm.comsystem.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state 22710148Sandreas.hansson@arm.comsystem.membus.throughput 1392796040 # Throughput (bytes/s) 2289797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 426 # Transaction distribution 2299797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 426 # Transaction distribution 2309729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 51 # Transaction distribution 2319729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 51 # Transaction distribution 2329838Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) 2339838Sandreas.hansson@arm.comsystem.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) 2349838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) 2359838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) 2369797Sandreas.hansson@arm.comsystem.membus.data_through_bus 30528 # Total data (bytes) 2379729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 2389988Snilay@cs.wisc.edusystem.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) 2399797Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 24010148Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4473250 # Layer occupancy (ticks) 2419978Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 20.4 # Layer utilization (%) 24210036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2439978Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2174 # Number of BP lookups 2449797Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted 2459729Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect 2469978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups 2479978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 492 # Number of BTB hits 2489481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2499978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage 2509797Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. 2519797Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. 2528428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2538428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2548428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2558428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2568428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2578428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2586039SN/Asystem.cpu.dtb.hits 0 # DTB hits 2596039SN/Asystem.cpu.dtb.misses 0 # DTB misses 2608428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2618428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2628428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2638428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2648428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2658428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2668428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2678428SN/Asystem.cpu.itb.hits 0 # DTB hits 2688428SN/Asystem.cpu.itb.misses 0 # DTB misses 2698428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 2708428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 27110148Sandreas.hansson@arm.comsystem.cpu.numCycles 43838 # number of cpu cycles simulated 2728428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2738428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 27410148Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss 2759978Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 13183 # Number of instructions fetch has processed 2769978Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2174 # Number of branches that fetch encountered 2779978Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken 2789978Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked 2799978Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing 28010148Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 1408 # Number of cycles fetch has spent blocked 2819322Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 2829978Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1965 # Number of cache lines fetched 2839978Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed 28410148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14505 # Number of instructions fetched each cycle (Total) 28510148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.908859 # Number of instructions fetched each cycle (Total) 28610148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.220900 # Number of instructions fetched each cycle (Total) 2876291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 28810148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 11292 77.85% 77.85% # Number of instructions fetched each cycle (Total) 28910148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 1317 9.08% 86.93% # Number of instructions fetched each cycle (Total) 29010148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 104 0.72% 87.65% # Number of instructions fetched each cycle (Total) 29110148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 131 0.90% 88.55% # Number of instructions fetched each cycle (Total) 29210148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total) 29310148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total) 29410148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total) 29510148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total) 29610148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total) 2976291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2986291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2996291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 30010148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14505 # Number of instructions fetched each cycle (Total) 30110148Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.049592 # Number of branch fetches per cycle 30210148Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.300721 # Number of inst fetches per cycle 30310148Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle 30410148Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 1660 # Number of cycles decode is blocked 3059988Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 3025 # Number of cycles decode is running 3069729Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking 3079978Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing 3089978Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch 3099797Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 3109988Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode 3119490Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode 3129978Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing 31310148Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle 3149797Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking 31510148Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst 3169988Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 2898 # Number of cycles rename is running 3179729Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking 3189988Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename 3199729Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 3209490Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 3219729Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full 3229988Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed 3239988Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made 3249988Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups 3259924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 3269150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 3279988Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing 3289797Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 16 # count of serializing insts renamed 3299797Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 3309797Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 328 # count of insts added to the skid buffer 3319978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit. 3329729Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. 3338428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 3348428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 3359978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) 3369729Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 3379978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8293 # Number of instructions issued 3389797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued 3399978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling 3409978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph 3419729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 34210148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14505 # Number of insts issued each cycle 34310148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.571734 # Number of insts issued each cycle 34410148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.240341 # Number of insts issued each cycle 3458428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 34610148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10922 75.30% 75.30% # Number of insts issued each cycle 34710148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1422 9.80% 85.10% # Number of insts issued each cycle 34810148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 891 6.14% 91.24% # Number of insts issued each cycle 34910148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 553 3.81% 95.06% # Number of insts issued each cycle 35010148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle 35110148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle 35210148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle 3539978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle 3549729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle 3558428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3568428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3578428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 35810148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14505 # Number of insts issued each cycle 3598428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3609797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available 3619797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available 3629797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available 3639797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available 3649797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available 3659797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available 3669797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available 3679797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available 3689797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 3699797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available 3709797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available 3719797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available 3729797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available 3739797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available 3749797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available 3759797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available 3769797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available 3779797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available 3789797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available 3799797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available 3809797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available 3819797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available 3829797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available 3839797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available 3849797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available 3859797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available 3869797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available 3879797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available 3889797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available 3899797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available 3909797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available 3918428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3928428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3938241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 3949978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued 3959978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued 3969978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued 3979978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued 3989978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued 3999978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued 4009978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued 4019978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued 4029978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued 4039978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued 4049978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued 4059978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued 4069978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued 4079978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued 4089978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued 4099978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued 4109978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued 4119978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued 4129978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued 4139978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued 4149978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued 4159978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued 4169978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued 4179978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued 4189978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued 4199978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued 4209978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued 4219978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued 4229978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued 4239978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued 4249978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued 4258241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4268241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4279978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8293 # Type of FU issued 42810148Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.189174 # Inst issue rate 4299797Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 160 # FU busy when requested 4309978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) 43110148Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 31286 # Number of integer instruction queue reads 4329978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes 4339978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses 4348428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 4358428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 4368428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 4379978Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses 4388428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 4399729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores 4408428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4419978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed 4429322Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 4439490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 4449729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed 4458428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4468428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4478428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 4489978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked 4498428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4509978Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing 4519797Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking 4529797Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 4539978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ 4549988Snilay@cs.wisc.edusystem.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch 4559978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions 4569729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions 4579729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 4589797Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 4599322Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4609490Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 4619797Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 4629797Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly 4639797Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute 4649978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions 4659978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed 4669797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute 4678428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4689978Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1512 # number of nop insts executed 4699978Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3186 # number of memory reference insts executed 4709978Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1344 # Number of branches executed 4719797Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1079 # Number of stores executed 47210148Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.180483 # Inst execution rate 4739978Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit 4749978Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 7455 # cumulative count of insts written-back 4759797Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 2921 # num instructions producing a value 4769797Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 4197 # num instructions consuming a value 4778428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 47810148Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.170058 # insts written-back per cycle 4799797Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back 4808428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4819978Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit 4828428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 4839797Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted 48410148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13637 # Number of insts commited each cycle 48510148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.426267 # Number of insts commited each cycle 48610148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.206560 # Number of insts commited each cycle 4878428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 48810148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 11235 82.39% 82.39% # Number of insts commited each cycle 48910148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle 49010148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle 49110148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle 49210148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle 49310148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle 4949797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle 4959797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle 4969729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle 4978428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4988428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4998428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 50010148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13637 # Number of insts commited each cycle 5019150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5813 # Number of instructions committed 5029150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 5038428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5049150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2088 # Number of memory references committed 5059150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1163 # Number of loads committed 5068428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 5079150SAli.Saidi@ARM.comsystem.cpu.commit.branches 915 # Number of branches committed 5088428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 5099150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 5111 # Number of committed integer instructions. 5108428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 5119729Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 5128428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 51310148Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 24245 # The number of ROB reads 5149978Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 22333 # The number of ROB writes 51510148Sandreas.hansson@arm.comsystem.cpu.timesIdled 286 # Number of times that the entire CPU went into an idle state and unscheduled itself 51610148Sandreas.hansson@arm.comsystem.cpu.idleCycles 29333 # Total number of cycles that the CPU has spent unscheduled due to idling 5179150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5156 # Number of Instructions Simulated 5189150SAli.Saidi@ARM.comsystem.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 5199150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 5156 # Number of Instructions Simulated 52010148Sandreas.hansson@arm.comsystem.cpu.cpi 8.502327 # CPI: Cycles Per Instruction 52110148Sandreas.hansson@arm.comsystem.cpu.cpi_total 8.502327 # CPI: Total CPI of All Threads 52210148Sandreas.hansson@arm.comsystem.cpu.ipc 0.117615 # IPC: Instructions Per Cycle 52310148Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.117615 # IPC: Total IPC of All Threads 5249978Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 10743 # number of integer regfile reads 5259978Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 5234 # number of integer regfile writes 5268428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 5278428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 5289729Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 148 # number of misc regfile reads 52910148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1401555763 # Throughput (bytes/s) 5309797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution 5319797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution 5329729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 5339729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 5349838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) 5359838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 5369838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 5379838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) 5389838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 5399838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) 5409797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) 5419729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 5429797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 5439729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 5449978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks) 5459797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 54610148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) 5479978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 5489838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 17 # number of replacements 54910148Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 161.390328 # Cycle average of tags in use 5509978Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. 5519838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. 5529978Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. 5539838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 55410148Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 161.390328 # Average occupied blocks per requestor 55510148Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.078804 # Average percentage of cache occupancy 55610148Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.078804 # Average percentage of cache occupancy 55710036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id 55810036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id 55910036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 56010036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id 56110036SAli.Saidi@ARM.comsystem.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses 56210036SAli.Saidi@ARM.comsystem.cpu.icache.tags.data_accesses 4268 # Number of data accesses 5639978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits 5649978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits 5659978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits 5669978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits 5679978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits 5689978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1514 # number of overall hits 5699978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses 5709978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses 5719978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses 5729978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses 5739978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses 5749978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 451 # number of overall misses 57510148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 31256750 # number of ReadReq miss cycles 57610148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 31256750 # number of ReadReq miss cycles 57710148Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 31256750 # number of demand (read+write) miss cycles 57810148Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 31256750 # number of demand (read+write) miss cycles 57910148Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 31256750 # number of overall miss cycles 58010148Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 31256750 # number of overall miss cycles 5819978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) 5829978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) 5839978Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses 5849978Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses 5859978Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses 5869978Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses 5879978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses 5889978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses 5899978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses 5909978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses 5919978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses 5929978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses 59310148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373 # average ReadReq miss latency 59410148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373 # average ReadReq miss latency 59510148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency 59610148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 69305.432373 # average overall miss latency 59710148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency 59810148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 69305.432373 # average overall miss latency 5999797Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked 6008428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6019322Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 6028428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 6039797Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked 6048983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6058428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6068428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 6079978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits 6089978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits 6099978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits 6109978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits 6119978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 6129978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 6139797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 6149797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 6159797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 6169797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 6179797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 6189797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses 61910148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24262750 # number of ReadReq MSHR miss cycles 62010148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 24262750 # number of ReadReq MSHR miss cycles 62110148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 24262750 # number of demand (read+write) MSHR miss cycles 62210148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 24262750 # number of demand (read+write) MSHR miss cycles 62310148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 24262750 # number of overall MSHR miss cycles 62410148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 24262750 # number of overall MSHR miss cycles 6259978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses 6269978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses 6279978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses 6289978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses 6299978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses 6309978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses 63110148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024 # average ReadReq mshr miss latency 63210148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024 # average ReadReq mshr miss latency 63310148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency 63410148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency 63510148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency 63610148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency 6378428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6389838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 63910148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 221.496759 # Cycle average of tags in use 6409838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 6419838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 6429838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 6439838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 64410148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 163.678282 # Average occupied blocks per requestor 64510148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 57.818477 # Average occupied blocks per requestor 64610148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy 64710148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy 64810148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy 64910036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id 65010148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 65110148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 65210036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id 65310036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses 65410036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses 6559348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 6569348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 6579348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 6589348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 6599348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 6609348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 6619797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 6629490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 6639797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 426 # number of ReadReq misses 6649348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 6659348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 6669797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 6679490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 6689797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses 6699797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 6709490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 6719797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 477 # number of overall misses 67210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23894750 # number of ReadReq miss cycles 67310148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7065750 # number of ReadReq miss cycles 67410148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 30960500 # number of ReadReq miss cycles 67510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3800750 # number of ReadExReq miss cycles 67610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3800750 # number of ReadExReq miss cycles 67710148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 23894750 # number of demand (read+write) miss cycles 67810148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles 67910148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 34761250 # number of demand (read+write) miss cycles 68010148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 23894750 # number of overall miss cycles 68110148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles 68210148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 34761250 # number of overall miss cycles 6839797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 6849490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 6859797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) 6869348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 6879348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 6889797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 6899490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 6909797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses 6919797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses 6929490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 6939797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 480 # number of overall (read+write) accesses 6949797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses 6959348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 6969797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.993007 # miss rate for ReadReq accesses 6979348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6989348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6999797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses 7009348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 7019797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses 7029797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 7039348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 7049797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses 70510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940 # average ReadReq miss latency 70610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396 # average ReadReq miss latency 70710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047 # average ReadReq miss latency 70810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804 # average ReadExReq miss latency 70910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804 # average ReadExReq miss latency 71010148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency 71110148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency 71210148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 72874.737945 # average overall miss latency 71310148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency 71410148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency 71510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 72874.737945 # average overall miss latency 7169348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7179348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7189348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 7199348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 7209348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7219348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7229348SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7239348SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 7249797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 7259490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 7269797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses 7279348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 7289348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 7299797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 7309490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 7319797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses 7329797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 7339490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 7349797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses 73510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19660250 # number of ReadReq MSHR miss cycles 73610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5948250 # number of ReadReq MSHR miss cycles 73710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 25608500 # number of ReadReq MSHR miss cycles 73810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3170750 # number of ReadExReq MSHR miss cycles 73910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3170750 # number of ReadExReq MSHR miss cycles 74010148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19660250 # number of demand (read+write) MSHR miss cycles 74110148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9119000 # number of demand (read+write) MSHR miss cycles 74210148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 28779250 # number of demand (read+write) MSHR miss cycles 74310148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19660250 # number of overall MSHR miss cycles 74410148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9119000 # number of overall MSHR miss cycles 74510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 28779250 # number of overall MSHR miss cycles 7469797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses 7479348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 7489797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses 7499348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 7509348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 7519797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses 7529348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 7539797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses 7549797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses 7559348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 7569797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses 75710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433 # average ReadReq mshr miss latency 75810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615 # average ReadReq mshr miss latency 75910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765 # average ReadReq mshr miss latency 76010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627 # average ReadExReq mshr miss latency 76110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627 # average ReadExReq mshr miss latency 76210148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency 76310148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency 76410148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency 76510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency 76610148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency 76710148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency 7689348SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7699838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 77010148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 91.623425 # Cycle average of tags in use 7719838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 7729838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 7739838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. 7749838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 77510148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 91.623425 # Average occupied blocks per requestor 77610148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.022369 # Average percentage of cache occupancy 77710148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.022369 # Average percentage of cache occupancy 77810036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 77910036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 78010036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 78110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id 78210036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses 78310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.data_accesses 5952 # Number of data accesses 7849797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits 7859797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits 7869729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 7879729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 7889797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 7899797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 7909797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 7919797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2395 # number of overall hits 7929797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 7939797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 7949729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 7959729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 7969797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses 7979797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses 7989797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses 7999797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 510 # number of overall misses 80010148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 10261250 # number of ReadReq miss cycles 80110148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 10261250 # number of ReadReq miss cycles 80210148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22413999 # number of WriteReq miss cycles 80310148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 22413999 # number of WriteReq miss cycles 80410148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 32675249 # number of demand (read+write) miss cycles 80510148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 32675249 # number of demand (read+write) miss cycles 80610148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 32675249 # number of overall miss cycles 80710148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 32675249 # number of overall miss cycles 8089797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) 8099797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) 8108835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 8118835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 8129797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses 8139797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses 8149797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses 8159797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses 8169797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses 8179797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses 8189729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 8199729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 8209797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses 8219797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses 8229797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses 8239797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses 82410148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270 # average ReadReq miss latency 82510148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270 # average ReadReq miss latency 82610148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309 # average WriteReq miss latency 82710148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309 # average WriteReq miss latency 82810148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency 82910148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 64069.115686 # average overall miss latency 83010148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency 83110148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 64069.115686 # average overall miss latency 8329978Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked 8338428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8349322Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 8358428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 8369978Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 8378983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8388428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8398428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8409797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 8419797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 8429729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 8439729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 8449797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits 8459797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits 8469797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits 8479797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits 8489490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 8499490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 8508835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 8518835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 8529490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 8539490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 8549490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 8559490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 85610148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7160250 # number of ReadReq MSHR miss cycles 85710148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7160250 # number of ReadReq MSHR miss cycles 85810148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3852749 # number of WriteReq MSHR miss cycles 85910148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3852749 # number of WriteReq MSHR miss cycles 86010148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 11012999 # number of demand (read+write) MSHR miss cycles 86110148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 11012999 # number of demand (read+write) MSHR miss cycles 86210148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 11012999 # number of overall MSHR miss cycles 86310148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 11012999 # number of overall MSHR miss cycles 8649797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses 8659797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses 8668835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 8679055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 8689797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses 8699797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses 8709797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses 8719797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses 87210148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934 # average ReadReq mshr miss latency 87310148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934 # average ReadReq mshr miss latency 87410148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039 # average WriteReq mshr miss latency 87510148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039 # average WriteReq mshr miss latency 87610148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency 87710148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency 87810148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency 87910148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency 8808428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8816039SN/A 8826039SN/A---------- End Simulation Statistics ---------- 883