config.ini revision 11384:e3cbd2823210
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=DerivO3CPU 51children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu.branchPred 61cachePorts=200 62checker=Null 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=1 72decodeWidth=8 73dispatchWidth=8 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dtb=system.cpu.dtb 78eventq_index=0 79fetchBufferSize=64 80fetchQueueSize=32 81fetchToDecodeDelay=1 82fetchTrapLatency=1 83fetchWidth=8 84forwardComSize=5 85fuPool=system.cpu.fuPool 86function_trace=false 87function_trace_start=0 88iewToCommitDelay=1 89iewToDecodeDelay=1 90iewToFetchDelay=1 91iewToRenameDelay=1 92interrupts=system.cpu.interrupts 93isa=system.cpu.isa 94issueToExecuteDelay=1 95issueWidth=8 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=64 103numPhysCCRegs=0 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] 139type=TournamentBP 140BTBEntries=4096 141BTBTagSize=16 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153 154[system.cpu.dcache] 155type=Cache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=2 159clk_domain=system.cpu_clk_domain 160clusivity=mostly_incl 161demand_mshr_reserve=1 162eventq_index=0 163hit_latency=2 164is_read_only=false 165max_miss_count=0 166mshrs=4 167prefetch_on_access=false 168prefetcher=Null 169response_latency=2 170sequential_access=false 171size=262144 172system=system 173tags=system.cpu.dcache.tags 174tgts_per_mshr=20 175write_buffers=8 176writeback_clean=false 177cpu_side=system.cpu.dcache_port 178mem_side=system.cpu.toL2Bus.slave[1] 179 180[system.cpu.dcache.tags] 181type=LRU 182assoc=2 183block_size=64 184clk_domain=system.cpu_clk_domain 185eventq_index=0 186hit_latency=2 187sequential_access=false 188size=262144 189 190[system.cpu.dtb] 191type=MipsTLB 192eventq_index=0 193size=64 194 195[system.cpu.fuPool] 196type=FUPool 197children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 198FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 199eventq_index=0 200 201[system.cpu.fuPool.FUList0] 202type=FUDesc 203children=opList 204count=6 205eventq_index=0 206opList=system.cpu.fuPool.FUList0.opList 207 208[system.cpu.fuPool.FUList0.opList] 209type=OpDesc 210eventq_index=0 211opClass=IntAlu 212opLat=1 213pipelined=true 214 215[system.cpu.fuPool.FUList1] 216type=FUDesc 217children=opList0 opList1 218count=2 219eventq_index=0 220opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 221 222[system.cpu.fuPool.FUList1.opList0] 223type=OpDesc 224eventq_index=0 225opClass=IntMult 226opLat=3 227pipelined=true 228 229[system.cpu.fuPool.FUList1.opList1] 230type=OpDesc 231eventq_index=0 232opClass=IntDiv 233opLat=20 234pipelined=false 235 236[system.cpu.fuPool.FUList2] 237type=FUDesc 238children=opList0 opList1 opList2 239count=4 240eventq_index=0 241opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 242 243[system.cpu.fuPool.FUList2.opList0] 244type=OpDesc 245eventq_index=0 246opClass=FloatAdd 247opLat=2 248pipelined=true 249 250[system.cpu.fuPool.FUList2.opList1] 251type=OpDesc 252eventq_index=0 253opClass=FloatCmp 254opLat=2 255pipelined=true 256 257[system.cpu.fuPool.FUList2.opList2] 258type=OpDesc 259eventq_index=0 260opClass=FloatCvt 261opLat=2 262pipelined=true 263 264[system.cpu.fuPool.FUList3] 265type=FUDesc 266children=opList0 opList1 opList2 267count=2 268eventq_index=0 269opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 270 271[system.cpu.fuPool.FUList3.opList0] 272type=OpDesc 273eventq_index=0 274opClass=FloatMult 275opLat=4 276pipelined=true 277 278[system.cpu.fuPool.FUList3.opList1] 279type=OpDesc 280eventq_index=0 281opClass=FloatDiv 282opLat=12 283pipelined=false 284 285[system.cpu.fuPool.FUList3.opList2] 286type=OpDesc 287eventq_index=0 288opClass=FloatSqrt 289opLat=24 290pipelined=false 291 292[system.cpu.fuPool.FUList4] 293type=FUDesc 294children=opList 295count=0 296eventq_index=0 297opList=system.cpu.fuPool.FUList4.opList 298 299[system.cpu.fuPool.FUList4.opList] 300type=OpDesc 301eventq_index=0 302opClass=MemRead 303opLat=1 304pipelined=true 305 306[system.cpu.fuPool.FUList5] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 309count=4 310eventq_index=0 311opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 312 313[system.cpu.fuPool.FUList5.opList00] 314type=OpDesc 315eventq_index=0 316opClass=SimdAdd 317opLat=1 318pipelined=true 319 320[system.cpu.fuPool.FUList5.opList01] 321type=OpDesc 322eventq_index=0 323opClass=SimdAddAcc 324opLat=1 325pipelined=true 326 327[system.cpu.fuPool.FUList5.opList02] 328type=OpDesc 329eventq_index=0 330opClass=SimdAlu 331opLat=1 332pipelined=true 333 334[system.cpu.fuPool.FUList5.opList03] 335type=OpDesc 336eventq_index=0 337opClass=SimdCmp 338opLat=1 339pipelined=true 340 341[system.cpu.fuPool.FUList5.opList04] 342type=OpDesc 343eventq_index=0 344opClass=SimdCvt 345opLat=1 346pipelined=true 347 348[system.cpu.fuPool.FUList5.opList05] 349type=OpDesc 350eventq_index=0 351opClass=SimdMisc 352opLat=1 353pipelined=true 354 355[system.cpu.fuPool.FUList5.opList06] 356type=OpDesc 357eventq_index=0 358opClass=SimdMult 359opLat=1 360pipelined=true 361 362[system.cpu.fuPool.FUList5.opList07] 363type=OpDesc 364eventq_index=0 365opClass=SimdMultAcc 366opLat=1 367pipelined=true 368 369[system.cpu.fuPool.FUList5.opList08] 370type=OpDesc 371eventq_index=0 372opClass=SimdShift 373opLat=1 374pipelined=true 375 376[system.cpu.fuPool.FUList5.opList09] 377type=OpDesc 378eventq_index=0 379opClass=SimdShiftAcc 380opLat=1 381pipelined=true 382 383[system.cpu.fuPool.FUList5.opList10] 384type=OpDesc 385eventq_index=0 386opClass=SimdSqrt 387opLat=1 388pipelined=true 389 390[system.cpu.fuPool.FUList5.opList11] 391type=OpDesc 392eventq_index=0 393opClass=SimdFloatAdd 394opLat=1 395pipelined=true 396 397[system.cpu.fuPool.FUList5.opList12] 398type=OpDesc 399eventq_index=0 400opClass=SimdFloatAlu 401opLat=1 402pipelined=true 403 404[system.cpu.fuPool.FUList5.opList13] 405type=OpDesc 406eventq_index=0 407opClass=SimdFloatCmp 408opLat=1 409pipelined=true 410 411[system.cpu.fuPool.FUList5.opList14] 412type=OpDesc 413eventq_index=0 414opClass=SimdFloatCvt 415opLat=1 416pipelined=true 417 418[system.cpu.fuPool.FUList5.opList15] 419type=OpDesc 420eventq_index=0 421opClass=SimdFloatDiv 422opLat=1 423pipelined=true 424 425[system.cpu.fuPool.FUList5.opList16] 426type=OpDesc 427eventq_index=0 428opClass=SimdFloatMisc 429opLat=1 430pipelined=true 431 432[system.cpu.fuPool.FUList5.opList17] 433type=OpDesc 434eventq_index=0 435opClass=SimdFloatMult 436opLat=1 437pipelined=true 438 439[system.cpu.fuPool.FUList5.opList18] 440type=OpDesc 441eventq_index=0 442opClass=SimdFloatMultAcc 443opLat=1 444pipelined=true 445 446[system.cpu.fuPool.FUList5.opList19] 447type=OpDesc 448eventq_index=0 449opClass=SimdFloatSqrt 450opLat=1 451pipelined=true 452 453[system.cpu.fuPool.FUList6] 454type=FUDesc 455children=opList 456count=0 457eventq_index=0 458opList=system.cpu.fuPool.FUList6.opList 459 460[system.cpu.fuPool.FUList6.opList] 461type=OpDesc 462eventq_index=0 463opClass=MemWrite 464opLat=1 465pipelined=true 466 467[system.cpu.fuPool.FUList7] 468type=FUDesc 469children=opList0 opList1 470count=4 471eventq_index=0 472opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 473 474[system.cpu.fuPool.FUList7.opList0] 475type=OpDesc 476eventq_index=0 477opClass=MemRead 478opLat=1 479pipelined=true 480 481[system.cpu.fuPool.FUList7.opList1] 482type=OpDesc 483eventq_index=0 484opClass=MemWrite 485opLat=1 486pipelined=true 487 488[system.cpu.fuPool.FUList8] 489type=FUDesc 490children=opList 491count=1 492eventq_index=0 493opList=system.cpu.fuPool.FUList8.opList 494 495[system.cpu.fuPool.FUList8.opList] 496type=OpDesc 497eventq_index=0 498opClass=IprAccess 499opLat=3 500pipelined=false 501 502[system.cpu.icache] 503type=Cache 504children=tags 505addr_ranges=0:18446744073709551615 506assoc=2 507clk_domain=system.cpu_clk_domain 508clusivity=mostly_incl 509demand_mshr_reserve=1 510eventq_index=0 511hit_latency=2 512is_read_only=true 513max_miss_count=0 514mshrs=4 515prefetch_on_access=false 516prefetcher=Null 517response_latency=2 518sequential_access=false 519size=131072 520system=system 521tags=system.cpu.icache.tags 522tgts_per_mshr=20 523write_buffers=8 524writeback_clean=true 525cpu_side=system.cpu.icache_port 526mem_side=system.cpu.toL2Bus.slave[0] 527 528[system.cpu.icache.tags] 529type=LRU 530assoc=2 531block_size=64 532clk_domain=system.cpu_clk_domain 533eventq_index=0 534hit_latency=2 535sequential_access=false 536size=131072 537 538[system.cpu.interrupts] 539type=MipsInterrupts 540eventq_index=0 541 542[system.cpu.isa] 543type=MipsISA 544eventq_index=0 545num_threads=1 546num_vpes=1 547system=system 548 549[system.cpu.itb] 550type=MipsTLB 551eventq_index=0 552size=64 553 554[system.cpu.l2cache] 555type=Cache 556children=tags 557addr_ranges=0:18446744073709551615 558assoc=8 559clk_domain=system.cpu_clk_domain 560clusivity=mostly_incl 561demand_mshr_reserve=1 562eventq_index=0 563hit_latency=20 564is_read_only=false 565max_miss_count=0 566mshrs=20 567prefetch_on_access=false 568prefetcher=Null 569response_latency=20 570sequential_access=false 571size=2097152 572system=system 573tags=system.cpu.l2cache.tags 574tgts_per_mshr=12 575write_buffers=8 576writeback_clean=false 577cpu_side=system.cpu.toL2Bus.master[0] 578mem_side=system.membus.slave[1] 579 580[system.cpu.l2cache.tags] 581type=LRU 582assoc=8 583block_size=64 584clk_domain=system.cpu_clk_domain 585eventq_index=0 586hit_latency=20 587sequential_access=false 588size=2097152 589 590[system.cpu.toL2Bus] 591type=CoherentXBar 592children=snoop_filter 593clk_domain=system.cpu_clk_domain 594eventq_index=0 595forward_latency=0 596frontend_latency=1 597point_of_coherency=false 598response_latency=1 599snoop_filter=system.cpu.toL2Bus.snoop_filter 600snoop_response_latency=1 601system=system 602use_default_range=false 603width=32 604master=system.cpu.l2cache.cpu_side 605slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 606 607[system.cpu.toL2Bus.snoop_filter] 608type=SnoopFilter 609eventq_index=0 610lookup_latency=0 611max_capacity=8388608 612system=system 613 614[system.cpu.tracer] 615type=ExeTracer 616eventq_index=0 617 618[system.cpu.workload] 619type=LiveProcess 620cmd=hello 621cwd= 622drivers= 623egid=100 624env= 625errout=cerr 626euid=100 627eventq_index=0 628executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello 629gid=100 630input=cin 631kvmInSE=false 632max_stack_size=67108864 633output=cout 634pid=100 635ppid=99 636simpoint=0 637system=system 638uid=100 639useArchPT=false 640 641[system.cpu_clk_domain] 642type=SrcClockDomain 643clock=500 644domain_id=-1 645eventq_index=0 646init_perf_level=0 647voltage_domain=system.voltage_domain 648 649[system.dvfs_handler] 650type=DVFSHandler 651domains= 652enable=false 653eventq_index=0 654sys_clk_domain=system.clk_domain 655transition_latency=100000000 656 657[system.membus] 658type=CoherentXBar 659clk_domain=system.clk_domain 660eventq_index=0 661forward_latency=4 662frontend_latency=3 663point_of_coherency=true 664response_latency=2 665snoop_filter=Null 666snoop_response_latency=4 667system=system 668use_default_range=false 669width=16 670master=system.physmem.port 671slave=system.system_port system.cpu.l2cache.mem_side 672 673[system.physmem] 674type=DRAMCtrl 675IDD0=0.075000 676IDD02=0.000000 677IDD2N=0.050000 678IDD2N2=0.000000 679IDD2P0=0.000000 680IDD2P02=0.000000 681IDD2P1=0.000000 682IDD2P12=0.000000 683IDD3N=0.057000 684IDD3N2=0.000000 685IDD3P0=0.000000 686IDD3P02=0.000000 687IDD3P1=0.000000 688IDD3P12=0.000000 689IDD4R=0.187000 690IDD4R2=0.000000 691IDD4W=0.165000 692IDD4W2=0.000000 693IDD5=0.220000 694IDD52=0.000000 695IDD6=0.000000 696IDD62=0.000000 697VDD=1.500000 698VDD2=0.000000 699activation_limit=4 700addr_mapping=RoRaBaCoCh 701bank_groups_per_rank=0 702banks_per_rank=8 703burst_length=8 704channels=1 705clk_domain=system.clk_domain 706conf_table_reported=true 707device_bus_width=8 708device_rowbuffer_size=1024 709device_size=536870912 710devices_per_rank=8 711dll=true 712eventq_index=0 713in_addr_map=true 714max_accesses_per_row=16 715mem_sched_policy=frfcfs 716min_writes_per_switch=16 717null=false 718page_policy=open_adaptive 719range=0:134217727 720ranks_per_channel=2 721read_buffer_size=32 722static_backend_latency=10000 723static_frontend_latency=10000 724tBURST=5000 725tCCD_L=0 726tCK=1250 727tCL=13750 728tCS=2500 729tRAS=35000 730tRCD=13750 731tREFI=7800000 732tRFC=260000 733tRP=13750 734tRRD=6000 735tRRD_L=0 736tRTP=7500 737tRTW=2500 738tWR=15000 739tWTR=7500 740tXAW=30000 741tXP=0 742tXPDLL=0 743tXS=0 744tXSDLL=0 745write_buffer_size=64 746write_high_thresh_perc=85 747write_low_thresh_perc=50 748port=system.membus.master[0] 749 750[system.voltage_domain] 751type=VoltageDomain 752eventq_index=0 753voltage=1.000000 754 755