config.ini revision 10315:9e02c14446bb
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dtb=system.cpu.dtb 75eventq_index=0 76fetchBufferSize=64 77fetchToDecodeDelay=1 78fetchTrapLatency=1 79fetchWidth=8 80forwardComSize=5 81fuPool=system.cpu.fuPool 82function_trace=false 83function_trace_start=0 84iewToCommitDelay=1 85iewToDecodeDelay=1 86iewToFetchDelay=1 87iewToRenameDelay=1 88interrupts=system.cpu.interrupts 89isa=system.cpu.isa 90issueToExecuteDelay=1 91issueWidth=8 92itb=system.cpu.itb 93max_insts_all_threads=0 94max_insts_any_thread=0 95max_loads_all_threads=0 96max_loads_any_thread=0 97needsTSO=false 98numIQEntries=64 99numPhysCCRegs=0 100numPhysFloatRegs=256 101numPhysIntRegs=256 102numROBEntries=192 103numRobs=1 104numThreads=1 105profile=0 106progress_interval=0 107renameToDecodeDelay=1 108renameToFetchDelay=1 109renameToIEWDelay=2 110renameToROBDelay=1 111renameWidth=8 112simpoint_start_insts= 113smtCommitPolicy=RoundRobin 114smtFetchPolicy=SingleThread 115smtIQPolicy=Partitioned 116smtIQThreshold=100 117smtLSQPolicy=Partitioned 118smtLSQThreshold=100 119smtNumFetchingThreads=1 120smtROBPolicy=Partitioned 121smtROBThreshold=100 122socket_id=0 123squashWidth=8 124store_set_clear_period=250000 125switched_out=false 126system=system 127tracer=system.cpu.tracer 128trapLatency=13 129wbDepth=1 130wbWidth=8 131workload=system.cpu.workload 132dcache_port=system.cpu.dcache.cpu_side 133icache_port=system.cpu.icache.cpu_side 134 135[system.cpu.branchPred] 136type=BranchPredictor 137BTBEntries=4096 138BTBTagSize=16 139RASSize=16 140choiceCtrBits=2 141choicePredictorSize=8192 142eventq_index=0 143globalCtrBits=2 144globalPredictorSize=8192 145instShiftAmt=2 146localCtrBits=2 147localHistoryTableSize=2048 148localPredictorSize=2048 149numThreads=1 150predType=tournament 151 152[system.cpu.dcache] 153type=BaseCache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=2 157clk_domain=system.cpu_clk_domain 158eventq_index=0 159forward_snoops=true 160hit_latency=2 161is_top_level=true 162max_miss_count=0 163mshrs=4 164prefetch_on_access=false 165prefetcher=Null 166response_latency=2 167sequential_access=false 168size=262144 169system=system 170tags=system.cpu.dcache.tags 171tgts_per_mshr=20 172two_queue=false 173write_buffers=8 174cpu_side=system.cpu.dcache_port 175mem_side=system.cpu.toL2Bus.slave[1] 176 177[system.cpu.dcache.tags] 178type=LRU 179assoc=2 180block_size=64 181clk_domain=system.cpu_clk_domain 182eventq_index=0 183hit_latency=2 184sequential_access=false 185size=262144 186 187[system.cpu.dtb] 188type=MipsTLB 189eventq_index=0 190size=64 191 192[system.cpu.fuPool] 193type=FUPool 194children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 195FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 196eventq_index=0 197 198[system.cpu.fuPool.FUList0] 199type=FUDesc 200children=opList 201count=6 202eventq_index=0 203opList=system.cpu.fuPool.FUList0.opList 204 205[system.cpu.fuPool.FUList0.opList] 206type=OpDesc 207eventq_index=0 208issueLat=1 209opClass=IntAlu 210opLat=1 211 212[system.cpu.fuPool.FUList1] 213type=FUDesc 214children=opList0 opList1 215count=2 216eventq_index=0 217opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 218 219[system.cpu.fuPool.FUList1.opList0] 220type=OpDesc 221eventq_index=0 222issueLat=1 223opClass=IntMult 224opLat=3 225 226[system.cpu.fuPool.FUList1.opList1] 227type=OpDesc 228eventq_index=0 229issueLat=19 230opClass=IntDiv 231opLat=20 232 233[system.cpu.fuPool.FUList2] 234type=FUDesc 235children=opList0 opList1 opList2 236count=4 237eventq_index=0 238opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 239 240[system.cpu.fuPool.FUList2.opList0] 241type=OpDesc 242eventq_index=0 243issueLat=1 244opClass=FloatAdd 245opLat=2 246 247[system.cpu.fuPool.FUList2.opList1] 248type=OpDesc 249eventq_index=0 250issueLat=1 251opClass=FloatCmp 252opLat=2 253 254[system.cpu.fuPool.FUList2.opList2] 255type=OpDesc 256eventq_index=0 257issueLat=1 258opClass=FloatCvt 259opLat=2 260 261[system.cpu.fuPool.FUList3] 262type=FUDesc 263children=opList0 opList1 opList2 264count=2 265eventq_index=0 266opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 267 268[system.cpu.fuPool.FUList3.opList0] 269type=OpDesc 270eventq_index=0 271issueLat=1 272opClass=FloatMult 273opLat=4 274 275[system.cpu.fuPool.FUList3.opList1] 276type=OpDesc 277eventq_index=0 278issueLat=12 279opClass=FloatDiv 280opLat=12 281 282[system.cpu.fuPool.FUList3.opList2] 283type=OpDesc 284eventq_index=0 285issueLat=24 286opClass=FloatSqrt 287opLat=24 288 289[system.cpu.fuPool.FUList4] 290type=FUDesc 291children=opList 292count=0 293eventq_index=0 294opList=system.cpu.fuPool.FUList4.opList 295 296[system.cpu.fuPool.FUList4.opList] 297type=OpDesc 298eventq_index=0 299issueLat=1 300opClass=MemRead 301opLat=1 302 303[system.cpu.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307eventq_index=0 308opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 309 310[system.cpu.fuPool.FUList5.opList00] 311type=OpDesc 312eventq_index=0 313issueLat=1 314opClass=SimdAdd 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList01] 318type=OpDesc 319eventq_index=0 320issueLat=1 321opClass=SimdAddAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList02] 325type=OpDesc 326eventq_index=0 327issueLat=1 328opClass=SimdAlu 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList03] 332type=OpDesc 333eventq_index=0 334issueLat=1 335opClass=SimdCmp 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList04] 339type=OpDesc 340eventq_index=0 341issueLat=1 342opClass=SimdCvt 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList05] 346type=OpDesc 347eventq_index=0 348issueLat=1 349opClass=SimdMisc 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList06] 353type=OpDesc 354eventq_index=0 355issueLat=1 356opClass=SimdMult 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList07] 360type=OpDesc 361eventq_index=0 362issueLat=1 363opClass=SimdMultAcc 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList08] 367type=OpDesc 368eventq_index=0 369issueLat=1 370opClass=SimdShift 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList09] 374type=OpDesc 375eventq_index=0 376issueLat=1 377opClass=SimdShiftAcc 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList10] 381type=OpDesc 382eventq_index=0 383issueLat=1 384opClass=SimdSqrt 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList11] 388type=OpDesc 389eventq_index=0 390issueLat=1 391opClass=SimdFloatAdd 392opLat=1 393 394[system.cpu.fuPool.FUList5.opList12] 395type=OpDesc 396eventq_index=0 397issueLat=1 398opClass=SimdFloatAlu 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList13] 402type=OpDesc 403eventq_index=0 404issueLat=1 405opClass=SimdFloatCmp 406opLat=1 407 408[system.cpu.fuPool.FUList5.opList14] 409type=OpDesc 410eventq_index=0 411issueLat=1 412opClass=SimdFloatCvt 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList15] 416type=OpDesc 417eventq_index=0 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList16] 423type=OpDesc 424eventq_index=0 425issueLat=1 426opClass=SimdFloatMisc 427opLat=1 428 429[system.cpu.fuPool.FUList5.opList17] 430type=OpDesc 431eventq_index=0 432issueLat=1 433opClass=SimdFloatMult 434opLat=1 435 436[system.cpu.fuPool.FUList5.opList18] 437type=OpDesc 438eventq_index=0 439issueLat=1 440opClass=SimdFloatMultAcc 441opLat=1 442 443[system.cpu.fuPool.FUList5.opList19] 444type=OpDesc 445eventq_index=0 446issueLat=1 447opClass=SimdFloatSqrt 448opLat=1 449 450[system.cpu.fuPool.FUList6] 451type=FUDesc 452children=opList 453count=0 454eventq_index=0 455opList=system.cpu.fuPool.FUList6.opList 456 457[system.cpu.fuPool.FUList6.opList] 458type=OpDesc 459eventq_index=0 460issueLat=1 461opClass=MemWrite 462opLat=1 463 464[system.cpu.fuPool.FUList7] 465type=FUDesc 466children=opList0 opList1 467count=4 468eventq_index=0 469opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 470 471[system.cpu.fuPool.FUList7.opList0] 472type=OpDesc 473eventq_index=0 474issueLat=1 475opClass=MemRead 476opLat=1 477 478[system.cpu.fuPool.FUList7.opList1] 479type=OpDesc 480eventq_index=0 481issueLat=1 482opClass=MemWrite 483opLat=1 484 485[system.cpu.fuPool.FUList8] 486type=FUDesc 487children=opList 488count=1 489eventq_index=0 490opList=system.cpu.fuPool.FUList8.opList 491 492[system.cpu.fuPool.FUList8.opList] 493type=OpDesc 494eventq_index=0 495issueLat=3 496opClass=IprAccess 497opLat=3 498 499[system.cpu.icache] 500type=BaseCache 501children=tags 502addr_ranges=0:18446744073709551615 503assoc=2 504clk_domain=system.cpu_clk_domain 505eventq_index=0 506forward_snoops=true 507hit_latency=2 508is_top_level=true 509max_miss_count=0 510mshrs=4 511prefetch_on_access=false 512prefetcher=Null 513response_latency=2 514sequential_access=false 515size=131072 516system=system 517tags=system.cpu.icache.tags 518tgts_per_mshr=20 519two_queue=false 520write_buffers=8 521cpu_side=system.cpu.icache_port 522mem_side=system.cpu.toL2Bus.slave[0] 523 524[system.cpu.icache.tags] 525type=LRU 526assoc=2 527block_size=64 528clk_domain=system.cpu_clk_domain 529eventq_index=0 530hit_latency=2 531sequential_access=false 532size=131072 533 534[system.cpu.interrupts] 535type=MipsInterrupts 536eventq_index=0 537 538[system.cpu.isa] 539type=MipsISA 540eventq_index=0 541num_threads=1 542num_vpes=1 543system=system 544 545[system.cpu.itb] 546type=MipsTLB 547eventq_index=0 548size=64 549 550[system.cpu.l2cache] 551type=BaseCache 552children=tags 553addr_ranges=0:18446744073709551615 554assoc=8 555clk_domain=system.cpu_clk_domain 556eventq_index=0 557forward_snoops=true 558hit_latency=20 559is_top_level=false 560max_miss_count=0 561mshrs=20 562prefetch_on_access=false 563prefetcher=Null 564response_latency=20 565sequential_access=false 566size=2097152 567system=system 568tags=system.cpu.l2cache.tags 569tgts_per_mshr=12 570two_queue=false 571write_buffers=8 572cpu_side=system.cpu.toL2Bus.master[0] 573mem_side=system.membus.slave[1] 574 575[system.cpu.l2cache.tags] 576type=LRU 577assoc=8 578block_size=64 579clk_domain=system.cpu_clk_domain 580eventq_index=0 581hit_latency=20 582sequential_access=false 583size=2097152 584 585[system.cpu.toL2Bus] 586type=CoherentBus 587clk_domain=system.cpu_clk_domain 588eventq_index=0 589header_cycles=1 590system=system 591use_default_range=false 592width=32 593master=system.cpu.l2cache.cpu_side 594slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 595 596[system.cpu.tracer] 597type=ExeTracer 598eventq_index=0 599 600[system.cpu.workload] 601type=LiveProcess 602cmd=hello 603cwd= 604egid=100 605env= 606errout=cerr 607euid=100 608eventq_index=0 609executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello 610gid=100 611input=cin 612max_stack_size=67108864 613output=cout 614pid=100 615ppid=99 616simpoint=0 617system=system 618uid=100 619 620[system.cpu_clk_domain] 621type=SrcClockDomain 622clock=500 623domain_id=-1 624eventq_index=0 625init_perf_level=0 626voltage_domain=system.voltage_domain 627 628[system.dvfs_handler] 629type=DVFSHandler 630domains= 631enable=false 632eventq_index=0 633sys_clk_domain=system.clk_domain 634transition_latency=100000000 635 636[system.membus] 637type=CoherentBus 638clk_domain=system.clk_domain 639eventq_index=0 640header_cycles=1 641system=system 642use_default_range=false 643width=8 644master=system.physmem.port 645slave=system.system_port system.cpu.l2cache.mem_side 646 647[system.physmem] 648type=DRAMCtrl 649activation_limit=4 650addr_mapping=RoRaBaChCo 651banks_per_rank=8 652burst_length=8 653channels=1 654clk_domain=system.clk_domain 655conf_table_reported=true 656device_bus_width=8 657device_rowbuffer_size=1024 658devices_per_rank=8 659eventq_index=0 660in_addr_map=true 661max_accesses_per_row=16 662mem_sched_policy=frfcfs 663min_writes_per_switch=16 664null=false 665page_policy=open_adaptive 666range=0:134217727 667ranks_per_channel=2 668read_buffer_size=32 669static_backend_latency=10000 670static_frontend_latency=10000 671tBURST=5000 672tCK=1250 673tCL=13750 674tRAS=35000 675tRCD=13750 676tREFI=7800000 677tRFC=260000 678tRP=13750 679tRRD=6000 680tRTP=7500 681tRTW=2500 682tWR=15000 683tWTR=7500 684tXAW=30000 685write_buffer_size=64 686write_high_thresh_perc=85 687write_low_thresh_perc=50 688port=system.membus.master[0] 689 690[system.voltage_domain] 691type=VoltageDomain 692eventq_index=0 693voltage=1.000000 694 695