stats.txt revision 9797:9cd5f91e7a79
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25969000 # Number of ticks simulated 5final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 220478 # Simulator instruction rate (inst/s) 8host_op_rate 273604 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1251201624 # Simulator tick rate (ticks/s) 10host_mem_usage 241012 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host 12sim_insts 4565 # Number of instructions simulated 13sim_ops 5672 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 16system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) 30system.membus.throughput 862566907 # Throughput (bytes/s) 31system.membus.trans_dist::ReadReq 307 # Transaction distribution 32system.membus.trans_dist::ReadResp 307 # Transaction distribution 33system.membus.trans_dist::ReadExReq 43 # Transaction distribution 34system.membus.trans_dist::ReadExResp 43 # Transaction distribution 35system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes) 36system.membus.pkt_count 700 # Packet count per connected master and slave (bytes) 37system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) 38system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes) 39system.membus.data_through_bus 22400 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks) 42system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 43system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks) 44system.membus.respLayer1.utilization 12.1 # Layer utilization (%) 45system.cpu.dtb.inst_hits 0 # ITB inst hits 46system.cpu.dtb.inst_misses 0 # ITB inst misses 47system.cpu.dtb.read_hits 0 # DTB read hits 48system.cpu.dtb.read_misses 0 # DTB read misses 49system.cpu.dtb.write_hits 0 # DTB write hits 50system.cpu.dtb.write_misses 0 # DTB write misses 51system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 52system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 53system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 54system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 55system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 56system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 57system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 58system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 59system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60system.cpu.dtb.read_accesses 0 # DTB read accesses 61system.cpu.dtb.write_accesses 0 # DTB write accesses 62system.cpu.dtb.inst_accesses 0 # ITB inst accesses 63system.cpu.dtb.hits 0 # DTB hits 64system.cpu.dtb.misses 0 # DTB misses 65system.cpu.dtb.accesses 0 # DTB accesses 66system.cpu.itb.inst_hits 0 # ITB inst hits 67system.cpu.itb.inst_misses 0 # ITB inst misses 68system.cpu.itb.read_hits 0 # DTB read hits 69system.cpu.itb.read_misses 0 # DTB read misses 70system.cpu.itb.write_hits 0 # DTB write hits 71system.cpu.itb.write_misses 0 # DTB write misses 72system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 73system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 74system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 75system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 76system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 77system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 78system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 79system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 80system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 81system.cpu.itb.read_accesses 0 # DTB read accesses 82system.cpu.itb.write_accesses 0 # DTB write accesses 83system.cpu.itb.inst_accesses 0 # ITB inst accesses 84system.cpu.itb.hits 0 # DTB hits 85system.cpu.itb.misses 0 # DTB misses 86system.cpu.itb.accesses 0 # DTB accesses 87system.cpu.workload.num_syscalls 13 # Number of system calls 88system.cpu.numCycles 51938 # number of cpu cycles simulated 89system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 90system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 91system.cpu.committedInsts 4565 # Number of instructions committed 92system.cpu.committedOps 5672 # Number of ops (including micro ops) committed 93system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses 94system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 95system.cpu.num_func_calls 203 # number of times a function call or return occured 96system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls 97system.cpu.num_int_insts 4976 # number of integer instructions 98system.cpu.num_fp_insts 16 # number of float instructions 99system.cpu.num_int_register_reads 28656 # number of times the integer registers were read 100system.cpu.num_int_register_writes 5334 # number of times the integer registers were written 101system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 102system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 103system.cpu.num_mem_refs 2138 # number of memory refs 104system.cpu.num_load_insts 1200 # Number of load instructions 105system.cpu.num_store_insts 938 # Number of store instructions 106system.cpu.num_idle_cycles 0 # Number of idle cycles 107system.cpu.num_busy_cycles 51938 # Number of busy cycles 108system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 109system.cpu.idle_fraction 0 # Percentage of idle cycles 110system.cpu.icache.tags.replacements 1 # number of replacements 111system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use 112system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. 113system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 114system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. 115system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 116system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor 117system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy 118system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy 119system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits 120system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits 121system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits 122system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits 123system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits 124system.cpu.icache.overall_hits::total 4364 # number of overall hits 125system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 126system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 127system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 128system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 129system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 130system.cpu.icache.overall_misses::total 241 # number of overall misses 131system.cpu.icache.ReadReq_miss_latency::cpu.inst 12583000 # number of ReadReq miss cycles 132system.cpu.icache.ReadReq_miss_latency::total 12583000 # number of ReadReq miss cycles 133system.cpu.icache.demand_miss_latency::cpu.inst 12583000 # number of demand (read+write) miss cycles 134system.cpu.icache.demand_miss_latency::total 12583000 # number of demand (read+write) miss cycles 135system.cpu.icache.overall_miss_latency::cpu.inst 12583000 # number of overall miss cycles 136system.cpu.icache.overall_miss_latency::total 12583000 # number of overall miss cycles 137system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) 138system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) 139system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses 140system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses 141system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses 142system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses 143system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses 144system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses 145system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses 146system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses 147system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses 148system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses 149system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257 # average ReadReq miss latency 150system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257 # average ReadReq miss latency 151system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency 152system.cpu.icache.demand_avg_miss_latency::total 52211.618257 # average overall miss latency 153system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency 154system.cpu.icache.overall_avg_miss_latency::total 52211.618257 # average overall miss latency 155system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 156system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 157system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 158system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 159system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 160system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 161system.cpu.icache.fast_writes 0 # number of fast writes performed 162system.cpu.icache.cache_copies 0 # number of cache copies performed 163system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 164system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 165system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 166system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 167system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 168system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses 169system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles 170system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles 171system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles 172system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles 173system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles 174system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles 175system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses 176system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses 177system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses 178system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses 179system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses 180system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses 181system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency 182system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency 183system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 184system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 185system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 186system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 187system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 188system.cpu.l2cache.tags.replacements 0 # number of replacements 189system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use 190system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 191system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 192system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 193system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 194system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor 195system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor 196system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy 197system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy 198system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy 199system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 200system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits 201system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits 202system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 203system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 204system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 205system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 206system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 207system.cpu.l2cache.overall_hits::total 32 # number of overall hits 208system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses 209system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses 210system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses 211system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 212system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 213system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 214system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 215system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses 216system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses 217system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 218system.cpu.l2cache.overall_misses::total 350 # number of overall misses 219system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles 220system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles 221system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles 222system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles 223system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles 224system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles 225system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles 226system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles 227system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles 228system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles 229system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles 230system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) 231system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) 232system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) 233system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 234system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 235system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses 236system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 237system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses 238system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses 239system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 240system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses 241system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses 242system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses 243system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses 244system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 245system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 246system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses 247system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses 248system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses 249system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses 250system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses 251system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses 252system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 253system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 254system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 255system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 256system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 257system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 258system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 259system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 260system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 261system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 262system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 263system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 264system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 265system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 266system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 267system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 268system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 269system.cpu.l2cache.fast_writes 0 # number of fast writes performed 270system.cpu.l2cache.cache_copies 0 # number of cache copies performed 271system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses 272system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 273system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses 274system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 275system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 276system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 277system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 278system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 279system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 280system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 281system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses 282system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles 283system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles 284system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles 285system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles 286system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles 287system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles 288system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles 289system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles 290system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles 291system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles 292system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles 293system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses 294system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses 295system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses 296system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 297system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 298system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses 299system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses 300system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses 301system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses 302system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses 303system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses 304system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 305system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 306system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 307system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 308system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 309system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 310system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 311system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 312system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 313system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 314system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 315system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 316system.cpu.dcache.tags.replacements 0 # number of replacements 317system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use 318system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks. 319system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 320system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks. 321system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 322system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor 323system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy 324system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy 325system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 326system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 327system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 328system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 329system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 330system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 331system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 332system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 333system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits 334system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits 335system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits 336system.cpu.dcache.overall_hits::total 1918 # number of overall hits 337system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 338system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 339system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 340system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 341system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 342system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 343system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 344system.cpu.dcache.overall_misses::total 141 # number of overall misses 345system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles 346system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles 347system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles 348system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles 349system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles 350system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles 351system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles 352system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles 353system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) 354system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) 355system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 356system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 357system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 358system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 359system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 360system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 361system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses 362system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses 363system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses 364system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses 365system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses 366system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses 367system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 368system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 369system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses 370system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses 371system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses 372system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses 373system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency 374system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency 375system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 376system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 377system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 378system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency 379system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 380system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency 381system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 382system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 383system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 384system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 385system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 386system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 387system.cpu.dcache.fast_writes 0 # number of fast writes performed 388system.cpu.dcache.cache_copies 0 # number of cache copies performed 389system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 390system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 391system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 392system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 393system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 394system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 395system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 396system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 397system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles 398system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles 399system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles 400system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles 401system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles 402system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles 403system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles 404system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles 405system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses 406system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses 407system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 408system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 409system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses 410system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses 411system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses 412system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses 413system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency 414system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency 415system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 416system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 417system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 418system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 419system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 420system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 421system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 422system.cpu.toL2Bus.throughput 941430167 # Throughput (bytes/s) 423system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution 424system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 425system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 426system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 427system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes) 428system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes) 429system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes) 430system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes) 431system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) 432system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes) 433system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes) 434system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 435system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) 436system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 437system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 438system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 439system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 440system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 441 442---------- End Simulation Statistics ---------- 443