stats.txt revision 9481:b0fa6b872f40
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25969000 # Number of ticks simulated 5final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 66941 # Simulator instruction rate (inst/s) 8host_op_rate 83151 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 380602116 # Simulator tick rate (ticks/s) 10host_mem_usage 284140 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 4565 # Number of instructions simulated 13sim_ops 5672 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 16system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 41system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 42system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 43system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 44system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45system.cpu.dtb.read_accesses 0 # DTB read accesses 46system.cpu.dtb.write_accesses 0 # DTB write accesses 47system.cpu.dtb.inst_accesses 0 # ITB inst accesses 48system.cpu.dtb.hits 0 # DTB hits 49system.cpu.dtb.misses 0 # DTB misses 50system.cpu.dtb.accesses 0 # DTB accesses 51system.cpu.itb.inst_hits 0 # ITB inst hits 52system.cpu.itb.inst_misses 0 # ITB inst misses 53system.cpu.itb.read_hits 0 # DTB read hits 54system.cpu.itb.read_misses 0 # DTB read misses 55system.cpu.itb.write_hits 0 # DTB write hits 56system.cpu.itb.write_misses 0 # DTB write misses 57system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 13 # Number of system calls 73system.cpu.numCycles 51938 # number of cpu cycles simulated 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.committedInsts 4565 # Number of instructions committed 77system.cpu.committedOps 5672 # Number of ops (including micro ops) committed 78system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses 79system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 80system.cpu.num_func_calls 203 # number of times a function call or return occured 81system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls 82system.cpu.num_int_insts 4976 # number of integer instructions 83system.cpu.num_fp_insts 16 # number of float instructions 84system.cpu.num_int_register_reads 28656 # number of times the integer registers were read 85system.cpu.num_int_register_writes 5334 # number of times the integer registers were written 86system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 87system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 88system.cpu.num_mem_refs 2138 # number of memory refs 89system.cpu.num_load_insts 1200 # Number of load instructions 90system.cpu.num_store_insts 938 # Number of store instructions 91system.cpu.num_idle_cycles 0 # Number of idle cycles 92system.cpu.num_busy_cycles 51938 # Number of busy cycles 93system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 94system.cpu.idle_fraction 0 # Percentage of idle cycles 95system.cpu.icache.replacements 1 # number of replacements 96system.cpu.icache.tagsinuse 114.614391 # Cycle average of tags in use 97system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. 98system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. 99system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. 100system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 101system.cpu.icache.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor 102system.cpu.icache.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy 103system.cpu.icache.occ_percent::total 0.055964 # Average percentage of cache occupancy 104system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits 105system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits 106system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits 107system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits 108system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits 109system.cpu.icache.overall_hits::total 4364 # number of overall hits 110system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 111system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 112system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 113system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 114system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 115system.cpu.icache.overall_misses::total 241 # number of overall misses 116system.cpu.icache.ReadReq_miss_latency::cpu.inst 12583000 # number of ReadReq miss cycles 117system.cpu.icache.ReadReq_miss_latency::total 12583000 # number of ReadReq miss cycles 118system.cpu.icache.demand_miss_latency::cpu.inst 12583000 # number of demand (read+write) miss cycles 119system.cpu.icache.demand_miss_latency::total 12583000 # number of demand (read+write) miss cycles 120system.cpu.icache.overall_miss_latency::cpu.inst 12583000 # number of overall miss cycles 121system.cpu.icache.overall_miss_latency::total 12583000 # number of overall miss cycles 122system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) 123system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) 124system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses 125system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses 126system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses 127system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses 128system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses 129system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses 130system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses 131system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses 132system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses 133system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses 134system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257 # average ReadReq miss latency 135system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257 # average ReadReq miss latency 136system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency 137system.cpu.icache.demand_avg_miss_latency::total 52211.618257 # average overall miss latency 138system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency 139system.cpu.icache.overall_avg_miss_latency::total 52211.618257 # average overall miss latency 140system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 141system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 142system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 143system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 144system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 145system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146system.cpu.icache.fast_writes 0 # number of fast writes performed 147system.cpu.icache.cache_copies 0 # number of cache copies performed 148system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 149system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 150system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 151system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 152system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 153system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses 154system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles 155system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles 156system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles 157system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles 158system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles 159system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles 160system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses 161system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses 162system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses 163system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses 164system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses 165system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses 166system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency 167system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency 168system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 169system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 170system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 171system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 172system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 173system.cpu.l2cache.replacements 0 # number of replacements 174system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use 175system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. 176system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. 177system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. 178system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 179system.cpu.l2cache.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor 180system.cpu.l2cache.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor 181system.cpu.l2cache.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy 182system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy 183system.cpu.l2cache.occ_percent::total 0.004702 # Average percentage of cache occupancy 184system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 185system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits 186system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits 187system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 188system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 189system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 190system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 191system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 192system.cpu.l2cache.overall_hits::total 32 # number of overall hits 193system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses 194system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses 195system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses 196system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 197system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 198system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 199system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 200system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses 201system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses 202system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 203system.cpu.l2cache.overall_misses::total 350 # number of overall misses 204system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles 205system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles 206system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles 207system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles 208system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles 209system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles 210system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles 211system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles 212system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles 213system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles 214system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles 215system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) 216system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) 217system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) 218system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 219system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 220system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses 221system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 222system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses 223system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses 224system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 225system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses 226system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses 227system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses 228system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses 229system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 230system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 231system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses 232system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses 233system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses 234system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses 235system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses 236system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses 237system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 238system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 239system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 240system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 241system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 242system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 243system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 244system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 245system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 246system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 247system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 248system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 249system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 250system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 251system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 252system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 253system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 254system.cpu.l2cache.fast_writes 0 # number of fast writes performed 255system.cpu.l2cache.cache_copies 0 # number of cache copies performed 256system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses 257system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 258system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses 259system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 260system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 261system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 262system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 263system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 264system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 265system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 266system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses 267system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles 268system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles 269system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles 270system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles 271system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles 272system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles 273system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles 274system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles 275system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles 276system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles 277system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles 278system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses 279system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses 280system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses 281system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 282system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 283system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses 284system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses 285system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses 286system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses 287system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses 288system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses 289system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 290system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 291system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 292system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 293system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 294system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 295system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 296system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 297system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 298system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 299system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 300system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 301system.cpu.dcache.replacements 0 # number of replacements 302system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use 303system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. 304system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 305system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. 306system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 307system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor 308system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy 309system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy 310system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 311system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 312system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 313system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 314system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 315system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 316system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 317system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 318system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits 319system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits 320system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits 321system.cpu.dcache.overall_hits::total 1918 # number of overall hits 322system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 323system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 324system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 325system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 326system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 327system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 328system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 329system.cpu.dcache.overall_misses::total 141 # number of overall misses 330system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles 331system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles 332system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles 333system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles 334system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles 335system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles 336system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles 337system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles 338system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) 339system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) 340system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 341system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 342system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 343system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 344system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 345system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 346system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses 347system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses 348system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses 349system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses 350system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses 351system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses 352system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 353system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 354system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses 355system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses 356system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses 357system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses 358system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency 359system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency 360system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 361system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 362system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 363system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency 364system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 365system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency 366system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 367system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 368system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 369system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 370system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 371system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 372system.cpu.dcache.fast_writes 0 # number of fast writes performed 373system.cpu.dcache.cache_copies 0 # number of cache copies performed 374system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 375system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 376system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 377system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 378system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 379system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 380system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 381system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 382system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles 383system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles 384system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles 385system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles 386system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles 387system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles 388system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles 389system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles 390system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses 391system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses 392system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 393system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 394system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses 395system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses 396system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses 397system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses 398system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency 399system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency 400system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 401system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 402system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 403system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 404system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 405system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 406system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 407 408---------- End Simulation Statistics ---------- 409