stats.txt revision 10409:8c80b91944c5
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25815000 # Number of ticks simulated 5final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 367819 # Simulator instruction rate (inst/s) 8host_op_rate 428893 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2075494452 # Simulator tick rate (ticks/s) 10host_mem_usage 302164 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4565 # Number of instructions simulated 13sim_ops 5329 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) 32system.membus.trans_dist::ReadReq 307 # Transaction distribution 33system.membus.trans_dist::ReadResp 307 # Transaction distribution 34system.membus.trans_dist::ReadExReq 43 # Transaction distribution 35system.membus.trans_dist::ReadExResp 43 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) 38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 350 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 350 # Request fanout histogram 51system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 53system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 12.2 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 119system.cpu.itb.inst_hits 0 # ITB inst hits 120system.cpu.itb.inst_misses 0 # ITB inst misses 121system.cpu.itb.read_hits 0 # DTB read hits 122system.cpu.itb.read_misses 0 # DTB read misses 123system.cpu.itb.write_hits 0 # DTB write hits 124system.cpu.itb.write_misses 0 # DTB write misses 125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 134system.cpu.itb.read_accesses 0 # DTB read accesses 135system.cpu.itb.write_accesses 0 # DTB write accesses 136system.cpu.itb.inst_accesses 0 # ITB inst accesses 137system.cpu.itb.hits 0 # DTB hits 138system.cpu.itb.misses 0 # DTB misses 139system.cpu.itb.accesses 0 # DTB accesses 140system.cpu.workload.num_syscalls 13 # Number of system calls 141system.cpu.numCycles 51630 # number of cpu cycles simulated 142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 144system.cpu.committedInsts 4565 # Number of instructions committed 145system.cpu.committedOps 5329 # Number of ops (including micro ops) committed 146system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 147system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 148system.cpu.num_func_calls 203 # number of times a function call or return occured 149system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 150system.cpu.num_int_insts 4624 # number of integer instructions 151system.cpu.num_fp_insts 16 # number of float instructions 152system.cpu.num_int_register_reads 7573 # number of times the integer registers were read 153system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 154system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 155system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 156system.cpu.num_cc_register_reads 19184 # number of times the CC registers were read 157system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 158system.cpu.num_mem_refs 1965 # number of memory refs 159system.cpu.num_load_insts 1027 # Number of load instructions 160system.cpu.num_store_insts 938 # Number of store instructions 161system.cpu.num_idle_cycles 0 # Number of idle cycles 162system.cpu.num_busy_cycles 51630 # Number of busy cycles 163system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 164system.cpu.idle_fraction 0 # Percentage of idle cycles 165system.cpu.Branches 1007 # Number of branches fetched 166system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 167system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction 168system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 169system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 170system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 171system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 172system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 173system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 174system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 175system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 176system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 177system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 178system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 179system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 180system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 181system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 182system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 183system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 184system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 185system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 186system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 187system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 188system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 189system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 190system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 191system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 192system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction 193system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction 194system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction 195system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction 196system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 197system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 198system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 199system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 200system.cpu.op_class::total 5390 # Class of executed instruction 201system.cpu.icache.tags.replacements 1 # number of replacements 202system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use 203system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. 204system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 205system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. 206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 207system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor 208system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy 209system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy 210system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 211system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 212system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 213system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 214system.cpu.icache.tags.tag_accesses 9451 # Number of tag accesses 215system.cpu.icache.tags.data_accesses 9451 # Number of data accesses 216system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits 217system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits 218system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits 219system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits 220system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits 221system.cpu.icache.overall_hits::total 4364 # number of overall hits 222system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 223system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 224system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 225system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 226system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 227system.cpu.icache.overall_misses::total 241 # number of overall misses 228system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles 229system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles 230system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles 231system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles 232system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles 233system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles 234system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) 235system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) 236system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses 237system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses 238system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses 239system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses 240system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses 241system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses 242system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses 243system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses 244system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses 245system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses 246system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency 247system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency 248system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency 249system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency 250system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency 251system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency 252system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 253system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 254system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 255system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 256system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 257system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 258system.cpu.icache.fast_writes 0 # number of fast writes performed 259system.cpu.icache.cache_copies 0 # number of cache copies performed 260system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 261system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 262system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 263system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 264system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 265system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses 266system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles 267system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles 268system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles 269system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles 270system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles 271system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles 272system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses 273system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses 274system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses 275system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses 276system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses 277system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses 278system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency 279system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency 280system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency 281system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency 282system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency 283system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency 284system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 285system.cpu.l2cache.tags.replacements 0 # number of replacements 286system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use 287system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 288system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 289system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 290system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 291system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor 292system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor 293system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy 294system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy 295system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy 296system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 297system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 298system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 299system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 300system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses 301system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses 302system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 303system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits 304system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits 305system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 306system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 307system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 308system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 309system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 310system.cpu.l2cache.overall_hits::total 32 # number of overall hits 311system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses 312system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses 313system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses 314system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 315system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 316system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 317system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 318system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses 319system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses 320system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 321system.cpu.l2cache.overall_misses::total 350 # number of overall misses 322system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles 323system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles 324system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles 325system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles 326system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles 327system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles 328system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles 329system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles 330system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles 331system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles 332system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles 333system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) 334system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) 335system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) 336system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 337system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 338system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses 339system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 340system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses 341system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses 342system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 343system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses 344system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses 345system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses 346system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses 347system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 348system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 349system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses 350system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses 351system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses 352system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses 353system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses 354system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses 355system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency 356system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 357system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency 358system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 359system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 360system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency 361system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 362system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency 363system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency 364system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 365system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency 366system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 367system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 368system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 369system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 370system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 371system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 372system.cpu.l2cache.fast_writes 0 # number of fast writes performed 373system.cpu.l2cache.cache_copies 0 # number of cache copies performed 374system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses 375system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 376system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses 377system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 378system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 379system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 380system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 381system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 382system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 383system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 384system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses 385system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles 386system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles 387system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles 388system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles 389system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles 390system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles 391system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles 392system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles 393system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles 394system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles 395system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles 396system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses 397system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses 398system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses 399system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 400system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 401system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses 402system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses 403system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses 404system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses 405system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses 406system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses 407system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 408system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 409system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 410system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 411system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 412system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 413system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 414system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 415system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 416system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 417system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 418system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 419system.cpu.dcache.tags.replacements 0 # number of replacements 420system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use 421system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. 422system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 423system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. 424system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 425system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor 426system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy 427system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy 428system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 429system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 430system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 431system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 432system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses 433system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses 434system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits 435system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits 436system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 437system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 438system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 439system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 440system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 441system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 442system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits 443system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits 444system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits 445system.cpu.dcache.overall_hits::total 1764 # number of overall hits 446system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 447system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 448system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 449system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 450system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 451system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 452system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 453system.cpu.dcache.overall_misses::total 141 # number of overall misses 454system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles 455system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles 456system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles 457system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles 458system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles 459system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles 460system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles 461system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles 462system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) 463system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) 464system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 465system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 466system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 467system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 468system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 469system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 470system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses 471system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses 472system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses 473system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses 474system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses 475system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses 476system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 477system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 478system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses 479system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses 480system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses 481system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses 482system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency 483system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency 484system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 485system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 486system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 487system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency 488system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 489system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency 490system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 491system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 492system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 493system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 494system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 495system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 496system.cpu.dcache.fast_writes 0 # number of fast writes performed 497system.cpu.dcache.cache_copies 0 # number of cache copies performed 498system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 499system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 500system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 501system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 502system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 503system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 504system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 505system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 506system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles 507system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles 508system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles 509system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles 510system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles 511system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles 512system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles 513system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles 514system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses 515system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses 516system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 517system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 518system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses 519system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses 520system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses 521system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses 522system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency 523system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency 524system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 525system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 526system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 527system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 528system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 529system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 530system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 531system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution 532system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 533system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 534system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 535system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) 536system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 537system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) 538system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 539system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 540system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) 541system.cpu.toL2Bus.snoops 0 # Total snoops (count) 542system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram 543system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 544system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 545system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 546system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 547system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 548system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 549system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 550system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 551system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram 552system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 553system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 554system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 555system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 556system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram 557system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) 558system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 559system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 560system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 561system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 562system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 563 564---------- End Simulation Statistics ---------- 565