stats.txt revision 10038:7eccd14e2610
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25969000 # Number of ticks simulated 5final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 122117 # Simulator instruction rate (inst/s) 8host_op_rate 151672 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 694181161 # Simulator tick rate (ticks/s) 10host_mem_usage 266760 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host 12sim_insts 4565 # Number of instructions simulated 13sim_ops 5672 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) 32system.membus.throughput 862566907 # Throughput (bytes/s) 33system.membus.trans_dist::ReadReq 307 # Transaction distribution 34system.membus.trans_dist::ReadResp 307 # Transaction distribution 35system.membus.trans_dist::ReadExReq 43 # Transaction distribution 36system.membus.trans_dist::ReadExResp 43 # Transaction distribution 37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) 38system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) 39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) 40system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) 41system.membus.data_through_bus 22400 # Total data (bytes) 42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 43system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks) 44system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 45system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks) 46system.membus.respLayer1.utilization 12.1 # Layer utilization (%) 47system.cpu_clk_domain.clock 500 # Clock period in ticks 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.inst_hits 0 # ITB inst hits 70system.cpu.dtb.inst_misses 0 # ITB inst misses 71system.cpu.dtb.read_hits 0 # DTB read hits 72system.cpu.dtb.read_misses 0 # DTB read misses 73system.cpu.dtb.write_hits 0 # DTB write hits 74system.cpu.dtb.write_misses 0 # DTB write misses 75system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 76system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 77system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 78system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 79system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 80system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 81system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 82system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 83system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 84system.cpu.dtb.read_accesses 0 # DTB read accesses 85system.cpu.dtb.write_accesses 0 # DTB write accesses 86system.cpu.dtb.inst_accesses 0 # ITB inst accesses 87system.cpu.dtb.hits 0 # DTB hits 88system.cpu.dtb.misses 0 # DTB misses 89system.cpu.dtb.accesses 0 # DTB accesses 90system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 91system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 92system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 93system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 94system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 95system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 96system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 97system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 98system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 99system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 100system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 101system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 102system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 103system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 104system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 105system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 106system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 107system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 108system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 109system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 110system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 111system.cpu.itb.inst_hits 0 # ITB inst hits 112system.cpu.itb.inst_misses 0 # ITB inst misses 113system.cpu.itb.read_hits 0 # DTB read hits 114system.cpu.itb.read_misses 0 # DTB read misses 115system.cpu.itb.write_hits 0 # DTB write hits 116system.cpu.itb.write_misses 0 # DTB write misses 117system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.itb.read_accesses 0 # DTB read accesses 127system.cpu.itb.write_accesses 0 # DTB write accesses 128system.cpu.itb.inst_accesses 0 # ITB inst accesses 129system.cpu.itb.hits 0 # DTB hits 130system.cpu.itb.misses 0 # DTB misses 131system.cpu.itb.accesses 0 # DTB accesses 132system.cpu.workload.num_syscalls 13 # Number of system calls 133system.cpu.numCycles 51938 # number of cpu cycles simulated 134system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 135system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 136system.cpu.committedInsts 4565 # Number of instructions committed 137system.cpu.committedOps 5672 # Number of ops (including micro ops) committed 138system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses 139system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 140system.cpu.num_func_calls 203 # number of times a function call or return occured 141system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls 142system.cpu.num_int_insts 4976 # number of integer instructions 143system.cpu.num_fp_insts 16 # number of float instructions 144system.cpu.num_int_register_reads 28821 # number of times the integer registers were read 145system.cpu.num_int_register_writes 5334 # number of times the integer registers were written 146system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 147system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 148system.cpu.num_mem_refs 2138 # number of memory refs 149system.cpu.num_load_insts 1200 # Number of load instructions 150system.cpu.num_store_insts 938 # Number of store instructions 151system.cpu.num_idle_cycles 0 # Number of idle cycles 152system.cpu.num_busy_cycles 51938 # Number of busy cycles 153system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 154system.cpu.idle_fraction 0 # Percentage of idle cycles 155system.cpu.icache.tags.replacements 1 # number of replacements 156system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use 157system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. 158system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 159system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. 160system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 161system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor 162system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy 163system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy 164system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 165system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 166system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 167system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 168system.cpu.icache.tags.tag_accesses 9451 # Number of tag accesses 169system.cpu.icache.tags.data_accesses 9451 # Number of data accesses 170system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits 171system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits 172system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits 173system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits 174system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits 175system.cpu.icache.overall_hits::total 4364 # number of overall hits 176system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 177system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 178system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 179system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 180system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 181system.cpu.icache.overall_misses::total 241 # number of overall misses 182system.cpu.icache.ReadReq_miss_latency::cpu.inst 12583000 # number of ReadReq miss cycles 183system.cpu.icache.ReadReq_miss_latency::total 12583000 # number of ReadReq miss cycles 184system.cpu.icache.demand_miss_latency::cpu.inst 12583000 # number of demand (read+write) miss cycles 185system.cpu.icache.demand_miss_latency::total 12583000 # number of demand (read+write) miss cycles 186system.cpu.icache.overall_miss_latency::cpu.inst 12583000 # number of overall miss cycles 187system.cpu.icache.overall_miss_latency::total 12583000 # number of overall miss cycles 188system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) 189system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) 190system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses 191system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses 192system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses 193system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses 194system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses 195system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses 196system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses 197system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses 198system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses 199system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses 200system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257 # average ReadReq miss latency 201system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257 # average ReadReq miss latency 202system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency 203system.cpu.icache.demand_avg_miss_latency::total 52211.618257 # average overall miss latency 204system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency 205system.cpu.icache.overall_avg_miss_latency::total 52211.618257 # average overall miss latency 206system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 207system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 208system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 209system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 210system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 211system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 212system.cpu.icache.fast_writes 0 # number of fast writes performed 213system.cpu.icache.cache_copies 0 # number of cache copies performed 214system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 215system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 216system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 217system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 218system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 219system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses 220system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles 221system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles 222system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles 223system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles 224system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles 225system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles 226system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses 227system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses 228system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses 229system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses 230system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses 231system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses 232system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency 233system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency 234system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 235system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 236system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 237system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 238system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 239system.cpu.l2cache.tags.replacements 0 # number of replacements 240system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use 241system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 242system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 243system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 244system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 245system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor 246system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor 247system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy 248system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy 249system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy 250system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 251system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 252system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 253system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 254system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses 255system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses 256system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 257system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits 258system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits 259system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 260system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 261system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 262system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 263system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 264system.cpu.l2cache.overall_hits::total 32 # number of overall hits 265system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses 266system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses 267system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses 268system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 269system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 270system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 271system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 272system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses 273system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses 274system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 275system.cpu.l2cache.overall_misses::total 350 # number of overall misses 276system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles 277system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles 278system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles 279system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles 280system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles 281system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles 282system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles 283system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles 284system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles 285system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles 286system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles 287system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) 288system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) 289system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) 290system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 291system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 292system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses 293system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 294system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses 295system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses 296system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 297system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses 298system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses 299system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses 300system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses 301system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 302system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 303system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses 304system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses 305system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses 306system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses 307system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses 308system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses 309system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 310system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 311system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 312system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 313system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 314system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 315system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 316system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 317system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 318system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 319system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 320system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 321system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 322system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 323system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 324system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 325system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 326system.cpu.l2cache.fast_writes 0 # number of fast writes performed 327system.cpu.l2cache.cache_copies 0 # number of cache copies performed 328system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses 329system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 330system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses 331system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 332system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 333system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 334system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 335system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 336system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 337system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 338system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses 339system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles 340system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles 341system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles 342system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles 343system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles 344system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles 345system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles 346system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles 347system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles 348system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles 349system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles 350system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses 351system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses 352system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses 353system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 354system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 355system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses 356system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses 357system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses 358system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses 359system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses 360system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses 361system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 362system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 363system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 364system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 365system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 366system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 367system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 368system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 369system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 370system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 371system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 372system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 373system.cpu.dcache.tags.replacements 0 # number of replacements 374system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use 375system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks. 376system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 377system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks. 378system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 379system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor 380system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy 381system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy 382system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 383system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 384system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id 385system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 386system.cpu.dcache.tags.tag_accesses 4303 # Number of tag accesses 387system.cpu.dcache.tags.data_accesses 4303 # Number of data accesses 388system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 389system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 390system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 391system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 392system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 393system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 394system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 395system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 396system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits 397system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits 398system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits 399system.cpu.dcache.overall_hits::total 1918 # number of overall hits 400system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 401system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 402system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 403system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 404system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 405system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 406system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 407system.cpu.dcache.overall_misses::total 141 # number of overall misses 408system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles 409system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles 410system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles 411system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles 412system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles 413system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles 414system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles 415system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles 416system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) 417system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) 418system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 419system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 420system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 421system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 422system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 423system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 424system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses 425system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses 426system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses 427system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses 428system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses 429system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses 430system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 431system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 432system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses 433system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses 434system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses 435system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses 436system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency 437system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency 438system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 439system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 440system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 441system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency 442system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 443system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency 444system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 445system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 446system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 447system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 448system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 449system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 450system.cpu.dcache.fast_writes 0 # number of fast writes performed 451system.cpu.dcache.cache_copies 0 # number of cache copies performed 452system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 453system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 454system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 455system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 456system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 457system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 458system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 459system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 460system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles 461system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles 462system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles 463system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles 464system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles 465system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles 466system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles 467system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles 468system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses 469system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses 470system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 471system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 472system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses 473system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses 474system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses 475system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses 476system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency 477system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency 478system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 479system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 480system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 481system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 482system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 483system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 484system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 485system.cpu.toL2Bus.throughput 941430167 # Throughput (bytes/s) 486system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution 487system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 488system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 489system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 490system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) 491system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 492system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) 493system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 494system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 495system.cpu.toL2Bus.tot_pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) 496system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes) 497system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 498system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) 499system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 500system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 501system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 502system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 503system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 504 505---------- End Simulation Statistics ---------- 506