stats.txt revision 10726:8a20e2a1562d
19241Sandreas.hansson@arm.com 29241Sandreas.hansson@arm.com---------- Begin Simulation Statistics ---------- 39241Sandreas.hansson@arm.comsim_seconds 0.000003 # Number of seconds simulated 49241Sandreas.hansson@arm.comsim_ticks 2694500 # Number of ticks simulated 59241Sandreas.hansson@arm.comfinal_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 69241Sandreas.hansson@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 79241Sandreas.hansson@arm.comhost_inst_rate 801222 # Simulator instruction rate (inst/s) 89241Sandreas.hansson@arm.comhost_op_rate 936270 # Simulator op (including micro ops) rate (op/s) 99241Sandreas.hansson@arm.comhost_tick_rate 468120222 # Simulator tick rate (ticks/s) 109241Sandreas.hansson@arm.comhost_mem_usage 297024 # Number of bytes of host memory used 119241Sandreas.hansson@arm.comhost_seconds 0.01 # Real time elapsed on the host 129241Sandreas.hansson@arm.comsim_insts 4591 # Number of instructions simulated 139241Sandreas.hansson@arm.comsim_ops 5377 # Number of ops (including micro ops) simulated 149241Sandreas.hansson@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 159241Sandreas.hansson@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 169241Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 179241Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 189241Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 22907 # Number of bytes read from this memory 199241Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory 209241Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory 219241Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 229241Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 3648 # Number of bytes written to this memory 239241Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory 249241Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory 259241Sandreas.hansson@arm.comsystem.physmem.num_reads::total 5607 # Number of read requests responded to by this memory 269241Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory 279241Sandreas.hansson@arm.comsystem.physmem.num_writes::total 924 # Number of write requests responded to by this memory 289241Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) 299241Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) 309241Sandreas.hansson@arm.comsystem.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) 319241Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) 329241Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) 339241Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) 349241Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) 359241Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) 369241Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) 379241Sandreas.hansson@arm.comsystem.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) 389241Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 399241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 409241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 419241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 429241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 439241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 449241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 469241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 479241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 489402Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 499241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 509241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 519241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 529241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 539241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 549241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 559241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 569241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 579241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 589241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 599241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 609241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 619241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 629241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 639241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 649241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 659241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 669241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 679241Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 689241Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 699241Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 709294Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 719294Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 729241Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 739241Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 749241Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 759241Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 769241Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 779241Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 789241Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 799241Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 809241Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 819241Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 829241Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 839241Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 849241Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 859241Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 869241Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 879524SAndreas.Sandberg@ARM.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 889241Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 899241Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 909241Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 919241Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 929241Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 939241Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 949241Sandreas.hansson@arm.comsystem.cpu.dtb.hits 0 # DTB hits 959241Sandreas.hansson@arm.comsystem.cpu.dtb.misses 0 # DTB misses 969241Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 979241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 989241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 999241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1009241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1019241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1029524SAndreas.Sandberg@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1039241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1049241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1059241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1069241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1079241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1089241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1099241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1109241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1119241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1129342SAndreas.Sandberg@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1139241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1149241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1159241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1169342SAndreas.Sandberg@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1179241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1189241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1199241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1209241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1219241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1229241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1239241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1249241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1259241Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1269241Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 1279241Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1289241Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1299241Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1309241Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1319241Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1329241Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1339241Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1349241Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 1359241Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 1369241Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 1379241Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 1389241Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 1399241Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 1409241Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 1419241Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1429241Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1439241Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1449241Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 1459241Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1469241Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1479241Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1489241Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1499241Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 1509241Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 1519241Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 1529241Sandreas.hansson@arm.comsystem.cpu.itb.hits 0 # DTB hits 1539241Sandreas.hansson@arm.comsystem.cpu.itb.misses 0 # DTB misses 1549241Sandreas.hansson@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 1559241Sandreas.hansson@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 1569241Sandreas.hansson@arm.comsystem.cpu.numCycles 5390 # number of cpu cycles simulated 1579241Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1589241Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1599241Sandreas.hansson@arm.comsystem.cpu.committedInsts 4591 # Number of instructions committed 1609241Sandreas.hansson@arm.comsystem.cpu.committedOps 5377 # Number of ops (including micro ops) committed 1619241Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 1629241Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 1639241Sandreas.hansson@arm.comsystem.cpu.num_func_calls 203 # number of times a function call or return occured 1649241Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 1659241Sandreas.hansson@arm.comsystem.cpu.num_int_insts 4624 # number of integer instructions 1669241Sandreas.hansson@arm.comsystem.cpu.num_fp_insts 16 # number of float instructions 1679241Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 7607 # number of times the integer registers were read 1689241Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 2728 # number of times the integer registers were written 1699241Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 16 # number of times the floating registers were read 1709241Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 1719241Sandreas.hansson@arm.comsystem.cpu.num_cc_register_reads 16172 # number of times the CC registers were read 1729241Sandreas.hansson@arm.comsystem.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 1739241Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 1965 # number of memory refs 1749241Sandreas.hansson@arm.comsystem.cpu.num_load_insts 1027 # Number of load instructions 1759241Sandreas.hansson@arm.comsystem.cpu.num_store_insts 938 # Number of store instructions 1769241Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 0.002000 # Number of idle cycles 1779241Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 5389.998000 # Number of busy cycles 1789241Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 1799241Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.000000 # Percentage of idle cycles 1809241Sandreas.hansson@arm.comsystem.cpu.Branches 1007 # Number of branches fetched 1819241Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 1829241Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction 1839241Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 1849241Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 1859241Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 1869241Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 1879241Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 1889241Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 1899241Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 1909241Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 1919241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 1929241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 1939241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 1949241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 1959241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 1969241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 1979241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 1989241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 1999241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 2009241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 2019241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 2029241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 2039241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 2049241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 2059241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 2069241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 2079241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction 2089241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction 2099241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction 2109241Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction 2119241Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 2129241Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 2139241Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 2149241Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 2159241Sandreas.hansson@arm.comsystem.cpu.op_class::total 5390 # Class of executed instruction 2169241Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 5596 # Transaction distribution 2179241Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 5607 # Transaction distribution 2189241Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 913 # Transaction distribution 2199241Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 913 # Transaction distribution 2209241Sandreas.hansson@arm.comsystem.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 2219241Sandreas.hansson@arm.comsystem.membus.trans_dist::StoreCondReq 11 # Transaction distribution 2229241Sandreas.hansson@arm.comsystem.membus.trans_dist::StoreCondResp 11 # Transaction distribution 2239241Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) 2249241Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 2259241Sandreas.hansson@arm.comsystem.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) 2269241Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) 2279241Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 2289241Sandreas.hansson@arm.comsystem.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) 2299241Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 2309241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 6531 # Request fanout histogram 2319241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 2.704946 # Request fanout histogram 2329241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram 2339241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2349241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2359241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2369241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram 2379241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram 2389241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2399241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 2 # Request fanout histogram 2409241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 3 # Request fanout histogram 2419241Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 6531 # Request fanout histogram 2429241Sandreas.hansson@arm.com 2439241Sandreas.hansson@arm.com---------- End Simulation Statistics ---------- 2449241Sandreas.hansson@arm.com