config.ini revision 10038:7eccd14e2610
112771Sqtt2@cornell.edu[root] 212771Sqtt2@cornell.edutype=Root 312771Sqtt2@cornell.educhildren=system 412771Sqtt2@cornell.edueventq_index=0 512771Sqtt2@cornell.edufull_system=false 612771Sqtt2@cornell.edusim_quantum=0 712771Sqtt2@cornell.edutime_sync_enable=false 812771Sqtt2@cornell.edutime_sync_period=100000000000 912771Sqtt2@cornell.edutime_sync_spin_threshold=100000000 1012771Sqtt2@cornell.edu 1112771Sqtt2@cornell.edu[system] 1212771Sqtt2@cornell.edutype=System 1312771Sqtt2@cornell.educhildren=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 1412771Sqtt2@cornell.eduboot_osflags=a 1512771Sqtt2@cornell.educache_line_size=64 1612771Sqtt2@cornell.educlk_domain=system.clk_domain 1712771Sqtt2@cornell.edueventq_index=0 1812771Sqtt2@cornell.eduinit_param=0 1912771Sqtt2@cornell.edukernel= 2012771Sqtt2@cornell.eduload_addr_mask=1099511627775 2112771Sqtt2@cornell.eduload_offset=0 2212771Sqtt2@cornell.edumem_mode=atomic 2312771Sqtt2@cornell.edumem_ranges= 2412771Sqtt2@cornell.edumemories=system.physmem 2512771Sqtt2@cornell.edunum_work_ids=16 2612771Sqtt2@cornell.edureadfile= 2712771Sqtt2@cornell.edusymbolfile= 2812771Sqtt2@cornell.eduwork_begin_ckpt_count=0 2912771Sqtt2@cornell.eduwork_begin_cpu_id_exit=-1 3012771Sqtt2@cornell.eduwork_begin_exit_count=0 3112771Sqtt2@cornell.eduwork_cpus_ckpt_count=0 3212771Sqtt2@cornell.eduwork_end_ckpt_count=0 3312771Sqtt2@cornell.eduwork_end_exit_count=0 3412771Sqtt2@cornell.eduwork_item_id=-1 3512771Sqtt2@cornell.edusystem_port=system.membus.slave[0] 3612771Sqtt2@cornell.edu 3712771Sqtt2@cornell.edu[system.clk_domain] 3812771Sqtt2@cornell.edutype=SrcClockDomain 3912771Sqtt2@cornell.educlock=1000 4012771Sqtt2@cornell.edueventq_index=0 4112771Sqtt2@cornell.eduvoltage_domain=system.voltage_domain 4212771Sqtt2@cornell.edu 4312771Sqtt2@cornell.edu[system.cpu] 4412771Sqtt2@cornell.edutype=AtomicSimpleCPU 4512771Sqtt2@cornell.educhildren=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload 4612771Sqtt2@cornell.educhecker=Null 4712771Sqtt2@cornell.educlk_domain=system.cpu_clk_domain 4812771Sqtt2@cornell.educpu_id=0 4912771Sqtt2@cornell.edudo_checkpoint_insts=true 5012771Sqtt2@cornell.edudo_quiesce=true 5112771Sqtt2@cornell.edudo_statistics_insts=true 5212771Sqtt2@cornell.edudstage2_mmu=system.cpu.dstage2_mmu 5312771Sqtt2@cornell.edudtb=system.cpu.dtb 5412771Sqtt2@cornell.edueventq_index=0 5512771Sqtt2@cornell.edufastmem=false 5612771Sqtt2@cornell.edufunction_trace=false 5712771Sqtt2@cornell.edufunction_trace_start=0 5812771Sqtt2@cornell.eduinterrupts=system.cpu.interrupts 5912771Sqtt2@cornell.eduisa=system.cpu.isa 6012771Sqtt2@cornell.eduistage2_mmu=system.cpu.istage2_mmu 6112771Sqtt2@cornell.eduitb=system.cpu.itb 6212771Sqtt2@cornell.edumax_insts_all_threads=0 6312771Sqtt2@cornell.edumax_insts_any_thread=0 6412771Sqtt2@cornell.edumax_loads_all_threads=0 6512771Sqtt2@cornell.edumax_loads_any_thread=0 6612771Sqtt2@cornell.edunumThreads=1 6712771Sqtt2@cornell.eduprofile=0 6812771Sqtt2@cornell.eduprogress_interval=0 6912771Sqtt2@cornell.edusimpoint_interval=100000000 7012771Sqtt2@cornell.edusimpoint_profile=false 7112771Sqtt2@cornell.edusimpoint_profile_file=simpoint.bb.gz 7212771Sqtt2@cornell.edusimpoint_start_insts= 7312771Sqtt2@cornell.edusimulate_data_stalls=false 7412771Sqtt2@cornell.edusimulate_inst_stalls=false 7512771Sqtt2@cornell.eduswitched_out=false 7612771Sqtt2@cornell.edusystem=system 7712771Sqtt2@cornell.edutracer=system.cpu.tracer 7812771Sqtt2@cornell.eduwidth=1 7912771Sqtt2@cornell.eduworkload=system.cpu.workload 8012771Sqtt2@cornell.edudcache_port=system.membus.slave[2] 8112771Sqtt2@cornell.eduicache_port=system.membus.slave[1] 8212771Sqtt2@cornell.edu 8312771Sqtt2@cornell.edu[system.cpu.dstage2_mmu] 8412771Sqtt2@cornell.edutype=ArmStage2MMU 8512771Sqtt2@cornell.educhildren=stage2_tlb 8612771Sqtt2@cornell.edueventq_index=0 8712771Sqtt2@cornell.edustage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 8812771Sqtt2@cornell.edutlb=system.cpu.dtb 8912771Sqtt2@cornell.edu 9012771Sqtt2@cornell.edu[system.cpu.dstage2_mmu.stage2_tlb] 91type=ArmTLB 92children=walker 93eventq_index=0 94is_stage2=true 95size=32 96walker=system.cpu.dstage2_mmu.stage2_tlb.walker 97 98[system.cpu.dstage2_mmu.stage2_tlb.walker] 99type=ArmTableWalker 100clk_domain=system.cpu_clk_domain 101eventq_index=0 102is_stage2=true 103num_squash_per_cycle=2 104sys=system 105port=system.membus.slave[6] 106 107[system.cpu.dtb] 108type=ArmTLB 109children=walker 110eventq_index=0 111is_stage2=false 112size=64 113walker=system.cpu.dtb.walker 114 115[system.cpu.dtb.walker] 116type=ArmTableWalker 117clk_domain=system.cpu_clk_domain 118eventq_index=0 119is_stage2=false 120num_squash_per_cycle=2 121sys=system 122port=system.membus.slave[4] 123 124[system.cpu.interrupts] 125type=ArmInterrupts 126eventq_index=0 127 128[system.cpu.isa] 129type=ArmISA 130eventq_index=0 131fpsid=1090793632 132id_aa64afr0_el1=0 133id_aa64afr1_el1=0 134id_aa64dfr0_el1=1052678 135id_aa64dfr1_el1=0 136id_aa64isar0_el1=0 137id_aa64isar1_el1=0 138id_aa64mmfr0_el1=15728642 139id_aa64mmfr1_el1=0 140id_aa64pfr0_el1=17 141id_aa64pfr1_el1=0 142id_isar0=34607377 143id_isar1=34677009 144id_isar2=555950401 145id_isar3=17899825 146id_isar4=268501314 147id_isar5=0 148id_mmfr0=270536963 149id_mmfr1=0 150id_mmfr2=19070976 151id_mmfr3=34611729 152id_pfr0=49 153id_pfr1=4113 154midr=1091551472 155system=system 156 157[system.cpu.istage2_mmu] 158type=ArmStage2MMU 159children=stage2_tlb 160eventq_index=0 161stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 162tlb=system.cpu.itb 163 164[system.cpu.istage2_mmu.stage2_tlb] 165type=ArmTLB 166children=walker 167eventq_index=0 168is_stage2=true 169size=32 170walker=system.cpu.istage2_mmu.stage2_tlb.walker 171 172[system.cpu.istage2_mmu.stage2_tlb.walker] 173type=ArmTableWalker 174clk_domain=system.cpu_clk_domain 175eventq_index=0 176is_stage2=true 177num_squash_per_cycle=2 178sys=system 179port=system.membus.slave[5] 180 181[system.cpu.itb] 182type=ArmTLB 183children=walker 184eventq_index=0 185is_stage2=false 186size=64 187walker=system.cpu.itb.walker 188 189[system.cpu.itb.walker] 190type=ArmTableWalker 191clk_domain=system.cpu_clk_domain 192eventq_index=0 193is_stage2=false 194num_squash_per_cycle=2 195sys=system 196port=system.membus.slave[3] 197 198[system.cpu.tracer] 199type=ExeTracer 200eventq_index=0 201 202[system.cpu.workload] 203type=LiveProcess 204cmd=hello 205cwd= 206egid=100 207env= 208errout=cerr 209euid=100 210eventq_index=0 211executable=/dist/test-progs/hello/bin/arm/linux/hello 212gid=100 213input=cin 214max_stack_size=67108864 215output=cout 216pid=100 217ppid=99 218simpoint=0 219system=system 220uid=100 221 222[system.cpu_clk_domain] 223type=SrcClockDomain 224clock=500 225eventq_index=0 226voltage_domain=system.voltage_domain 227 228[system.membus] 229type=CoherentBus 230clk_domain=system.clk_domain 231eventq_index=0 232header_cycles=1 233system=system 234use_default_range=false 235width=8 236master=system.physmem.port 237slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 238 239[system.physmem] 240type=SimpleMemory 241bandwidth=73.000000 242clk_domain=system.clk_domain 243conf_table_reported=true 244eventq_index=0 245in_addr_map=true 246latency=30000 247latency_var=0 248null=false 249range=0:134217727 250port=system.membus.master[0] 251 252[system.voltage_domain] 253type=VoltageDomain 254eventq_index=0 255voltage=1.000000 256 257