stats.txt revision 9285:9901180cd573
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10412000 # Number of ticks simulated 5final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 40558 # Simulator instruction rate (inst/s) 8host_op_rate 50593 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 91854675 # Simulator tick rate (ticks/s) 10host_mem_usage 232720 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host 12sim_insts 4596 # Number of instructions simulated 13sim_ops 5734 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25600 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 400 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 41system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 42system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 43system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 44system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45system.cpu.dtb.read_accesses 0 # DTB read accesses 46system.cpu.dtb.write_accesses 0 # DTB write accesses 47system.cpu.dtb.inst_accesses 0 # ITB inst accesses 48system.cpu.dtb.hits 0 # DTB hits 49system.cpu.dtb.misses 0 # DTB misses 50system.cpu.dtb.accesses 0 # DTB accesses 51system.cpu.itb.inst_hits 0 # ITB inst hits 52system.cpu.itb.inst_misses 0 # ITB inst misses 53system.cpu.itb.read_hits 0 # DTB read hits 54system.cpu.itb.read_misses 0 # DTB read misses 55system.cpu.itb.write_hits 0 # DTB write hits 56system.cpu.itb.write_misses 0 # DTB write misses 57system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 13 # Number of system calls 73system.cpu.numCycles 20825 # number of cpu cycles simulated 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.BPredUnit.lookups 2492 # Number of BP lookups 77system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted 78system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect 79system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups 80system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits 81system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 82system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. 83system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. 84system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss 85system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed 86system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered 87system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken 88system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked 89system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing 90system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked 91system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 92system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched 93system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed 94system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle 112system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle 113system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle 114system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked 115system.cpu.decode.RunCycles 2432 # Number of cycles decode is running 116system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking 117system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing 118system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch 119system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction 120system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode 121system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode 122system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing 123system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle 124system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking 125system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst 126system.cpu.rename.RunCycles 2229 # Number of cycles rename is running 127system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking 128system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename 129system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full 130system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full 131system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed 132system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made 133system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups 134system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups 135system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed 136system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing 137system.cpu.rename.serializingInsts 47 # count of serializing insts renamed 138system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed 139system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer 140system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. 141system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. 142system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. 143system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. 144system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) 145system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ 146system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued 147system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 148system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling 149system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph 150system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed 151system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle 168system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 169system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available 170system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available 171system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available 172system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available 173system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available 174system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available 175system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available 176system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available 177system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available 198system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available 199system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available 200system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 201system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 202system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 203system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued 204system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued 205system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued 206system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued 207system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued 208system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued 209system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued 210system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued 211system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued 232system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued 233system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued 234system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 235system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 236system.cpu.iq.FU_type_0::total 8838 # Type of FU issued 237system.cpu.iq.rate 0.424394 # Inst issue rate 238system.cpu.iq.fu_busy_cnt 221 # FU busy when requested 239system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) 240system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads 241system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes 242system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses 243system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 244system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 245system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 246system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses 247system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 248system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores 249system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 250system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed 251system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed 252system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 253system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed 254system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 255system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 256system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 257system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 258system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 259system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing 260system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking 261system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking 262system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ 263system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch 264system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions 265system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions 266system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions 267system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall 268system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 269system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 270system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly 271system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly 272system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute 273system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions 274system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed 275system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute 276system.cpu.iew.exec_swp 0 # number of swp insts executed 277system.cpu.iew.exec_nop 0 # number of nop insts executed 278system.cpu.iew.exec_refs 3246 # number of memory reference insts executed 279system.cpu.iew.exec_branches 1415 # Number of branches executed 280system.cpu.iew.exec_stores 1167 # Number of stores executed 281system.cpu.iew.exec_rate 0.404994 # Inst execution rate 282system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit 283system.cpu.iew.wb_count 7997 # cumulative count of insts written-back 284system.cpu.iew.wb_producers 3850 # num instructions producing a value 285system.cpu.iew.wb_consumers 7766 # num instructions consuming a value 286system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 287system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle 288system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back 289system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 290system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit 291system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards 292system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted 293system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle 310system.cpu.commit.committedInsts 4596 # Number of instructions committed 311system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed 312system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 313system.cpu.commit.refs 2140 # Number of memory references committed 314system.cpu.commit.loads 1201 # Number of loads committed 315system.cpu.commit.membars 12 # Number of memory barriers committed 316system.cpu.commit.branches 1008 # Number of branches committed 317system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 318system.cpu.commit.int_insts 4980 # Number of committed integer instructions. 319system.cpu.commit.function_calls 82 # Number of function calls committed. 320system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached 321system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 322system.cpu.rob.rob_reads 22290 # The number of ROB reads 323system.cpu.rob.rob_writes 23328 # The number of ROB writes 324system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself 325system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling 326system.cpu.committedInsts 4596 # Number of Instructions Simulated 327system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated 328system.cpu.committedInsts_total 4596 # Number of Instructions Simulated 329system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction 330system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads 331system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle 332system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads 333system.cpu.int_regfile_reads 38756 # number of integer regfile reads 334system.cpu.int_regfile_writes 7886 # number of integer regfile writes 335system.cpu.fp_regfile_reads 16 # number of floating regfile reads 336system.cpu.misc_regfile_reads 15116 # number of misc regfile reads 337system.cpu.misc_regfile_writes 26 # number of misc regfile writes 338system.cpu.icache.replacements 3 # number of replacements 339system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use 340system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. 341system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. 342system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. 343system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 344system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor 345system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy 346system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy 347system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits 348system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits 349system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits 350system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits 351system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits 352system.cpu.icache.overall_hits::total 1564 # number of overall hits 353system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses 354system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses 355system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses 356system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses 357system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses 358system.cpu.icache.overall_misses::total 368 # number of overall misses 359system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles 360system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles 361system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles 362system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles 363system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles 364system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles 365system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) 366system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) 367system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses 368system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses 369system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses 370system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses 371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses 372system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses 373system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses 374system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses 375system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses 376system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses 377system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency 378system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency 379system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency 380system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency 381system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency 382system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency 383system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 384system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 385system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 386system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 387system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 388system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 389system.cpu.icache.fast_writes 0 # number of fast writes performed 390system.cpu.icache.cache_copies 0 # number of cache copies performed 391system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits 392system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 393system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits 394system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 395system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits 396system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits 397system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 398system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 399system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 400system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 401system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 402system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 403system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles 404system.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles 405system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles 406system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles 407system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles 408system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles 409system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses 410system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses 411system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses 412system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses 413system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses 414system.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses 415system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency 416system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency 417system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency 418system.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency 419system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency 420system.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency 421system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 422system.cpu.dcache.replacements 0 # number of replacements 423system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use 424system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. 425system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. 426system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. 427system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 428system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor 429system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy 430system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy 431system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits 432system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits 433system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 434system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 435system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits 436system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits 437system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits 438system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits 439system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits 440system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits 441system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits 442system.cpu.dcache.overall_hits::total 2306 # number of overall hits 443system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses 444system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses 445system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 446system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 447system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 448system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 449system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses 450system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses 451system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses 452system.cpu.dcache.overall_misses::total 502 # number of overall misses 453system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles 454system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles 455system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles 456system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles 457system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles 458system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles 459system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles 460system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles 461system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles 462system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles 463system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) 464system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) 465system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 466system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 467system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) 468system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) 469system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) 470system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) 471system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses 472system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses 473system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses 474system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses 475system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses 476system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses 477system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 478system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 479system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses 480system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses 481system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses 482system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses 483system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses 484system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses 485system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency 486system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency 487system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency 488system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency 489system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency 490system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency 491system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency 492system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency 493system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency 494system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency 495system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 496system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 497system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 498system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 499system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 500system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 501system.cpu.dcache.fast_writes 0 # number of fast writes performed 502system.cpu.dcache.cache_copies 0 # number of cache copies performed 503system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits 504system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits 505system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 506system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 507system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 508system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 509system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 510system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 511system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 512system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits 513system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 514system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 515system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 516system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 517system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 518system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 519system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 520system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 521system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3549000 # number of ReadReq MSHR miss cycles 522system.cpu.dcache.ReadReq_mshr_miss_latency::total 3549000 # number of ReadReq MSHR miss cycles 523system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1700000 # number of WriteReq MSHR miss cycles 524system.cpu.dcache.WriteReq_mshr_miss_latency::total 1700000 # number of WriteReq MSHR miss cycles 525system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5249000 # number of demand (read+write) MSHR miss cycles 526system.cpu.dcache.demand_mshr_miss_latency::total 5249000 # number of demand (read+write) MSHR miss cycles 527system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5249000 # number of overall MSHR miss cycles 528system.cpu.dcache.overall_mshr_miss_latency::total 5249000 # number of overall MSHR miss cycles 529system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055409 # mshr miss rate for ReadReq accesses 530system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055409 # mshr miss rate for ReadReq accesses 531system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 532system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 533system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for demand accesses 534system.cpu.dcache.demand_mshr_miss_rate::total 0.052350 # mshr miss rate for demand accesses 535system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for overall accesses 536system.cpu.dcache.overall_mshr_miss_rate::total 0.052350 # mshr miss rate for overall accesses 537system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33800 # average ReadReq mshr miss latency 538system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33800 # average ReadReq mshr miss latency 539system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40476.190476 # average WriteReq mshr miss latency 540system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40476.190476 # average WriteReq mshr miss latency 541system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency 542system.cpu.dcache.demand_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency 543system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency 544system.cpu.dcache.overall_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency 545system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 546system.cpu.l2cache.replacements 0 # number of replacements 547system.cpu.l2cache.tagsinuse 188.003042 # Cycle average of tags in use 548system.cpu.l2cache.total_refs 37 # Total number of references to valid blocks. 549system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. 550system.cpu.l2cache.avg_refs 0.103352 # Average number of references to valid blocks. 551system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 552system.cpu.l2cache.occ_blocks::cpu.inst 141.702568 # Average occupied blocks per requestor 553system.cpu.l2cache.occ_blocks::cpu.data 46.300474 # Average occupied blocks per requestor 554system.cpu.l2cache.occ_percent::cpu.inst 0.004324 # Average percentage of cache occupancy 555system.cpu.l2cache.occ_percent::cpu.data 0.001413 # Average percentage of cache occupancy 556system.cpu.l2cache.occ_percent::total 0.005737 # Average percentage of cache occupancy 557system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 558system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 559system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits 560system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 561system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 562system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits 563system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 564system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 565system.cpu.l2cache.overall_hits::total 37 # number of overall hits 566system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 567system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses 568system.cpu.l2cache.ReadReq_misses::total 364 # number of ReadReq misses 569system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 570system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 571system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 572system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 573system.cpu.l2cache.demand_misses::total 406 # number of demand (read+write) misses 574system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses 575system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 576system.cpu.l2cache.overall_misses::total 406 # number of overall misses 577system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10097000 # number of ReadReq miss cycles 578system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3413000 # number of ReadReq miss cycles 579system.cpu.l2cache.ReadReq_miss_latency::total 13510000 # number of ReadReq miss cycles 580system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1657000 # number of ReadExReq miss cycles 581system.cpu.l2cache.ReadExReq_miss_latency::total 1657000 # number of ReadExReq miss cycles 582system.cpu.l2cache.demand_miss_latency::cpu.inst 10097000 # number of demand (read+write) miss cycles 583system.cpu.l2cache.demand_miss_latency::cpu.data 5070000 # number of demand (read+write) miss cycles 584system.cpu.l2cache.demand_miss_latency::total 15167000 # number of demand (read+write) miss cycles 585system.cpu.l2cache.overall_miss_latency::cpu.inst 10097000 # number of overall miss cycles 586system.cpu.l2cache.overall_miss_latency::cpu.data 5070000 # number of overall miss cycles 587system.cpu.l2cache.overall_miss_latency::total 15167000 # number of overall miss cycles 588system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) 589system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 590system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) 591system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 592system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 593system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 594system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 595system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses 596system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses 597system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 598system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses 599system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942568 # miss rate for ReadReq accesses 600system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses 601system.cpu.l2cache.ReadReq_miss_rate::total 0.907731 # miss rate for ReadReq accesses 602system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 603system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 604system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942568 # miss rate for demand accesses 605system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 606system.cpu.l2cache.demand_miss_rate::total 0.916479 # miss rate for demand accesses 607system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942568 # miss rate for overall accesses 608system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 609system.cpu.l2cache.overall_miss_rate::total 0.916479 # miss rate for overall accesses 610system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36189.964158 # average ReadReq miss latency 611system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40152.941176 # average ReadReq miss latency 612system.cpu.l2cache.ReadReq_avg_miss_latency::total 37115.384615 # average ReadReq miss latency 613system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39452.380952 # average ReadExReq miss latency 614system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39452.380952 # average ReadExReq miss latency 615system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency 616system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency 617system.cpu.l2cache.demand_avg_miss_latency::total 37357.142857 # average overall miss latency 618system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency 619system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency 620system.cpu.l2cache.overall_avg_miss_latency::total 37357.142857 # average overall miss latency 621system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 622system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 623system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 624system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 625system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 626system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 627system.cpu.l2cache.fast_writes 0 # number of fast writes performed 628system.cpu.l2cache.cache_copies 0 # number of cache copies performed 629system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 630system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 631system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 632system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 633system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 634system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 635system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 636system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 637system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 638system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses 639system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 640system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses 641system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 642system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 643system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 644system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses 645system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses 646system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses 647system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses 648system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses 649system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9207000 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036500 # number of ReadReq MSHR miss cycles 651system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12243500 # number of ReadReq MSHR miss cycles 652system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles 654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9207000 # number of demand (read+write) MSHR miss cycles 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4564000 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::total 13771000 # number of demand (read+write) MSHR miss cycles 657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9207000 # number of overall MSHR miss cycles 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses 661system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses 662system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses 663system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 664system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 665system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses 666system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses 667system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses 668system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses 669system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses 670system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses 671system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency 672system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency 673system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency 674system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency 675system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency 678system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency 680system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency 681system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency 682system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 683 684---------- End Simulation Statistics ---------- 685