config.ini revision 8911:4da2ea94319f
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19physmem=system.physmem 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99phase=0 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null 143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port 151mem_side=system.cpu.toL2Bus.slave[1] 152 153[system.cpu.dtb] 154type=ArmTLB 155children=walker 156size=64 157walker=system.cpu.dtb.walker 158 159[system.cpu.dtb.walker] 160type=ArmTableWalker 161max_backoff=100000 162min_backoff=0 163sys=system 164port=system.cpu.toL2Bus.slave[3] 165 166[system.cpu.fuPool] 167type=FUPool 168children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 169FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 170 171[system.cpu.fuPool.FUList0] 172type=FUDesc 173children=opList 174count=6 175opList=system.cpu.fuPool.FUList0.opList 176 177[system.cpu.fuPool.FUList0.opList] 178type=OpDesc 179issueLat=1 180opClass=IntAlu 181opLat=1 182 183[system.cpu.fuPool.FUList1] 184type=FUDesc 185children=opList0 opList1 186count=2 187opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 188 189[system.cpu.fuPool.FUList1.opList0] 190type=OpDesc 191issueLat=1 192opClass=IntMult 193opLat=3 194 195[system.cpu.fuPool.FUList1.opList1] 196type=OpDesc 197issueLat=19 198opClass=IntDiv 199opLat=20 200 201[system.cpu.fuPool.FUList2] 202type=FUDesc 203children=opList0 opList1 opList2 204count=4 205opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 206 207[system.cpu.fuPool.FUList2.opList0] 208type=OpDesc 209issueLat=1 210opClass=FloatAdd 211opLat=2 212 213[system.cpu.fuPool.FUList2.opList1] 214type=OpDesc 215issueLat=1 216opClass=FloatCmp 217opLat=2 218 219[system.cpu.fuPool.FUList2.opList2] 220type=OpDesc 221issueLat=1 222opClass=FloatCvt 223opLat=2 224 225[system.cpu.fuPool.FUList3] 226type=FUDesc 227children=opList0 opList1 opList2 228count=2 229opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 230 231[system.cpu.fuPool.FUList3.opList0] 232type=OpDesc 233issueLat=1 234opClass=FloatMult 235opLat=4 236 237[system.cpu.fuPool.FUList3.opList1] 238type=OpDesc 239issueLat=12 240opClass=FloatDiv 241opLat=12 242 243[system.cpu.fuPool.FUList3.opList2] 244type=OpDesc 245issueLat=24 246opClass=FloatSqrt 247opLat=24 248 249[system.cpu.fuPool.FUList4] 250type=FUDesc 251children=opList 252count=0 253opList=system.cpu.fuPool.FUList4.opList 254 255[system.cpu.fuPool.FUList4.opList] 256type=OpDesc 257issueLat=1 258opClass=MemRead 259opLat=1 260 261[system.cpu.fuPool.FUList5] 262type=FUDesc 263children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 264count=4 265opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 266 267[system.cpu.fuPool.FUList5.opList00] 268type=OpDesc 269issueLat=1 270opClass=SimdAdd 271opLat=1 272 273[system.cpu.fuPool.FUList5.opList01] 274type=OpDesc 275issueLat=1 276opClass=SimdAddAcc 277opLat=1 278 279[system.cpu.fuPool.FUList5.opList02] 280type=OpDesc 281issueLat=1 282opClass=SimdAlu 283opLat=1 284 285[system.cpu.fuPool.FUList5.opList03] 286type=OpDesc 287issueLat=1 288opClass=SimdCmp 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList04] 292type=OpDesc 293issueLat=1 294opClass=SimdCvt 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList05] 298type=OpDesc 299issueLat=1 300opClass=SimdMisc 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList06] 304type=OpDesc 305issueLat=1 306opClass=SimdMult 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList07] 310type=OpDesc 311issueLat=1 312opClass=SimdMultAcc 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList08] 316type=OpDesc 317issueLat=1 318opClass=SimdShift 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList09] 322type=OpDesc 323issueLat=1 324opClass=SimdShiftAcc 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList10] 328type=OpDesc 329issueLat=1 330opClass=SimdSqrt 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList11] 334type=OpDesc 335issueLat=1 336opClass=SimdFloatAdd 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList12] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatAlu 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList13] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatCmp 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList14] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatCvt 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList15] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatDiv 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList16] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatMisc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList17] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMult 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList18] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatMultAcc 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList19] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatSqrt 385opLat=1 386 387[system.cpu.fuPool.FUList6] 388type=FUDesc 389children=opList 390count=0 391opList=system.cpu.fuPool.FUList6.opList 392 393[system.cpu.fuPool.FUList6.opList] 394type=OpDesc 395issueLat=1 396opClass=MemWrite 397opLat=1 398 399[system.cpu.fuPool.FUList7] 400type=FUDesc 401children=opList0 opList1 402count=4 403opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 404 405[system.cpu.fuPool.FUList7.opList0] 406type=OpDesc 407issueLat=1 408opClass=MemRead 409opLat=1 410 411[system.cpu.fuPool.FUList7.opList1] 412type=OpDesc 413issueLat=1 414opClass=MemWrite 415opLat=1 416 417[system.cpu.fuPool.FUList8] 418type=FUDesc 419children=opList 420count=1 421opList=system.cpu.fuPool.FUList8.opList 422 423[system.cpu.fuPool.FUList8.opList] 424type=OpDesc 425issueLat=3 426opClass=IprAccess 427opLat=3 428 429[system.cpu.icache] 430type=BaseCache 431addr_ranges=0:18446744073709551615 432assoc=2 433block_size=64 434forward_snoops=true 435hash_delay=1 436is_top_level=true 437latency=1000 438max_miss_count=0 439mshrs=10 440prefetch_on_access=false 441prefetcher=Null 442prioritizeRequests=false 443repl=Null 444size=131072 445subblock_size=0 446system=system 447tgts_per_mshr=20 448trace_addr=0 449two_queue=false 450write_buffers=8 451cpu_side=system.cpu.icache_port 452mem_side=system.cpu.toL2Bus.slave[0] 453 454[system.cpu.interrupts] 455type=ArmInterrupts 456 457[system.cpu.itb] 458type=ArmTLB 459children=walker 460size=64 461walker=system.cpu.itb.walker 462 463[system.cpu.itb.walker] 464type=ArmTableWalker 465max_backoff=100000 466min_backoff=0 467sys=system 468port=system.cpu.toL2Bus.slave[2] 469 470[system.cpu.l2cache] 471type=BaseCache 472addr_ranges=0:18446744073709551615 473assoc=2 474block_size=64 475forward_snoops=true 476hash_delay=1 477is_top_level=false 478latency=1000 479max_miss_count=0 480mshrs=10 481prefetch_on_access=false 482prefetcher=Null 483prioritizeRequests=false 484repl=Null 485size=2097152 486subblock_size=0 487system=system 488tgts_per_mshr=5 489trace_addr=0 490two_queue=false 491write_buffers=8 492cpu_side=system.cpu.toL2Bus.master[0] 493mem_side=system.membus.slave[1] 494 495[system.cpu.toL2Bus] 496type=Bus 497block_size=64 498bus_id=0 499clock=1000 500header_cycles=1 501use_default_range=false 502width=64 503master=system.cpu.l2cache.cpu_side 504slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 505 506[system.cpu.tracer] 507type=ExeTracer 508 509[system.cpu.workload] 510type=LiveProcess 511cmd=hello 512cwd= 513egid=100 514env= 515errout=cerr 516euid=100 517executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello 518gid=100 519input=cin 520max_stack_size=67108864 521output=cout 522pid=100 523ppid=99 524simpoint=0 525system=system 526uid=100 527 528[system.membus] 529type=Bus 530block_size=64 531bus_id=0 532clock=1000 533header_cycles=1 534use_default_range=false 535width=64 536master=system.physmem.port[0] 537slave=system.system_port system.cpu.l2cache.mem_side 538 539[system.physmem] 540type=PhysicalMemory 541file= 542latency=30000 543latency_var=0 544null=false 545range=0:134217727 546zero=false 547port=system.membus.master[0] 548 549