config.ini revision 11731
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=16 61LSQCheckLoads=true 62LSQDepCheckShift=0 63SQEntries=16 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=2 79decodeWidth=3 80default_p_state=UNDEFINED 81dispatchWidth=6 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dstage2_mmu=system.cpu.dstage2_mmu 86dtb=system.cpu.dtb 87eventq_index=0 88fetchBufferSize=16 89fetchQueueSize=32 90fetchToDecodeDelay=3 91fetchTrapLatency=1 92fetchWidth=3 93forwardComSize=5 94fuPool=system.cpu.fuPool 95function_trace=false 96function_trace_start=0 97iewToCommitDelay=1 98iewToDecodeDelay=1 99iewToFetchDelay=1 100iewToRenameDelay=1 101interrupts=system.cpu.interrupts 102isa=system.cpu.isa 103issueToExecuteDelay=1 104issueWidth=8 105istage2_mmu=system.cpu.istage2_mmu 106itb=system.cpu.itb 107max_insts_all_threads=0 108max_insts_any_thread=0 109max_loads_all_threads=0 110max_loads_any_thread=0 111needsTSO=false 112numIQEntries=32 113numPhysCCRegs=640 114numPhysFloatRegs=192 115numPhysIntRegs=128 116numROBEntries=40 117numRobs=1 118numThreads=1 119p_state_clk_gate_bins=20 120p_state_clk_gate_max=1000000000000 121p_state_clk_gate_min=1000 122power_model=Null 123profile=0 124progress_interval=0 125renameToDecodeDelay=1 126renameToFetchDelay=1 127renameToIEWDelay=1 128renameToROBDelay=1 129renameWidth=3 130simpoint_start_insts= 131smtCommitPolicy=RoundRobin 132smtFetchPolicy=SingleThread 133smtIQPolicy=Partitioned 134smtIQThreshold=100 135smtLSQPolicy=Partitioned 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false 144system=system 145tracer=system.cpu.tracer 146trapLatency=13 147wbWidth=8 148workload=system.cpu.workload 149dcache_port=system.cpu.dcache.cpu_side 150icache_port=system.cpu.icache.cpu_side 151 152[system.cpu.branchPred] 153type=BiModeBP 154BTBEntries=2048 155BTBTagSize=18 156RASSize=16 157choiceCtrBits=2 158choicePredictorSize=8192 159eventq_index=0 160globalCtrBits=2 161globalPredictorSize=8192 162indirectHashGHR=true 163indirectHashTargets=true 164indirectPathLength=3 165indirectSets=256 166indirectTagSize=16 167indirectWays=2 168instShiftAmt=2 169numThreads=1 170useIndirect=true 171 172[system.cpu.dcache] 173type=Cache 174children=tags 175addr_ranges=0:18446744073709551615:0:0:0:0 176assoc=2 177clk_domain=system.cpu_clk_domain 178clusivity=mostly_incl 179data_latency=2 180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0 183is_read_only=false 184max_miss_count=0 185mshrs=6 186p_state_clk_gate_bins=20 187p_state_clk_gate_max=1000000000000 188p_state_clk_gate_min=1000 189power_model=Null 190prefetch_on_access=false 191prefetcher=Null 192response_latency=2 193sequential_access=false 194size=32768 195system=system 196tag_latency=2 197tags=system.cpu.dcache.tags 198tgts_per_mshr=8 199write_buffers=16 200writeback_clean=true 201cpu_side=system.cpu.dcache_port 202mem_side=system.cpu.toL2Bus.slave[1] 203 204[system.cpu.dcache.tags] 205type=LRU 206assoc=2 207block_size=64 208clk_domain=system.cpu_clk_domain 209data_latency=2 210default_p_state=UNDEFINED 211eventq_index=0 212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null 216sequential_access=false 217size=32768 218tag_latency=2 219 220[system.cpu.dstage2_mmu] 221type=ArmStage2MMU 222children=stage2_tlb 223eventq_index=0 224stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 225sys=system 226tlb=system.cpu.dtb 227 228[system.cpu.dstage2_mmu.stage2_tlb] 229type=ArmTLB 230children=walker 231eventq_index=0 232is_stage2=true 233size=32 234walker=system.cpu.dstage2_mmu.stage2_tlb.walker 235 236[system.cpu.dstage2_mmu.stage2_tlb.walker] 237type=ArmTableWalker 238clk_domain=system.cpu_clk_domain 239default_p_state=UNDEFINED 240eventq_index=0 241is_stage2=true 242num_squash_per_cycle=2 243p_state_clk_gate_bins=20 244p_state_clk_gate_max=1000000000000 245p_state_clk_gate_min=1000 246power_model=Null 247sys=system 248 249[system.cpu.dtb] 250type=ArmTLB 251children=walker 252eventq_index=0 253is_stage2=false 254size=64 255walker=system.cpu.dtb.walker 256 257[system.cpu.dtb.walker] 258type=ArmTableWalker 259clk_domain=system.cpu_clk_domain 260default_p_state=UNDEFINED 261eventq_index=0 262is_stage2=false 263num_squash_per_cycle=2 264p_state_clk_gate_bins=20 265p_state_clk_gate_max=1000000000000 266p_state_clk_gate_min=1000 267power_model=Null 268sys=system 269port=system.cpu.toL2Bus.slave[3] 270 271[system.cpu.fuPool] 272type=FUPool 273children=FUList0 FUList1 FUList2 FUList3 FUList4 274FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 275eventq_index=0 276 277[system.cpu.fuPool.FUList0] 278type=FUDesc 279children=opList 280count=2 281eventq_index=0 282opList=system.cpu.fuPool.FUList0.opList 283 284[system.cpu.fuPool.FUList0.opList] 285type=OpDesc 286eventq_index=0 287opClass=IntAlu 288opLat=1 289pipelined=true 290 291[system.cpu.fuPool.FUList1] 292type=FUDesc 293children=opList0 opList1 opList2 294count=1 295eventq_index=0 296opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 297 298[system.cpu.fuPool.FUList1.opList0] 299type=OpDesc 300eventq_index=0 301opClass=IntMult 302opLat=3 303pipelined=true 304 305[system.cpu.fuPool.FUList1.opList1] 306type=OpDesc 307eventq_index=0 308opClass=IntDiv 309opLat=12 310pipelined=false 311 312[system.cpu.fuPool.FUList1.opList2] 313type=OpDesc 314eventq_index=0 315opClass=IprAccess 316opLat=3 317pipelined=true 318 319[system.cpu.fuPool.FUList2] 320type=FUDesc 321children=opList0 opList1 322count=1 323eventq_index=0 324opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 325 326[system.cpu.fuPool.FUList2.opList0] 327type=OpDesc 328eventq_index=0 329opClass=MemRead 330opLat=2 331pipelined=true 332 333[system.cpu.fuPool.FUList2.opList1] 334type=OpDesc 335eventq_index=0 336opClass=FloatMemRead 337opLat=2 338pipelined=true 339 340[system.cpu.fuPool.FUList3] 341type=FUDesc 342children=opList0 opList1 343count=1 344eventq_index=0 345opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 346 347[system.cpu.fuPool.FUList3.opList0] 348type=OpDesc 349eventq_index=0 350opClass=MemWrite 351opLat=2 352pipelined=true 353 354[system.cpu.fuPool.FUList3.opList1] 355type=OpDesc 356eventq_index=0 357opClass=FloatMemWrite 358opLat=2 359pipelined=true 360 361[system.cpu.fuPool.FUList4] 362type=FUDesc 363children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 364count=2 365eventq_index=0 366opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 367 368[system.cpu.fuPool.FUList4.opList00] 369type=OpDesc 370eventq_index=0 371opClass=SimdAdd 372opLat=4 373pipelined=true 374 375[system.cpu.fuPool.FUList4.opList01] 376type=OpDesc 377eventq_index=0 378opClass=SimdAddAcc 379opLat=4 380pipelined=true 381 382[system.cpu.fuPool.FUList4.opList02] 383type=OpDesc 384eventq_index=0 385opClass=SimdAlu 386opLat=4 387pipelined=true 388 389[system.cpu.fuPool.FUList4.opList03] 390type=OpDesc 391eventq_index=0 392opClass=SimdCmp 393opLat=4 394pipelined=true 395 396[system.cpu.fuPool.FUList4.opList04] 397type=OpDesc 398eventq_index=0 399opClass=SimdCvt 400opLat=3 401pipelined=true 402 403[system.cpu.fuPool.FUList4.opList05] 404type=OpDesc 405eventq_index=0 406opClass=SimdMisc 407opLat=3 408pipelined=true 409 410[system.cpu.fuPool.FUList4.opList06] 411type=OpDesc 412eventq_index=0 413opClass=SimdMult 414opLat=5 415pipelined=true 416 417[system.cpu.fuPool.FUList4.opList07] 418type=OpDesc 419eventq_index=0 420opClass=SimdMultAcc 421opLat=5 422pipelined=true 423 424[system.cpu.fuPool.FUList4.opList08] 425type=OpDesc 426eventq_index=0 427opClass=SimdShift 428opLat=3 429pipelined=true 430 431[system.cpu.fuPool.FUList4.opList09] 432type=OpDesc 433eventq_index=0 434opClass=SimdShiftAcc 435opLat=3 436pipelined=true 437 438[system.cpu.fuPool.FUList4.opList10] 439type=OpDesc 440eventq_index=0 441opClass=SimdSqrt 442opLat=9 443pipelined=true 444 445[system.cpu.fuPool.FUList4.opList11] 446type=OpDesc 447eventq_index=0 448opClass=SimdFloatAdd 449opLat=5 450pipelined=true 451 452[system.cpu.fuPool.FUList4.opList12] 453type=OpDesc 454eventq_index=0 455opClass=SimdFloatAlu 456opLat=5 457pipelined=true 458 459[system.cpu.fuPool.FUList4.opList13] 460type=OpDesc 461eventq_index=0 462opClass=SimdFloatCmp 463opLat=3 464pipelined=true 465 466[system.cpu.fuPool.FUList4.opList14] 467type=OpDesc 468eventq_index=0 469opClass=SimdFloatCvt 470opLat=3 471pipelined=true 472 473[system.cpu.fuPool.FUList4.opList15] 474type=OpDesc 475eventq_index=0 476opClass=SimdFloatDiv 477opLat=3 478pipelined=true 479 480[system.cpu.fuPool.FUList4.opList16] 481type=OpDesc 482eventq_index=0 483opClass=SimdFloatMisc 484opLat=3 485pipelined=true 486 487[system.cpu.fuPool.FUList4.opList17] 488type=OpDesc 489eventq_index=0 490opClass=SimdFloatMult 491opLat=3 492pipelined=true 493 494[system.cpu.fuPool.FUList4.opList18] 495type=OpDesc 496eventq_index=0 497opClass=SimdFloatMultAcc 498opLat=5 499pipelined=true 500 501[system.cpu.fuPool.FUList4.opList19] 502type=OpDesc 503eventq_index=0 504opClass=SimdFloatSqrt 505opLat=9 506pipelined=true 507 508[system.cpu.fuPool.FUList4.opList20] 509type=OpDesc 510eventq_index=0 511opClass=FloatAdd 512opLat=5 513pipelined=true 514 515[system.cpu.fuPool.FUList4.opList21] 516type=OpDesc 517eventq_index=0 518opClass=FloatCmp 519opLat=5 520pipelined=true 521 522[system.cpu.fuPool.FUList4.opList22] 523type=OpDesc 524eventq_index=0 525opClass=FloatCvt 526opLat=5 527pipelined=true 528 529[system.cpu.fuPool.FUList4.opList23] 530type=OpDesc 531eventq_index=0 532opClass=FloatDiv 533opLat=9 534pipelined=false 535 536[system.cpu.fuPool.FUList4.opList24] 537type=OpDesc 538eventq_index=0 539opClass=FloatSqrt 540opLat=33 541pipelined=false 542 543[system.cpu.fuPool.FUList4.opList25] 544type=OpDesc 545eventq_index=0 546opClass=FloatMult 547opLat=4 548pipelined=true 549 550[system.cpu.fuPool.FUList4.opList26] 551type=OpDesc 552eventq_index=0 553opClass=FloatMultAcc 554opLat=5 555pipelined=true 556 557[system.cpu.fuPool.FUList4.opList27] 558type=OpDesc 559eventq_index=0 560opClass=FloatMisc 561opLat=3 562pipelined=true 563 564[system.cpu.icache] 565type=Cache 566children=tags 567addr_ranges=0:18446744073709551615:0:0:0:0 568assoc=2 569clk_domain=system.cpu_clk_domain 570clusivity=mostly_incl 571data_latency=1 572default_p_state=UNDEFINED 573demand_mshr_reserve=1 574eventq_index=0 575is_read_only=true 576max_miss_count=0 577mshrs=2 578p_state_clk_gate_bins=20 579p_state_clk_gate_max=1000000000000 580p_state_clk_gate_min=1000 581power_model=Null 582prefetch_on_access=false 583prefetcher=Null 584response_latency=1 585sequential_access=false 586size=32768 587system=system 588tag_latency=1 589tags=system.cpu.icache.tags 590tgts_per_mshr=8 591write_buffers=8 592writeback_clean=true 593cpu_side=system.cpu.icache_port 594mem_side=system.cpu.toL2Bus.slave[0] 595 596[system.cpu.icache.tags] 597type=LRU 598assoc=2 599block_size=64 600clk_domain=system.cpu_clk_domain 601data_latency=1 602default_p_state=UNDEFINED 603eventq_index=0 604p_state_clk_gate_bins=20 605p_state_clk_gate_max=1000000000000 606p_state_clk_gate_min=1000 607power_model=Null 608sequential_access=false 609size=32768 610tag_latency=1 611 612[system.cpu.interrupts] 613type=ArmInterrupts 614eventq_index=0 615 616[system.cpu.isa] 617type=ArmISA 618decoderFlavour=Generic 619eventq_index=0 620fpsid=1090793632 621id_aa64afr0_el1=0 622id_aa64afr1_el1=0 623id_aa64dfr0_el1=1052678 624id_aa64dfr1_el1=0 625id_aa64isar0_el1=0 626id_aa64isar1_el1=0 627id_aa64mmfr0_el1=15728642 628id_aa64mmfr1_el1=0 629id_aa64pfr0_el1=34 630id_aa64pfr1_el1=0 631id_isar0=34607377 632id_isar1=34677009 633id_isar2=555950401 634id_isar3=17899825 635id_isar4=268501314 636id_isar5=0 637id_mmfr0=270536963 638id_mmfr1=0 639id_mmfr2=19070976 640id_mmfr3=34611729 641id_pfr0=49 642id_pfr1=4113 643midr=1091551472 644pmu=Null 645system=system 646 647[system.cpu.istage2_mmu] 648type=ArmStage2MMU 649children=stage2_tlb 650eventq_index=0 651stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 652sys=system 653tlb=system.cpu.itb 654 655[system.cpu.istage2_mmu.stage2_tlb] 656type=ArmTLB 657children=walker 658eventq_index=0 659is_stage2=true 660size=32 661walker=system.cpu.istage2_mmu.stage2_tlb.walker 662 663[system.cpu.istage2_mmu.stage2_tlb.walker] 664type=ArmTableWalker 665clk_domain=system.cpu_clk_domain 666default_p_state=UNDEFINED 667eventq_index=0 668is_stage2=true 669num_squash_per_cycle=2 670p_state_clk_gate_bins=20 671p_state_clk_gate_max=1000000000000 672p_state_clk_gate_min=1000 673power_model=Null 674sys=system 675 676[system.cpu.itb] 677type=ArmTLB 678children=walker 679eventq_index=0 680is_stage2=false 681size=64 682walker=system.cpu.itb.walker 683 684[system.cpu.itb.walker] 685type=ArmTableWalker 686clk_domain=system.cpu_clk_domain 687default_p_state=UNDEFINED 688eventq_index=0 689is_stage2=false 690num_squash_per_cycle=2 691p_state_clk_gate_bins=20 692p_state_clk_gate_max=1000000000000 693p_state_clk_gate_min=1000 694power_model=Null 695sys=system 696port=system.cpu.toL2Bus.slave[2] 697 698[system.cpu.l2cache] 699type=Cache 700children=prefetcher tags 701addr_ranges=0:18446744073709551615:0:0:0:0 702assoc=16 703clk_domain=system.cpu_clk_domain 704clusivity=mostly_excl 705data_latency=12 706default_p_state=UNDEFINED 707demand_mshr_reserve=1 708eventq_index=0 709is_read_only=false 710max_miss_count=0 711mshrs=16 712p_state_clk_gate_bins=20 713p_state_clk_gate_max=1000000000000 714p_state_clk_gate_min=1000 715power_model=Null 716prefetch_on_access=true 717prefetcher=system.cpu.l2cache.prefetcher 718response_latency=12 719sequential_access=false 720size=1048576 721system=system 722tag_latency=12 723tags=system.cpu.l2cache.tags 724tgts_per_mshr=8 725write_buffers=8 726writeback_clean=false 727cpu_side=system.cpu.toL2Bus.master[0] 728mem_side=system.membus.slave[1] 729 730[system.cpu.l2cache.prefetcher] 731type=StridePrefetcher 732cache_snoop=false 733clk_domain=system.cpu_clk_domain 734default_p_state=UNDEFINED 735degree=8 736eventq_index=0 737latency=1 738max_conf=7 739min_conf=0 740on_data=true 741on_inst=true 742on_miss=false 743on_read=true 744on_write=true 745p_state_clk_gate_bins=20 746p_state_clk_gate_max=1000000000000 747p_state_clk_gate_min=1000 748power_model=Null 749queue_filter=true 750queue_size=32 751queue_squash=true 752start_conf=4 753sys=system 754table_assoc=4 755table_sets=16 756tag_prefetch=true 757thresh_conf=4 758use_master_id=true 759 760[system.cpu.l2cache.tags] 761type=RandomRepl 762assoc=16 763block_size=64 764clk_domain=system.cpu_clk_domain 765data_latency=12 766default_p_state=UNDEFINED 767eventq_index=0 768p_state_clk_gate_bins=20 769p_state_clk_gate_max=1000000000000 770p_state_clk_gate_min=1000 771power_model=Null 772sequential_access=false 773size=1048576 774tag_latency=12 775 776[system.cpu.toL2Bus] 777type=CoherentXBar 778children=snoop_filter 779clk_domain=system.cpu_clk_domain 780default_p_state=UNDEFINED 781eventq_index=0 782forward_latency=0 783frontend_latency=1 784p_state_clk_gate_bins=20 785p_state_clk_gate_max=1000000000000 786p_state_clk_gate_min=1000 787point_of_coherency=false 788power_model=Null 789response_latency=1 790snoop_filter=system.cpu.toL2Bus.snoop_filter 791snoop_response_latency=1 792system=system 793use_default_range=false 794width=32 795master=system.cpu.l2cache.cpu_side 796slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 797 798[system.cpu.toL2Bus.snoop_filter] 799type=SnoopFilter 800eventq_index=0 801lookup_latency=0 802max_capacity=8388608 803system=system 804 805[system.cpu.tracer] 806type=ExeTracer 807eventq_index=0 808 809[system.cpu.workload] 810type=LiveProcess 811cmd=hello 812cwd= 813drivers= 814egid=100 815env= 816errout=cerr 817euid=100 818eventq_index=0 819executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 820gid=100 821input=cin 822kvmInSE=false 823max_stack_size=67108864 824output=cout 825pid=100 826ppid=99 827simpoint=0 828system=system 829uid=100 830useArchPT=false 831 832[system.cpu_clk_domain] 833type=SrcClockDomain 834clock=500 835domain_id=-1 836eventq_index=0 837init_perf_level=0 838voltage_domain=system.voltage_domain 839 840[system.dvfs_handler] 841type=DVFSHandler 842domains= 843enable=false 844eventq_index=0 845sys_clk_domain=system.clk_domain 846transition_latency=100000000 847 848[system.membus] 849type=CoherentXBar 850children=snoop_filter 851clk_domain=system.clk_domain 852default_p_state=UNDEFINED 853eventq_index=0 854forward_latency=4 855frontend_latency=3 856p_state_clk_gate_bins=20 857p_state_clk_gate_max=1000000000000 858p_state_clk_gate_min=1000 859point_of_coherency=true 860power_model=Null 861response_latency=2 862snoop_filter=system.membus.snoop_filter 863snoop_response_latency=4 864system=system 865use_default_range=false 866width=16 867master=system.physmem.port 868slave=system.system_port system.cpu.l2cache.mem_side 869 870[system.membus.snoop_filter] 871type=SnoopFilter 872eventq_index=0 873lookup_latency=1 874max_capacity=8388608 875system=system 876 877[system.physmem] 878type=DRAMCtrl 879IDD0=0.055000 880IDD02=0.000000 881IDD2N=0.032000 882IDD2N2=0.000000 883IDD2P0=0.000000 884IDD2P02=0.000000 885IDD2P1=0.032000 886IDD2P12=0.000000 887IDD3N=0.038000 888IDD3N2=0.000000 889IDD3P0=0.000000 890IDD3P02=0.000000 891IDD3P1=0.038000 892IDD3P12=0.000000 893IDD4R=0.157000 894IDD4R2=0.000000 895IDD4W=0.125000 896IDD4W2=0.000000 897IDD5=0.235000 898IDD52=0.000000 899IDD6=0.020000 900IDD62=0.000000 901VDD=1.500000 902VDD2=0.000000 903activation_limit=4 904addr_mapping=RoRaBaCoCh 905bank_groups_per_rank=0 906banks_per_rank=8 907burst_length=8 908channels=1 909clk_domain=system.clk_domain 910conf_table_reported=true 911default_p_state=UNDEFINED 912device_bus_width=8 913device_rowbuffer_size=1024 914device_size=536870912 915devices_per_rank=8 916dll=true 917eventq_index=0 918in_addr_map=true 919kvm_map=true 920max_accesses_per_row=16 921mem_sched_policy=frfcfs 922min_writes_per_switch=16 923null=false 924p_state_clk_gate_bins=20 925p_state_clk_gate_max=1000000000000 926p_state_clk_gate_min=1000 927page_policy=open_adaptive 928power_model=Null 929range=0:134217727:0:0:0:0 930ranks_per_channel=2 931read_buffer_size=32 932static_backend_latency=10000 933static_frontend_latency=10000 934tBURST=5000 935tCCD_L=0 936tCK=1250 937tCL=13750 938tCS=2500 939tRAS=35000 940tRCD=13750 941tREFI=7800000 942tRFC=260000 943tRP=13750 944tRRD=6000 945tRRD_L=0 946tRTP=7500 947tRTW=2500 948tWR=15000 949tWTR=7500 950tXAW=30000 951tXP=6000 952tXPDLL=0 953tXS=270000 954tXSDLL=0 955write_buffer_size=64 956write_high_thresh_perc=85 957write_low_thresh_perc=50 958port=system.membus.master[0] 959 960[system.voltage_domain] 961type=VoltageDomain 962eventq_index=0 963voltage=1.000000 964 965