config.ini revision 11312
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=DerivO3CPU 51children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 52LFSTSize=1024 53LQEntries=16 54LSQCheckLoads=true 55LSQDepCheckShift=0 56SQEntries=16 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu.branchPred 61cachePorts=200 62checker=Null 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=2 72decodeWidth=3 73dispatchWidth=6 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dstage2_mmu=system.cpu.dstage2_mmu 78dtb=system.cpu.dtb 79eventq_index=0 80fetchBufferSize=16 81fetchQueueSize=32 82fetchToDecodeDelay=3 83fetchTrapLatency=1 84fetchWidth=3 85forwardComSize=5 86fuPool=system.cpu.fuPool 87function_trace=false 88function_trace_start=0 89iewToCommitDelay=1 90iewToDecodeDelay=1 91iewToFetchDelay=1 92iewToRenameDelay=1 93interrupts=system.cpu.interrupts 94isa=system.cpu.isa 95issueToExecuteDelay=1 96issueWidth=8 97istage2_mmu=system.cpu.istage2_mmu 98itb=system.cpu.itb 99max_insts_all_threads=0 100max_insts_any_thread=0 101max_loads_all_threads=0 102max_loads_any_thread=0 103needsTSO=false 104numIQEntries=32 105numPhysCCRegs=640 106numPhysFloatRegs=192 107numPhysIntRegs=128 108numROBEntries=40 109numRobs=1 110numThreads=1 111profile=0 112progress_interval=0 113renameToDecodeDelay=1 114renameToFetchDelay=1 115renameToIEWDelay=1 116renameToROBDelay=1 117renameWidth=3 118simpoint_start_insts= 119smtCommitPolicy=RoundRobin 120smtFetchPolicy=SingleThread 121smtIQPolicy=Partitioned 122smtIQThreshold=100 123smtLSQPolicy=Partitioned 124smtLSQThreshold=100 125smtNumFetchingThreads=1 126smtROBPolicy=Partitioned 127smtROBThreshold=100 128socket_id=0 129squashWidth=8 130store_set_clear_period=250000 131switched_out=false 132system=system 133tracer=system.cpu.tracer 134trapLatency=13 135wbWidth=8 136workload=system.cpu.workload 137dcache_port=system.cpu.dcache.cpu_side 138icache_port=system.cpu.icache.cpu_side 139 140[system.cpu.branchPred] 141type=BiModeBP 142BTBEntries=2048 143BTBTagSize=18 144RASSize=16 145choiceCtrBits=2 146choicePredictorSize=8192 147eventq_index=0 148globalCtrBits=2 149globalPredictorSize=8192 150instShiftAmt=2 151numThreads=1 152 153[system.cpu.dcache] 154type=Cache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain 159clusivity=mostly_incl 160demand_mshr_reserve=1 161eventq_index=0 162forward_snoops=true 163hit_latency=2 164is_read_only=false 165max_miss_count=0 166mshrs=6 167prefetch_on_access=false 168prefetcher=Null 169response_latency=2 170sequential_access=false 171size=32768 172system=system 173tags=system.cpu.dcache.tags 174tgts_per_mshr=8 175write_buffers=16 176writeback_clean=true 177cpu_side=system.cpu.dcache_port 178mem_side=system.cpu.toL2Bus.slave[1] 179 180[system.cpu.dcache.tags] 181type=LRU 182assoc=2 183block_size=64 184clk_domain=system.cpu_clk_domain 185eventq_index=0 186hit_latency=2 187sequential_access=false 188size=32768 189 190[system.cpu.dstage2_mmu] 191type=ArmStage2MMU 192children=stage2_tlb 193eventq_index=0 194stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 195sys=system 196tlb=system.cpu.dtb 197 198[system.cpu.dstage2_mmu.stage2_tlb] 199type=ArmTLB 200children=walker 201eventq_index=0 202is_stage2=true 203size=32 204walker=system.cpu.dstage2_mmu.stage2_tlb.walker 205 206[system.cpu.dstage2_mmu.stage2_tlb.walker] 207type=ArmTableWalker 208clk_domain=system.cpu_clk_domain 209eventq_index=0 210is_stage2=true 211num_squash_per_cycle=2 212sys=system 213 214[system.cpu.dtb] 215type=ArmTLB 216children=walker 217eventq_index=0 218is_stage2=false 219size=64 220walker=system.cpu.dtb.walker 221 222[system.cpu.dtb.walker] 223type=ArmTableWalker 224clk_domain=system.cpu_clk_domain 225eventq_index=0 226is_stage2=false 227num_squash_per_cycle=2 228sys=system 229port=system.cpu.toL2Bus.slave[3] 230 231[system.cpu.fuPool] 232type=FUPool 233children=FUList0 FUList1 FUList2 FUList3 FUList4 234FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 235eventq_index=0 236 237[system.cpu.fuPool.FUList0] 238type=FUDesc 239children=opList 240count=2 241eventq_index=0 242opList=system.cpu.fuPool.FUList0.opList 243 244[system.cpu.fuPool.FUList0.opList] 245type=OpDesc 246eventq_index=0 247opClass=IntAlu 248opLat=1 249pipelined=true 250 251[system.cpu.fuPool.FUList1] 252type=FUDesc 253children=opList0 opList1 opList2 254count=1 255eventq_index=0 256opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 257 258[system.cpu.fuPool.FUList1.opList0] 259type=OpDesc 260eventq_index=0 261opClass=IntMult 262opLat=3 263pipelined=true 264 265[system.cpu.fuPool.FUList1.opList1] 266type=OpDesc 267eventq_index=0 268opClass=IntDiv 269opLat=12 270pipelined=false 271 272[system.cpu.fuPool.FUList1.opList2] 273type=OpDesc 274eventq_index=0 275opClass=IprAccess 276opLat=3 277pipelined=true 278 279[system.cpu.fuPool.FUList2] 280type=FUDesc 281children=opList 282count=1 283eventq_index=0 284opList=system.cpu.fuPool.FUList2.opList 285 286[system.cpu.fuPool.FUList2.opList] 287type=OpDesc 288eventq_index=0 289opClass=MemRead 290opLat=2 291pipelined=true 292 293[system.cpu.fuPool.FUList3] 294type=FUDesc 295children=opList 296count=1 297eventq_index=0 298opList=system.cpu.fuPool.FUList3.opList 299 300[system.cpu.fuPool.FUList3.opList] 301type=OpDesc 302eventq_index=0 303opClass=MemWrite 304opLat=2 305pipelined=true 306 307[system.cpu.fuPool.FUList4] 308type=FUDesc 309children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 310count=2 311eventq_index=0 312opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 313 314[system.cpu.fuPool.FUList4.opList00] 315type=OpDesc 316eventq_index=0 317opClass=SimdAdd 318opLat=4 319pipelined=true 320 321[system.cpu.fuPool.FUList4.opList01] 322type=OpDesc 323eventq_index=0 324opClass=SimdAddAcc 325opLat=4 326pipelined=true 327 328[system.cpu.fuPool.FUList4.opList02] 329type=OpDesc 330eventq_index=0 331opClass=SimdAlu 332opLat=4 333pipelined=true 334 335[system.cpu.fuPool.FUList4.opList03] 336type=OpDesc 337eventq_index=0 338opClass=SimdCmp 339opLat=4 340pipelined=true 341 342[system.cpu.fuPool.FUList4.opList04] 343type=OpDesc 344eventq_index=0 345opClass=SimdCvt 346opLat=3 347pipelined=true 348 349[system.cpu.fuPool.FUList4.opList05] 350type=OpDesc 351eventq_index=0 352opClass=SimdMisc 353opLat=3 354pipelined=true 355 356[system.cpu.fuPool.FUList4.opList06] 357type=OpDesc 358eventq_index=0 359opClass=SimdMult 360opLat=5 361pipelined=true 362 363[system.cpu.fuPool.FUList4.opList07] 364type=OpDesc 365eventq_index=0 366opClass=SimdMultAcc 367opLat=5 368pipelined=true 369 370[system.cpu.fuPool.FUList4.opList08] 371type=OpDesc 372eventq_index=0 373opClass=SimdShift 374opLat=3 375pipelined=true 376 377[system.cpu.fuPool.FUList4.opList09] 378type=OpDesc 379eventq_index=0 380opClass=SimdShiftAcc 381opLat=3 382pipelined=true 383 384[system.cpu.fuPool.FUList4.opList10] 385type=OpDesc 386eventq_index=0 387opClass=SimdSqrt 388opLat=9 389pipelined=true 390 391[system.cpu.fuPool.FUList4.opList11] 392type=OpDesc 393eventq_index=0 394opClass=SimdFloatAdd 395opLat=5 396pipelined=true 397 398[system.cpu.fuPool.FUList4.opList12] 399type=OpDesc 400eventq_index=0 401opClass=SimdFloatAlu 402opLat=5 403pipelined=true 404 405[system.cpu.fuPool.FUList4.opList13] 406type=OpDesc 407eventq_index=0 408opClass=SimdFloatCmp 409opLat=3 410pipelined=true 411 412[system.cpu.fuPool.FUList4.opList14] 413type=OpDesc 414eventq_index=0 415opClass=SimdFloatCvt 416opLat=3 417pipelined=true 418 419[system.cpu.fuPool.FUList4.opList15] 420type=OpDesc 421eventq_index=0 422opClass=SimdFloatDiv 423opLat=3 424pipelined=true 425 426[system.cpu.fuPool.FUList4.opList16] 427type=OpDesc 428eventq_index=0 429opClass=SimdFloatMisc 430opLat=3 431pipelined=true 432 433[system.cpu.fuPool.FUList4.opList17] 434type=OpDesc 435eventq_index=0 436opClass=SimdFloatMult 437opLat=3 438pipelined=true 439 440[system.cpu.fuPool.FUList4.opList18] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatMultAcc 444opLat=1 445pipelined=true 446 447[system.cpu.fuPool.FUList4.opList19] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatSqrt 451opLat=9 452pipelined=true 453 454[system.cpu.fuPool.FUList4.opList20] 455type=OpDesc 456eventq_index=0 457opClass=FloatAdd 458opLat=5 459pipelined=true 460 461[system.cpu.fuPool.FUList4.opList21] 462type=OpDesc 463eventq_index=0 464opClass=FloatCmp 465opLat=5 466pipelined=true 467 468[system.cpu.fuPool.FUList4.opList22] 469type=OpDesc 470eventq_index=0 471opClass=FloatCvt 472opLat=5 473pipelined=true 474 475[system.cpu.fuPool.FUList4.opList23] 476type=OpDesc 477eventq_index=0 478opClass=FloatDiv 479opLat=9 480pipelined=false 481 482[system.cpu.fuPool.FUList4.opList24] 483type=OpDesc 484eventq_index=0 485opClass=FloatSqrt 486opLat=33 487pipelined=false 488 489[system.cpu.fuPool.FUList4.opList25] 490type=OpDesc 491eventq_index=0 492opClass=FloatMult 493opLat=4 494pipelined=true 495 496[system.cpu.icache] 497type=Cache 498children=tags 499addr_ranges=0:18446744073709551615 500assoc=2 501clk_domain=system.cpu_clk_domain 502clusivity=mostly_incl 503demand_mshr_reserve=1 504eventq_index=0 505forward_snoops=false 506hit_latency=1 507is_read_only=true 508max_miss_count=0 509mshrs=2 510prefetch_on_access=false 511prefetcher=Null 512response_latency=1 513sequential_access=false 514size=32768 515system=system 516tags=system.cpu.icache.tags 517tgts_per_mshr=8 518write_buffers=8 519writeback_clean=true 520cpu_side=system.cpu.icache_port 521mem_side=system.cpu.toL2Bus.slave[0] 522 523[system.cpu.icache.tags] 524type=LRU 525assoc=2 526block_size=64 527clk_domain=system.cpu_clk_domain 528eventq_index=0 529hit_latency=1 530sequential_access=false 531size=32768 532 533[system.cpu.interrupts] 534type=ArmInterrupts 535eventq_index=0 536 537[system.cpu.isa] 538type=ArmISA 539decoderFlavour=Generic 540eventq_index=0 541fpsid=1090793632 542id_aa64afr0_el1=0 543id_aa64afr1_el1=0 544id_aa64dfr0_el1=1052678 545id_aa64dfr1_el1=0 546id_aa64isar0_el1=0 547id_aa64isar1_el1=0 548id_aa64mmfr0_el1=15728642 549id_aa64mmfr1_el1=0 550id_aa64pfr0_el1=17 551id_aa64pfr1_el1=0 552id_isar0=34607377 553id_isar1=34677009 554id_isar2=555950401 555id_isar3=17899825 556id_isar4=268501314 557id_isar5=0 558id_mmfr0=270536963 559id_mmfr1=0 560id_mmfr2=19070976 561id_mmfr3=34611729 562id_pfr0=49 563id_pfr1=4113 564midr=1091551472 565pmu=Null 566system=system 567 568[system.cpu.istage2_mmu] 569type=ArmStage2MMU 570children=stage2_tlb 571eventq_index=0 572stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 573sys=system 574tlb=system.cpu.itb 575 576[system.cpu.istage2_mmu.stage2_tlb] 577type=ArmTLB 578children=walker 579eventq_index=0 580is_stage2=true 581size=32 582walker=system.cpu.istage2_mmu.stage2_tlb.walker 583 584[system.cpu.istage2_mmu.stage2_tlb.walker] 585type=ArmTableWalker 586clk_domain=system.cpu_clk_domain 587eventq_index=0 588is_stage2=true 589num_squash_per_cycle=2 590sys=system 591 592[system.cpu.itb] 593type=ArmTLB 594children=walker 595eventq_index=0 596is_stage2=false 597size=64 598walker=system.cpu.itb.walker 599 600[system.cpu.itb.walker] 601type=ArmTableWalker 602clk_domain=system.cpu_clk_domain 603eventq_index=0 604is_stage2=false 605num_squash_per_cycle=2 606sys=system 607port=system.cpu.toL2Bus.slave[2] 608 609[system.cpu.l2cache] 610type=Cache 611children=prefetcher tags 612addr_ranges=0:18446744073709551615 613assoc=16 614clk_domain=system.cpu_clk_domain 615clusivity=mostly_excl 616demand_mshr_reserve=1 617eventq_index=0 618forward_snoops=true 619hit_latency=12 620is_read_only=false 621max_miss_count=0 622mshrs=16 623prefetch_on_access=true 624prefetcher=system.cpu.l2cache.prefetcher 625response_latency=12 626sequential_access=false 627size=1048576 628system=system 629tags=system.cpu.l2cache.tags 630tgts_per_mshr=8 631write_buffers=8 632writeback_clean=false 633cpu_side=system.cpu.toL2Bus.master[0] 634mem_side=system.membus.slave[1] 635 636[system.cpu.l2cache.prefetcher] 637type=StridePrefetcher 638cache_snoop=false 639clk_domain=system.cpu_clk_domain 640degree=8 641eventq_index=0 642latency=1 643max_conf=7 644min_conf=0 645on_data=true 646on_inst=true 647on_miss=false 648on_read=true 649on_write=true 650queue_filter=true 651queue_size=32 652queue_squash=true 653start_conf=4 654sys=system 655table_assoc=4 656table_sets=16 657tag_prefetch=true 658thresh_conf=4 659use_master_id=true 660 661[system.cpu.l2cache.tags] 662type=RandomRepl 663assoc=16 664block_size=64 665clk_domain=system.cpu_clk_domain 666eventq_index=0 667hit_latency=12 668sequential_access=false 669size=1048576 670 671[system.cpu.toL2Bus] 672type=CoherentXBar 673children=snoop_filter 674clk_domain=system.cpu_clk_domain 675eventq_index=0 676forward_latency=0 677frontend_latency=1 678response_latency=1 679snoop_filter=system.cpu.toL2Bus.snoop_filter 680snoop_response_latency=1 681system=system 682use_default_range=false 683width=32 684master=system.cpu.l2cache.cpu_side 685slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 686 687[system.cpu.toL2Bus.snoop_filter] 688type=SnoopFilter 689eventq_index=0 690lookup_latency=0 691max_capacity=8388608 692system=system 693 694[system.cpu.tracer] 695type=ExeTracer 696eventq_index=0 697 698[system.cpu.workload] 699type=LiveProcess 700cmd=hello 701cwd= 702drivers= 703egid=100 704env= 705errout=cerr 706euid=100 707eventq_index=0 708executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 709gid=100 710input=cin 711kvmInSE=false 712max_stack_size=67108864 713output=cout 714pid=100 715ppid=99 716simpoint=0 717system=system 718uid=100 719useArchPT=false 720 721[system.cpu_clk_domain] 722type=SrcClockDomain 723clock=500 724domain_id=-1 725eventq_index=0 726init_perf_level=0 727voltage_domain=system.voltage_domain 728 729[system.dvfs_handler] 730type=DVFSHandler 731domains= 732enable=false 733eventq_index=0 734sys_clk_domain=system.clk_domain 735transition_latency=100000000 736 737[system.membus] 738type=CoherentXBar 739clk_domain=system.clk_domain 740eventq_index=0 741forward_latency=4 742frontend_latency=3 743response_latency=2 744snoop_filter=Null 745snoop_response_latency=4 746system=system 747use_default_range=false 748width=16 749master=system.physmem.port 750slave=system.system_port system.cpu.l2cache.mem_side 751 752[system.physmem] 753type=DRAMCtrl 754IDD0=0.075000 755IDD02=0.000000 756IDD2N=0.050000 757IDD2N2=0.000000 758IDD2P0=0.000000 759IDD2P02=0.000000 760IDD2P1=0.000000 761IDD2P12=0.000000 762IDD3N=0.057000 763IDD3N2=0.000000 764IDD3P0=0.000000 765IDD3P02=0.000000 766IDD3P1=0.000000 767IDD3P12=0.000000 768IDD4R=0.187000 769IDD4R2=0.000000 770IDD4W=0.165000 771IDD4W2=0.000000 772IDD5=0.220000 773IDD52=0.000000 774IDD6=0.000000 775IDD62=0.000000 776VDD=1.500000 777VDD2=0.000000 778activation_limit=4 779addr_mapping=RoRaBaCoCh 780bank_groups_per_rank=0 781banks_per_rank=8 782burst_length=8 783channels=1 784clk_domain=system.clk_domain 785conf_table_reported=true 786device_bus_width=8 787device_rowbuffer_size=1024 788device_size=536870912 789devices_per_rank=8 790dll=true 791eventq_index=0 792in_addr_map=true 793max_accesses_per_row=16 794mem_sched_policy=frfcfs 795min_writes_per_switch=16 796null=false 797page_policy=open_adaptive 798range=0:134217727 799ranks_per_channel=2 800read_buffer_size=32 801static_backend_latency=10000 802static_frontend_latency=10000 803tBURST=5000 804tCCD_L=0 805tCK=1250 806tCL=13750 807tCS=2500 808tRAS=35000 809tRCD=13750 810tREFI=7800000 811tRFC=260000 812tRP=13750 813tRRD=6000 814tRRD_L=0 815tRTP=7500 816tRTW=2500 817tWR=15000 818tWTR=7500 819tXAW=30000 820tXP=0 821tXPDLL=0 822tXS=0 823tXSDLL=0 824write_buffer_size=64 825write_high_thresh_perc=85 826write_low_thresh_perc=50 827port=system.membus.master[0] 828 829[system.voltage_domain] 830type=VoltageDomain 831eventq_index=0 832voltage=1.000000 833 834