config.ini revision 8983
17860SN/A[root] 27860SN/Atype=Root 37860SN/Achildren=system 48825Snilay@cs.wisc.edufull_system=false 57935SN/Atime_sync_enable=false 67935SN/Atime_sync_period=100000000000 77935SN/Atime_sync_spin_threshold=100000000 87860SN/A 97860SN/A[system] 107860SN/Atype=System 117860SN/Achildren=cpu membus physmem 128825Snilay@cs.wisc.eduboot_osflags=a 138825Snilay@cs.wisc.eduinit_param=0 148825Snilay@cs.wisc.edukernel= 158825Snilay@cs.wisc.eduload_addr_mask=1099511627775 167860SN/Amem_mode=atomic 178464SN/Amemories=system.physmem 188721SN/Anum_work_ids=16 198825Snilay@cs.wisc.edureadfile= 208825Snilay@cs.wisc.edusymbolfile= 217935SN/Awork_begin_ckpt_count=0 227935SN/Awork_begin_cpu_id_exit=-1 237935SN/Awork_begin_exit_count=0 247935SN/Awork_cpus_ckpt_count=0 257935SN/Awork_end_ckpt_count=0 267935SN/Awork_end_exit_count=0 277935SN/Awork_item_id=-1 288893Ssaidi@eecs.umich.edusystem_port=system.membus.slave[0] 297860SN/A 307860SN/A[system.cpu] 317860SN/Atype=DerivO3CPU 328825Snilay@cs.wisc.educhildren=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 337860SN/ABTBEntries=4096 347860SN/ABTBTagSize=16 357860SN/ALFSTSize=1024 367860SN/ALQEntries=32 378210SN/ALSQCheckLoads=true 388210SN/ALSQDepCheckShift=4 397860SN/ARASSize=16 407860SN/ASQEntries=32 417860SN/ASSITSize=1024 427860SN/Aactivity=0 437860SN/AbackComSize=5 447860SN/AcachePorts=200 457860SN/Achecker=Null 467860SN/AchoiceCtrBits=2 477860SN/AchoicePredictorSize=8192 487860SN/Aclock=500 497860SN/AcommitToDecodeDelay=1 507860SN/AcommitToFetchDelay=1 517860SN/AcommitToIEWDelay=1 527860SN/AcommitToRenameDelay=1 537860SN/AcommitWidth=8 547860SN/Acpu_id=0 557860SN/AdecodeToFetchDelay=1 567860SN/AdecodeToRenameDelay=1 577860SN/AdecodeWidth=8 587860SN/Adefer_registration=false 597860SN/AdispatchWidth=8 607860SN/Ado_checkpoint_insts=true 618825Snilay@cs.wisc.edudo_quiesce=true 627860SN/Ado_statistics_insts=true 637860SN/Adtb=system.cpu.dtb 647860SN/AfetchToDecodeDelay=1 657860SN/AfetchTrapLatency=1 667860SN/AfetchWidth=8 677860SN/AforwardComSize=5 687860SN/AfuPool=system.cpu.fuPool 697860SN/Afunction_trace=false 707860SN/Afunction_trace_start=0 717860SN/AglobalCtrBits=2 727860SN/AglobalHistoryBits=13 737860SN/AglobalPredictorSize=8192 747860SN/AiewToCommitDelay=1 757860SN/AiewToDecodeDelay=1 767860SN/AiewToFetchDelay=1 777860SN/AiewToRenameDelay=1 787860SN/AinstShiftAmt=2 798825Snilay@cs.wisc.eduinterrupts=system.cpu.interrupts 807860SN/AissueToExecuteDelay=1 817860SN/AissueWidth=8 827860SN/Aitb=system.cpu.itb 837860SN/AlocalCtrBits=2 847860SN/AlocalHistoryBits=11 857860SN/AlocalHistoryTableSize=2048 867860SN/AlocalPredictorSize=2048 877860SN/Amax_insts_all_threads=0 887860SN/Amax_insts_any_thread=0 897860SN/Amax_loads_all_threads=0 907860SN/Amax_loads_any_thread=0 918825Snilay@cs.wisc.eduneedsTSO=false 927860SN/AnumIQEntries=64 937860SN/AnumPhysFloatRegs=256 947860SN/AnumPhysIntRegs=256 957860SN/AnumROBEntries=192 967860SN/AnumRobs=1 977860SN/AnumThreads=1 987860SN/Aphase=0 997860SN/ApredType=tournament 1008825Snilay@cs.wisc.eduprofile=0 1017860SN/Aprogress_interval=0 1027860SN/ArenameToDecodeDelay=1 1037860SN/ArenameToFetchDelay=1 1047860SN/ArenameToIEWDelay=2 1057860SN/ArenameToROBDelay=1 1067860SN/ArenameWidth=8 1077860SN/AsmtCommitPolicy=RoundRobin 1087860SN/AsmtFetchPolicy=SingleThread 1097860SN/AsmtIQPolicy=Partitioned 1107860SN/AsmtIQThreshold=100 1117860SN/AsmtLSQPolicy=Partitioned 1127860SN/AsmtLSQThreshold=100 1137860SN/AsmtNumFetchingThreads=1 1147860SN/AsmtROBPolicy=Partitioned 1157860SN/AsmtROBThreshold=100 1167860SN/AsquashWidth=8 1178546SN/Astore_set_clear_period=250000 1187860SN/Asystem=system 1197860SN/Atracer=system.cpu.tracer 1207860SN/AtrapLatency=13 1217860SN/AwbDepth=1 1227860SN/AwbWidth=8 1237860SN/Aworkload=system.cpu.workload 1247860SN/Adcache_port=system.cpu.dcache.cpu_side 1257860SN/Aicache_port=system.cpu.icache.cpu_side 1267860SN/A 1277860SN/A[system.cpu.dcache] 1287860SN/Atype=BaseCache 1298893Ssaidi@eecs.umich.eduaddr_ranges=0:18446744073709551615 1307860SN/Aassoc=2 1317860SN/Ablock_size=64 1327860SN/Aforward_snoops=true 1337860SN/Ahash_delay=1 1348150SN/Ais_top_level=true 1357860SN/Alatency=1000 1367860SN/Amax_miss_count=0 1377860SN/Amshrs=10 1387860SN/Aprefetch_on_access=false 1398835SAli.Saidi@ARM.comprefetcher=Null 1407860SN/AprioritizeRequests=false 1417860SN/Arepl=Null 1427860SN/Asize=262144 1437860SN/Asubblock_size=0 1448835SAli.Saidi@ARM.comsystem=system 1457860SN/Atgts_per_mshr=20 1467860SN/Atrace_addr=0 1477860SN/Atwo_queue=false 1487860SN/Awrite_buffers=8 1497860SN/Acpu_side=system.cpu.dcache_port 1508893Ssaidi@eecs.umich.edumem_side=system.cpu.toL2Bus.slave[1] 1517860SN/A 1527860SN/A[system.cpu.dtb] 1537860SN/Atype=ArmTLB 1548825Snilay@cs.wisc.educhildren=walker 1557860SN/Asize=64 1568825Snilay@cs.wisc.eduwalker=system.cpu.dtb.walker 1578825Snilay@cs.wisc.edu 1588825Snilay@cs.wisc.edu[system.cpu.dtb.walker] 1598825Snilay@cs.wisc.edutype=ArmTableWalker 1608825Snilay@cs.wisc.edumax_backoff=100000 1618825Snilay@cs.wisc.edumin_backoff=0 1628825Snilay@cs.wisc.edusys=system 1638893Ssaidi@eecs.umich.eduport=system.cpu.toL2Bus.slave[3] 1647860SN/A 1657860SN/A[system.cpu.fuPool] 1667860SN/Atype=FUPool 1677860SN/Achildren=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1687860SN/AFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 1697860SN/A 1707860SN/A[system.cpu.fuPool.FUList0] 1717860SN/Atype=FUDesc 1727860SN/Achildren=opList 1737860SN/Acount=6 1747860SN/AopList=system.cpu.fuPool.FUList0.opList 1757860SN/A 1767860SN/A[system.cpu.fuPool.FUList0.opList] 1777860SN/Atype=OpDesc 1787860SN/AissueLat=1 1797860SN/AopClass=IntAlu 1807860SN/AopLat=1 1817860SN/A 1827860SN/A[system.cpu.fuPool.FUList1] 1837860SN/Atype=FUDesc 1847860SN/Achildren=opList0 opList1 1857860SN/Acount=2 1867860SN/AopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 1877860SN/A 1887860SN/A[system.cpu.fuPool.FUList1.opList0] 1897860SN/Atype=OpDesc 1907860SN/AissueLat=1 1917860SN/AopClass=IntMult 1927860SN/AopLat=3 1937860SN/A 1947860SN/A[system.cpu.fuPool.FUList1.opList1] 1957860SN/Atype=OpDesc 1967860SN/AissueLat=19 1977860SN/AopClass=IntDiv 1987860SN/AopLat=20 1997860SN/A 2007860SN/A[system.cpu.fuPool.FUList2] 2017860SN/Atype=FUDesc 2027860SN/Achildren=opList0 opList1 opList2 2037860SN/Acount=4 2047860SN/AopList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 2057860SN/A 2067860SN/A[system.cpu.fuPool.FUList2.opList0] 2077860SN/Atype=OpDesc 2087860SN/AissueLat=1 2097860SN/AopClass=FloatAdd 2107860SN/AopLat=2 2117860SN/A 2127860SN/A[system.cpu.fuPool.FUList2.opList1] 2137860SN/Atype=OpDesc 2147860SN/AissueLat=1 2157860SN/AopClass=FloatCmp 2167860SN/AopLat=2 2177860SN/A 2187860SN/A[system.cpu.fuPool.FUList2.opList2] 2197860SN/Atype=OpDesc 2207860SN/AissueLat=1 2217860SN/AopClass=FloatCvt 2227860SN/AopLat=2 2237860SN/A 2247860SN/A[system.cpu.fuPool.FUList3] 2257860SN/Atype=FUDesc 2267860SN/Achildren=opList0 opList1 opList2 2277860SN/Acount=2 2287860SN/AopList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 2297860SN/A 2307860SN/A[system.cpu.fuPool.FUList3.opList0] 2317860SN/Atype=OpDesc 2327860SN/AissueLat=1 2337860SN/AopClass=FloatMult 2347860SN/AopLat=4 2357860SN/A 2367860SN/A[system.cpu.fuPool.FUList3.opList1] 2377860SN/Atype=OpDesc 2387860SN/AissueLat=12 2397860SN/AopClass=FloatDiv 2407860SN/AopLat=12 2417860SN/A 2427860SN/A[system.cpu.fuPool.FUList3.opList2] 2437860SN/Atype=OpDesc 2447860SN/AissueLat=24 2457860SN/AopClass=FloatSqrt 2467860SN/AopLat=24 2477860SN/A 2487860SN/A[system.cpu.fuPool.FUList4] 2497860SN/Atype=FUDesc 2507860SN/Achildren=opList 2517860SN/Acount=0 2527860SN/AopList=system.cpu.fuPool.FUList4.opList 2537860SN/A 2547860SN/A[system.cpu.fuPool.FUList4.opList] 2557860SN/Atype=OpDesc 2567860SN/AissueLat=1 2577860SN/AopClass=MemRead 2587860SN/AopLat=1 2597860SN/A 2607860SN/A[system.cpu.fuPool.FUList5] 2617860SN/Atype=FUDesc 2627860SN/Achildren=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 2637860SN/Acount=4 2647860SN/AopList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 2657860SN/A 2667860SN/A[system.cpu.fuPool.FUList5.opList00] 2677860SN/Atype=OpDesc 2687860SN/AissueLat=1 2697860SN/AopClass=SimdAdd 2707860SN/AopLat=1 2717860SN/A 2727860SN/A[system.cpu.fuPool.FUList5.opList01] 2737860SN/Atype=OpDesc 2747860SN/AissueLat=1 2757860SN/AopClass=SimdAddAcc 2767860SN/AopLat=1 2777860SN/A 2787860SN/A[system.cpu.fuPool.FUList5.opList02] 2797860SN/Atype=OpDesc 2807860SN/AissueLat=1 2817860SN/AopClass=SimdAlu 2827860SN/AopLat=1 2837860SN/A 2847860SN/A[system.cpu.fuPool.FUList5.opList03] 2857860SN/Atype=OpDesc 2867860SN/AissueLat=1 2877860SN/AopClass=SimdCmp 2887860SN/AopLat=1 2897860SN/A 2907860SN/A[system.cpu.fuPool.FUList5.opList04] 2917860SN/Atype=OpDesc 2927860SN/AissueLat=1 2937860SN/AopClass=SimdCvt 2947860SN/AopLat=1 2957860SN/A 2967860SN/A[system.cpu.fuPool.FUList5.opList05] 2977860SN/Atype=OpDesc 2987860SN/AissueLat=1 2997860SN/AopClass=SimdMisc 3007860SN/AopLat=1 3017860SN/A 3027860SN/A[system.cpu.fuPool.FUList5.opList06] 3037860SN/Atype=OpDesc 3047860SN/AissueLat=1 3057860SN/AopClass=SimdMult 3067860SN/AopLat=1 3077860SN/A 3087860SN/A[system.cpu.fuPool.FUList5.opList07] 3097860SN/Atype=OpDesc 3107860SN/AissueLat=1 3117860SN/AopClass=SimdMultAcc 3127860SN/AopLat=1 3137860SN/A 3147860SN/A[system.cpu.fuPool.FUList5.opList08] 3157860SN/Atype=OpDesc 3167860SN/AissueLat=1 3177860SN/AopClass=SimdShift 3187860SN/AopLat=1 3197860SN/A 3207860SN/A[system.cpu.fuPool.FUList5.opList09] 3217860SN/Atype=OpDesc 3227860SN/AissueLat=1 3237860SN/AopClass=SimdShiftAcc 3247860SN/AopLat=1 3257860SN/A 3267860SN/A[system.cpu.fuPool.FUList5.opList10] 3277860SN/Atype=OpDesc 3287860SN/AissueLat=1 3297860SN/AopClass=SimdSqrt 3307860SN/AopLat=1 3317860SN/A 3327860SN/A[system.cpu.fuPool.FUList5.opList11] 3337860SN/Atype=OpDesc 3347860SN/AissueLat=1 3357860SN/AopClass=SimdFloatAdd 3367860SN/AopLat=1 3377860SN/A 3387860SN/A[system.cpu.fuPool.FUList5.opList12] 3397860SN/Atype=OpDesc 3407860SN/AissueLat=1 3417860SN/AopClass=SimdFloatAlu 3427860SN/AopLat=1 3437860SN/A 3447860SN/A[system.cpu.fuPool.FUList5.opList13] 3457860SN/Atype=OpDesc 3467860SN/AissueLat=1 3477860SN/AopClass=SimdFloatCmp 3487860SN/AopLat=1 3497860SN/A 3507860SN/A[system.cpu.fuPool.FUList5.opList14] 3517860SN/Atype=OpDesc 3527860SN/AissueLat=1 3537860SN/AopClass=SimdFloatCvt 3547860SN/AopLat=1 3557860SN/A 3567860SN/A[system.cpu.fuPool.FUList5.opList15] 3577860SN/Atype=OpDesc 3587860SN/AissueLat=1 3597860SN/AopClass=SimdFloatDiv 3607860SN/AopLat=1 3617860SN/A 3627860SN/A[system.cpu.fuPool.FUList5.opList16] 3637860SN/Atype=OpDesc 3647860SN/AissueLat=1 3657860SN/AopClass=SimdFloatMisc 3667860SN/AopLat=1 3677860SN/A 3687860SN/A[system.cpu.fuPool.FUList5.opList17] 3697860SN/Atype=OpDesc 3707860SN/AissueLat=1 3717860SN/AopClass=SimdFloatMult 3727860SN/AopLat=1 3737860SN/A 3747860SN/A[system.cpu.fuPool.FUList5.opList18] 3757860SN/Atype=OpDesc 3767860SN/AissueLat=1 3777860SN/AopClass=SimdFloatMultAcc 3787860SN/AopLat=1 3797860SN/A 3807860SN/A[system.cpu.fuPool.FUList5.opList19] 3817860SN/Atype=OpDesc 3827860SN/AissueLat=1 3837860SN/AopClass=SimdFloatSqrt 3847860SN/AopLat=1 3857860SN/A 3867860SN/A[system.cpu.fuPool.FUList6] 3877860SN/Atype=FUDesc 3887860SN/Achildren=opList 3897860SN/Acount=0 3907860SN/AopList=system.cpu.fuPool.FUList6.opList 3917860SN/A 3927860SN/A[system.cpu.fuPool.FUList6.opList] 3937860SN/Atype=OpDesc 3947860SN/AissueLat=1 3957860SN/AopClass=MemWrite 3967860SN/AopLat=1 3977860SN/A 3987860SN/A[system.cpu.fuPool.FUList7] 3997860SN/Atype=FUDesc 4007860SN/Achildren=opList0 opList1 4017860SN/Acount=4 4027860SN/AopList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 4037860SN/A 4047860SN/A[system.cpu.fuPool.FUList7.opList0] 4057860SN/Atype=OpDesc 4067860SN/AissueLat=1 4077860SN/AopClass=MemRead 4087860SN/AopLat=1 4097860SN/A 4107860SN/A[system.cpu.fuPool.FUList7.opList1] 4117860SN/Atype=OpDesc 4127860SN/AissueLat=1 4137860SN/AopClass=MemWrite 4147860SN/AopLat=1 4157860SN/A 4167860SN/A[system.cpu.fuPool.FUList8] 4177860SN/Atype=FUDesc 4187860SN/Achildren=opList 4197860SN/Acount=1 4207860SN/AopList=system.cpu.fuPool.FUList8.opList 4217860SN/A 4227860SN/A[system.cpu.fuPool.FUList8.opList] 4237860SN/Atype=OpDesc 4247860SN/AissueLat=3 4257860SN/AopClass=IprAccess 4267860SN/AopLat=3 4277860SN/A 4287860SN/A[system.cpu.icache] 4297860SN/Atype=BaseCache 4308893Ssaidi@eecs.umich.eduaddr_ranges=0:18446744073709551615 4317860SN/Aassoc=2 4327860SN/Ablock_size=64 4337860SN/Aforward_snoops=true 4347860SN/Ahash_delay=1 4358150SN/Ais_top_level=true 4367860SN/Alatency=1000 4377860SN/Amax_miss_count=0 4387860SN/Amshrs=10 4397860SN/Aprefetch_on_access=false 4408835SAli.Saidi@ARM.comprefetcher=Null 4417860SN/AprioritizeRequests=false 4427860SN/Arepl=Null 4437860SN/Asize=131072 4447860SN/Asubblock_size=0 4458835SAli.Saidi@ARM.comsystem=system 4467860SN/Atgts_per_mshr=20 4477860SN/Atrace_addr=0 4487860SN/Atwo_queue=false 4497860SN/Awrite_buffers=8 4507860SN/Acpu_side=system.cpu.icache_port 4518893Ssaidi@eecs.umich.edumem_side=system.cpu.toL2Bus.slave[0] 4527860SN/A 4538825Snilay@cs.wisc.edu[system.cpu.interrupts] 4548825Snilay@cs.wisc.edutype=ArmInterrupts 4558825Snilay@cs.wisc.edu 4567860SN/A[system.cpu.itb] 4577860SN/Atype=ArmTLB 4588825Snilay@cs.wisc.educhildren=walker 4597860SN/Asize=64 4608825Snilay@cs.wisc.eduwalker=system.cpu.itb.walker 4618825Snilay@cs.wisc.edu 4628825Snilay@cs.wisc.edu[system.cpu.itb.walker] 4638825Snilay@cs.wisc.edutype=ArmTableWalker 4648825Snilay@cs.wisc.edumax_backoff=100000 4658825Snilay@cs.wisc.edumin_backoff=0 4668825Snilay@cs.wisc.edusys=system 4678893Ssaidi@eecs.umich.eduport=system.cpu.toL2Bus.slave[2] 4687860SN/A 4697860SN/A[system.cpu.l2cache] 4707860SN/Atype=BaseCache 4718893Ssaidi@eecs.umich.eduaddr_ranges=0:18446744073709551615 4727860SN/Aassoc=2 4737860SN/Ablock_size=64 4747860SN/Aforward_snoops=true 4757860SN/Ahash_delay=1 4768150SN/Ais_top_level=false 4777860SN/Alatency=1000 4787860SN/Amax_miss_count=0 4797860SN/Amshrs=10 4807860SN/Aprefetch_on_access=false 4818835SAli.Saidi@ARM.comprefetcher=Null 4827860SN/AprioritizeRequests=false 4837860SN/Arepl=Null 4847860SN/Asize=2097152 4857860SN/Asubblock_size=0 4868835SAli.Saidi@ARM.comsystem=system 4877860SN/Atgts_per_mshr=5 4887860SN/Atrace_addr=0 4897860SN/Atwo_queue=false 4907860SN/Awrite_buffers=8 4918893Ssaidi@eecs.umich.educpu_side=system.cpu.toL2Bus.master[0] 4928893Ssaidi@eecs.umich.edumem_side=system.membus.slave[1] 4937860SN/A 4947860SN/A[system.cpu.toL2Bus] 4957860SN/Atype=Bus 4967860SN/Ablock_size=64 4977860SN/Abus_id=0 4987860SN/Aclock=1000 4997860SN/Aheader_cycles=1 5007860SN/Ause_default_range=false 5017860SN/Awidth=64 5028893Ssaidi@eecs.umich.edumaster=system.cpu.l2cache.cpu_side 5038893Ssaidi@eecs.umich.eduslave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 5047860SN/A 5057860SN/A[system.cpu.tracer] 5067860SN/Atype=ExeTracer 5077860SN/A 5087860SN/A[system.cpu.workload] 5097860SN/Atype=LiveProcess 5107860SN/Acmd=hello 5117860SN/Acwd= 5127860SN/Aegid=100 5137860SN/Aenv= 5147860SN/Aerrout=cerr 5157860SN/Aeuid=100 5168983Snate@binkert.orgexecutable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 5177860SN/Agid=100 5187860SN/Ainput=cin 5197860SN/Amax_stack_size=67108864 5207860SN/Aoutput=cout 5217860SN/Apid=100 5227860SN/Appid=99 5237860SN/Asimpoint=0 5247860SN/Asystem=system 5257860SN/Auid=100 5267860SN/A 5277860SN/A[system.membus] 5287860SN/Atype=Bus 5297860SN/Ablock_size=64 5307860SN/Abus_id=0 5317860SN/Aclock=1000 5327860SN/Aheader_cycles=1 5337860SN/Ause_default_range=false 5347860SN/Awidth=64 5358893Ssaidi@eecs.umich.edumaster=system.physmem.port[0] 5368893Ssaidi@eecs.umich.eduslave=system.system_port system.cpu.l2cache.mem_side 5377860SN/A 5387860SN/A[system.physmem] 5398983Snate@binkert.orgtype=SimpleMemory 5408983Snate@binkert.orgconf_table_reported=false 5417860SN/Afile= 5428983Snate@binkert.orgin_addr_map=true 5437860SN/Alatency=30000 5447860SN/Alatency_var=0 5457860SN/Anull=false 5467860SN/Arange=0:134217727 5477860SN/Azero=false 5488893Ssaidi@eecs.umich.eduport=system.membus.master[0] 5497860SN/A 550