config.ini revision 8210
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu membus physmem 11mem_mode=atomic 12physmem=system.physmem 13work_begin_ckpt_count=0 14work_begin_cpu_id_exit=-1 15work_begin_exit_count=0 16work_cpus_ckpt_count=0 17work_end_ckpt_count=0 18work_end_exit_count=0 19work_item_id=-1 20 21[system.cpu] 22type=DerivO3CPU 23children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 24BTBEntries=4096 25BTBTagSize=16 26LFSTSize=1024 27LQEntries=32 28LSQCheckLoads=true 29LSQDepCheckShift=4 30RASSize=16 31SQEntries=32 32SSITSize=1024 33activity=0 34backComSize=5 35cachePorts=200 36checker=Null 37choiceCtrBits=2 38choicePredictorSize=8192 39clock=500 40commitToDecodeDelay=1 41commitToFetchDelay=1 42commitToIEWDelay=1 43commitToRenameDelay=1 44commitWidth=8 45cpu_id=0 46decodeToFetchDelay=1 47decodeToRenameDelay=1 48decodeWidth=8 49defer_registration=false 50dispatchWidth=8 51do_checkpoint_insts=true 52do_statistics_insts=true 53dtb=system.cpu.dtb 54fetchToDecodeDelay=1 55fetchTrapLatency=1 56fetchWidth=8 57forwardComSize=5 58fuPool=system.cpu.fuPool 59function_trace=false 60function_trace_start=0 61globalCtrBits=2 62globalHistoryBits=13 63globalPredictorSize=8192 64iewToCommitDelay=1 65iewToDecodeDelay=1 66iewToFetchDelay=1 67iewToRenameDelay=1 68instShiftAmt=2 69issueToExecuteDelay=1 70issueWidth=8 71itb=system.cpu.itb 72localCtrBits=2 73localHistoryBits=11 74localHistoryTableSize=2048 75localPredictorSize=2048 76max_insts_all_threads=0 77max_insts_any_thread=0 78max_loads_all_threads=0 79max_loads_any_thread=0 80numIQEntries=64 81numPhysFloatRegs=256 82numPhysIntRegs=256 83numROBEntries=192 84numRobs=1 85numThreads=1 86phase=0 87predType=tournament 88progress_interval=0 89renameToDecodeDelay=1 90renameToFetchDelay=1 91renameToIEWDelay=2 92renameToROBDelay=1 93renameWidth=8 94smtCommitPolicy=RoundRobin 95smtFetchPolicy=SingleThread 96smtIQPolicy=Partitioned 97smtIQThreshold=100 98smtLSQPolicy=Partitioned 99smtLSQThreshold=100 100smtNumFetchingThreads=1 101smtROBPolicy=Partitioned 102smtROBThreshold=100 103squashWidth=8 104system=system 105tracer=system.cpu.tracer 106trapLatency=13 107wbDepth=1 108wbWidth=8 109workload=system.cpu.workload 110dcache_port=system.cpu.dcache.cpu_side 111icache_port=system.cpu.icache.cpu_side 112 113[system.cpu.dcache] 114type=BaseCache 115addr_range=0:18446744073709551615 116assoc=2 117block_size=64 118forward_snoops=true 119hash_delay=1 120is_top_level=true 121latency=1000 122max_miss_count=0 123mshrs=10 124num_cpus=1 125prefetch_data_accesses_only=false 126prefetch_degree=1 127prefetch_latency=10000 128prefetch_on_access=false 129prefetch_past_page=false 130prefetch_policy=none 131prefetch_serial_squash=false 132prefetch_use_cpu_id=true 133prefetcher_size=100 134prioritizeRequests=false 135repl=Null 136size=262144 137subblock_size=0 138tgts_per_mshr=20 139trace_addr=0 140two_queue=false 141write_buffers=8 142cpu_side=system.cpu.dcache_port 143mem_side=system.cpu.toL2Bus.port[1] 144 145[system.cpu.dtb] 146type=ArmTLB 147size=64 148 149[system.cpu.fuPool] 150type=FUPool 151children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 152FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 153 154[system.cpu.fuPool.FUList0] 155type=FUDesc 156children=opList 157count=6 158opList=system.cpu.fuPool.FUList0.opList 159 160[system.cpu.fuPool.FUList0.opList] 161type=OpDesc 162issueLat=1 163opClass=IntAlu 164opLat=1 165 166[system.cpu.fuPool.FUList1] 167type=FUDesc 168children=opList0 opList1 169count=2 170opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 171 172[system.cpu.fuPool.FUList1.opList0] 173type=OpDesc 174issueLat=1 175opClass=IntMult 176opLat=3 177 178[system.cpu.fuPool.FUList1.opList1] 179type=OpDesc 180issueLat=19 181opClass=IntDiv 182opLat=20 183 184[system.cpu.fuPool.FUList2] 185type=FUDesc 186children=opList0 opList1 opList2 187count=4 188opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 189 190[system.cpu.fuPool.FUList2.opList0] 191type=OpDesc 192issueLat=1 193opClass=FloatAdd 194opLat=2 195 196[system.cpu.fuPool.FUList2.opList1] 197type=OpDesc 198issueLat=1 199opClass=FloatCmp 200opLat=2 201 202[system.cpu.fuPool.FUList2.opList2] 203type=OpDesc 204issueLat=1 205opClass=FloatCvt 206opLat=2 207 208[system.cpu.fuPool.FUList3] 209type=FUDesc 210children=opList0 opList1 opList2 211count=2 212opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 213 214[system.cpu.fuPool.FUList3.opList0] 215type=OpDesc 216issueLat=1 217opClass=FloatMult 218opLat=4 219 220[system.cpu.fuPool.FUList3.opList1] 221type=OpDesc 222issueLat=12 223opClass=FloatDiv 224opLat=12 225 226[system.cpu.fuPool.FUList3.opList2] 227type=OpDesc 228issueLat=24 229opClass=FloatSqrt 230opLat=24 231 232[system.cpu.fuPool.FUList4] 233type=FUDesc 234children=opList 235count=0 236opList=system.cpu.fuPool.FUList4.opList 237 238[system.cpu.fuPool.FUList4.opList] 239type=OpDesc 240issueLat=1 241opClass=MemRead 242opLat=1 243 244[system.cpu.fuPool.FUList5] 245type=FUDesc 246children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 247count=4 248opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 249 250[system.cpu.fuPool.FUList5.opList00] 251type=OpDesc 252issueLat=1 253opClass=SimdAdd 254opLat=1 255 256[system.cpu.fuPool.FUList5.opList01] 257type=OpDesc 258issueLat=1 259opClass=SimdAddAcc 260opLat=1 261 262[system.cpu.fuPool.FUList5.opList02] 263type=OpDesc 264issueLat=1 265opClass=SimdAlu 266opLat=1 267 268[system.cpu.fuPool.FUList5.opList03] 269type=OpDesc 270issueLat=1 271opClass=SimdCmp 272opLat=1 273 274[system.cpu.fuPool.FUList5.opList04] 275type=OpDesc 276issueLat=1 277opClass=SimdCvt 278opLat=1 279 280[system.cpu.fuPool.FUList5.opList05] 281type=OpDesc 282issueLat=1 283opClass=SimdMisc 284opLat=1 285 286[system.cpu.fuPool.FUList5.opList06] 287type=OpDesc 288issueLat=1 289opClass=SimdMult 290opLat=1 291 292[system.cpu.fuPool.FUList5.opList07] 293type=OpDesc 294issueLat=1 295opClass=SimdMultAcc 296opLat=1 297 298[system.cpu.fuPool.FUList5.opList08] 299type=OpDesc 300issueLat=1 301opClass=SimdShift 302opLat=1 303 304[system.cpu.fuPool.FUList5.opList09] 305type=OpDesc 306issueLat=1 307opClass=SimdShiftAcc 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList10] 311type=OpDesc 312issueLat=1 313opClass=SimdSqrt 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList11] 317type=OpDesc 318issueLat=1 319opClass=SimdFloatAdd 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList12] 323type=OpDesc 324issueLat=1 325opClass=SimdFloatAlu 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList13] 329type=OpDesc 330issueLat=1 331opClass=SimdFloatCmp 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList14] 335type=OpDesc 336issueLat=1 337opClass=SimdFloatCvt 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList15] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatDiv 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList16] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatMisc 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList17] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatMult 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList18] 359type=OpDesc 360issueLat=1 361opClass=SimdFloatMultAcc 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList19] 365type=OpDesc 366issueLat=1 367opClass=SimdFloatSqrt 368opLat=1 369 370[system.cpu.fuPool.FUList6] 371type=FUDesc 372children=opList 373count=0 374opList=system.cpu.fuPool.FUList6.opList 375 376[system.cpu.fuPool.FUList6.opList] 377type=OpDesc 378issueLat=1 379opClass=MemWrite 380opLat=1 381 382[system.cpu.fuPool.FUList7] 383type=FUDesc 384children=opList0 opList1 385count=4 386opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 387 388[system.cpu.fuPool.FUList7.opList0] 389type=OpDesc 390issueLat=1 391opClass=MemRead 392opLat=1 393 394[system.cpu.fuPool.FUList7.opList1] 395type=OpDesc 396issueLat=1 397opClass=MemWrite 398opLat=1 399 400[system.cpu.fuPool.FUList8] 401type=FUDesc 402children=opList 403count=1 404opList=system.cpu.fuPool.FUList8.opList 405 406[system.cpu.fuPool.FUList8.opList] 407type=OpDesc 408issueLat=3 409opClass=IprAccess 410opLat=3 411 412[system.cpu.icache] 413type=BaseCache 414addr_range=0:18446744073709551615 415assoc=2 416block_size=64 417forward_snoops=true 418hash_delay=1 419is_top_level=true 420latency=1000 421max_miss_count=0 422mshrs=10 423num_cpus=1 424prefetch_data_accesses_only=false 425prefetch_degree=1 426prefetch_latency=10000 427prefetch_on_access=false 428prefetch_past_page=false 429prefetch_policy=none 430prefetch_serial_squash=false 431prefetch_use_cpu_id=true 432prefetcher_size=100 433prioritizeRequests=false 434repl=Null 435size=131072 436subblock_size=0 437tgts_per_mshr=20 438trace_addr=0 439two_queue=false 440write_buffers=8 441cpu_side=system.cpu.icache_port 442mem_side=system.cpu.toL2Bus.port[0] 443 444[system.cpu.itb] 445type=ArmTLB 446size=64 447 448[system.cpu.l2cache] 449type=BaseCache 450addr_range=0:18446744073709551615 451assoc=2 452block_size=64 453forward_snoops=true 454hash_delay=1 455is_top_level=false 456latency=1000 457max_miss_count=0 458mshrs=10 459num_cpus=1 460prefetch_data_accesses_only=false 461prefetch_degree=1 462prefetch_latency=10000 463prefetch_on_access=false 464prefetch_past_page=false 465prefetch_policy=none 466prefetch_serial_squash=false 467prefetch_use_cpu_id=true 468prefetcher_size=100 469prioritizeRequests=false 470repl=Null 471size=2097152 472subblock_size=0 473tgts_per_mshr=5 474trace_addr=0 475two_queue=false 476write_buffers=8 477cpu_side=system.cpu.toL2Bus.port[2] 478mem_side=system.membus.port[1] 479 480[system.cpu.toL2Bus] 481type=Bus 482block_size=64 483bus_id=0 484clock=1000 485header_cycles=1 486use_default_range=false 487width=64 488port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 489 490[system.cpu.tracer] 491type=ExeTracer 492 493[system.cpu.workload] 494type=LiveProcess 495cmd=hello 496cwd= 497egid=100 498env= 499errout=cerr 500euid=100 501executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello 502gid=100 503input=cin 504max_stack_size=67108864 505output=cout 506pid=100 507ppid=99 508simpoint=0 509system=system 510uid=100 511 512[system.membus] 513type=Bus 514block_size=64 515bus_id=0 516clock=1000 517header_cycles=1 518use_default_range=false 519width=64 520port=system.physmem.port[0] system.cpu.l2cache.mem_side 521 522[system.physmem] 523type=PhysicalMemory 524file= 525latency=30000 526latency_var=0 527null=false 528range=0:134217727 529zero=false 530port=system.membus.port[0] 531 532