config.ini revision 9924:31ef410b6843
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu.branchPred 50cachePorts=200 51checker=system.cpu.checker 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=false 88numIQEntries=64 89numPhysCCRegs=0 90numPhysFloatRegs=256 91numPhysIntRegs=256 92numROBEntries=192 93numRobs=1 94numThreads=1 95profile=0 96progress_interval=0 97renameToDecodeDelay=1 98renameToFetchDelay=1 99renameToIEWDelay=2 100renameToROBDelay=1 101renameWidth=8 102simpoint_start_insts= 103smtCommitPolicy=RoundRobin 104smtFetchPolicy=SingleThread 105smtIQPolicy=Partitioned 106smtIQThreshold=100 107smtLSQPolicy=Partitioned 108smtLSQThreshold=100 109smtNumFetchingThreads=1 110smtROBPolicy=Partitioned 111smtROBThreshold=100 112squashWidth=8 113store_set_clear_period=250000 114switched_out=false 115system=system 116tracer=system.cpu.tracer 117trapLatency=13 118wbDepth=1 119wbWidth=8 120workload=system.cpu.workload 121dcache_port=system.cpu.dcache.cpu_side 122icache_port=system.cpu.icache.cpu_side 123 124[system.cpu.branchPred] 125type=BranchPredictor 126BTBEntries=4096 127BTBTagSize=16 128RASSize=16 129choiceCtrBits=2 130choicePredictorSize=8192 131globalCtrBits=2 132globalPredictorSize=8192 133instShiftAmt=2 134localCtrBits=2 135localHistoryTableSize=2048 136localPredictorSize=2048 137numThreads=1 138predType=tournament 139 140[system.cpu.checker] 141type=O3Checker 142children=dtb isa itb tracer 143checker=Null 144clk_domain=system.cpu_clk_domain 145cpu_id=0 146do_checkpoint_insts=true 147do_quiesce=true 148do_statistics_insts=true 149dtb=system.cpu.checker.dtb 150exitOnError=false 151function_trace=false 152function_trace_start=0 153interrupts=Null 154isa=system.cpu.checker.isa 155itb=system.cpu.checker.itb 156max_insts_all_threads=0 157max_insts_any_thread=0 158max_loads_all_threads=0 159max_loads_any_thread=0 160numThreads=1 161profile=0 162progress_interval=0 163simpoint_start_insts= 164switched_out=false 165system=system 166tracer=system.cpu.checker.tracer 167updateOnError=true 168warnOnlyOnLoadError=true 169workload=system.cpu.workload 170 171[system.cpu.checker.dtb] 172type=ArmTLB 173children=walker 174size=64 175walker=system.cpu.checker.dtb.walker 176 177[system.cpu.checker.dtb.walker] 178type=ArmTableWalker 179clk_domain=system.cpu_clk_domain 180num_squash_per_cycle=2 181sys=system 182port=system.cpu.toL2Bus.slave[5] 183 184[system.cpu.checker.isa] 185type=ArmISA 186fpsid=1090793632 187id_isar0=34607377 188id_isar1=34677009 189id_isar2=555950401 190id_isar3=17899825 191id_isar4=268501314 192id_isar5=0 193id_mmfr0=3 194id_mmfr1=0 195id_mmfr2=19070976 196id_mmfr3=4027589137 197id_pfr0=49 198id_pfr1=1 199midr=890224640 200 201[system.cpu.checker.itb] 202type=ArmTLB 203children=walker 204size=64 205walker=system.cpu.checker.itb.walker 206 207[system.cpu.checker.itb.walker] 208type=ArmTableWalker 209clk_domain=system.cpu_clk_domain 210num_squash_per_cycle=2 211sys=system 212port=system.cpu.toL2Bus.slave[4] 213 214[system.cpu.checker.tracer] 215type=ExeTracer 216 217[system.cpu.dcache] 218type=BaseCache 219children=tags 220addr_ranges=0:18446744073709551615 221assoc=2 222clk_domain=system.cpu_clk_domain 223forward_snoops=true 224hit_latency=2 225is_top_level=true 226max_miss_count=0 227mshrs=4 228prefetch_on_access=false 229prefetcher=Null 230response_latency=2 231size=262144 232system=system 233tags=system.cpu.dcache.tags 234tgts_per_mshr=20 235two_queue=false 236write_buffers=8 237cpu_side=system.cpu.dcache_port 238mem_side=system.cpu.toL2Bus.slave[1] 239 240[system.cpu.dcache.tags] 241type=LRU 242assoc=2 243block_size=64 244clk_domain=system.cpu_clk_domain 245hit_latency=2 246size=262144 247 248[system.cpu.dtb] 249type=ArmTLB 250children=walker 251size=64 252walker=system.cpu.dtb.walker 253 254[system.cpu.dtb.walker] 255type=ArmTableWalker 256clk_domain=system.cpu_clk_domain 257num_squash_per_cycle=2 258sys=system 259port=system.cpu.toL2Bus.slave[3] 260 261[system.cpu.fuPool] 262type=FUPool 263children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 264FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 265 266[system.cpu.fuPool.FUList0] 267type=FUDesc 268children=opList 269count=6 270opList=system.cpu.fuPool.FUList0.opList 271 272[system.cpu.fuPool.FUList0.opList] 273type=OpDesc 274issueLat=1 275opClass=IntAlu 276opLat=1 277 278[system.cpu.fuPool.FUList1] 279type=FUDesc 280children=opList0 opList1 281count=2 282opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 283 284[system.cpu.fuPool.FUList1.opList0] 285type=OpDesc 286issueLat=1 287opClass=IntMult 288opLat=3 289 290[system.cpu.fuPool.FUList1.opList1] 291type=OpDesc 292issueLat=19 293opClass=IntDiv 294opLat=20 295 296[system.cpu.fuPool.FUList2] 297type=FUDesc 298children=opList0 opList1 opList2 299count=4 300opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 301 302[system.cpu.fuPool.FUList2.opList0] 303type=OpDesc 304issueLat=1 305opClass=FloatAdd 306opLat=2 307 308[system.cpu.fuPool.FUList2.opList1] 309type=OpDesc 310issueLat=1 311opClass=FloatCmp 312opLat=2 313 314[system.cpu.fuPool.FUList2.opList2] 315type=OpDesc 316issueLat=1 317opClass=FloatCvt 318opLat=2 319 320[system.cpu.fuPool.FUList3] 321type=FUDesc 322children=opList0 opList1 opList2 323count=2 324opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 325 326[system.cpu.fuPool.FUList3.opList0] 327type=OpDesc 328issueLat=1 329opClass=FloatMult 330opLat=4 331 332[system.cpu.fuPool.FUList3.opList1] 333type=OpDesc 334issueLat=12 335opClass=FloatDiv 336opLat=12 337 338[system.cpu.fuPool.FUList3.opList2] 339type=OpDesc 340issueLat=24 341opClass=FloatSqrt 342opLat=24 343 344[system.cpu.fuPool.FUList4] 345type=FUDesc 346children=opList 347count=0 348opList=system.cpu.fuPool.FUList4.opList 349 350[system.cpu.fuPool.FUList4.opList] 351type=OpDesc 352issueLat=1 353opClass=MemRead 354opLat=1 355 356[system.cpu.fuPool.FUList5] 357type=FUDesc 358children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 359count=4 360opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 361 362[system.cpu.fuPool.FUList5.opList00] 363type=OpDesc 364issueLat=1 365opClass=SimdAdd 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList01] 369type=OpDesc 370issueLat=1 371opClass=SimdAddAcc 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList02] 375type=OpDesc 376issueLat=1 377opClass=SimdAlu 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList03] 381type=OpDesc 382issueLat=1 383opClass=SimdCmp 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList04] 387type=OpDesc 388issueLat=1 389opClass=SimdCvt 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList05] 393type=OpDesc 394issueLat=1 395opClass=SimdMisc 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList06] 399type=OpDesc 400issueLat=1 401opClass=SimdMult 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList07] 405type=OpDesc 406issueLat=1 407opClass=SimdMultAcc 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList08] 411type=OpDesc 412issueLat=1 413opClass=SimdShift 414opLat=1 415 416[system.cpu.fuPool.FUList5.opList09] 417type=OpDesc 418issueLat=1 419opClass=SimdShiftAcc 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList10] 423type=OpDesc 424issueLat=1 425opClass=SimdSqrt 426opLat=1 427 428[system.cpu.fuPool.FUList5.opList11] 429type=OpDesc 430issueLat=1 431opClass=SimdFloatAdd 432opLat=1 433 434[system.cpu.fuPool.FUList5.opList12] 435type=OpDesc 436issueLat=1 437opClass=SimdFloatAlu 438opLat=1 439 440[system.cpu.fuPool.FUList5.opList13] 441type=OpDesc 442issueLat=1 443opClass=SimdFloatCmp 444opLat=1 445 446[system.cpu.fuPool.FUList5.opList14] 447type=OpDesc 448issueLat=1 449opClass=SimdFloatCvt 450opLat=1 451 452[system.cpu.fuPool.FUList5.opList15] 453type=OpDesc 454issueLat=1 455opClass=SimdFloatDiv 456opLat=1 457 458[system.cpu.fuPool.FUList5.opList16] 459type=OpDesc 460issueLat=1 461opClass=SimdFloatMisc 462opLat=1 463 464[system.cpu.fuPool.FUList5.opList17] 465type=OpDesc 466issueLat=1 467opClass=SimdFloatMult 468opLat=1 469 470[system.cpu.fuPool.FUList5.opList18] 471type=OpDesc 472issueLat=1 473opClass=SimdFloatMultAcc 474opLat=1 475 476[system.cpu.fuPool.FUList5.opList19] 477type=OpDesc 478issueLat=1 479opClass=SimdFloatSqrt 480opLat=1 481 482[system.cpu.fuPool.FUList6] 483type=FUDesc 484children=opList 485count=0 486opList=system.cpu.fuPool.FUList6.opList 487 488[system.cpu.fuPool.FUList6.opList] 489type=OpDesc 490issueLat=1 491opClass=MemWrite 492opLat=1 493 494[system.cpu.fuPool.FUList7] 495type=FUDesc 496children=opList0 opList1 497count=4 498opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 499 500[system.cpu.fuPool.FUList7.opList0] 501type=OpDesc 502issueLat=1 503opClass=MemRead 504opLat=1 505 506[system.cpu.fuPool.FUList7.opList1] 507type=OpDesc 508issueLat=1 509opClass=MemWrite 510opLat=1 511 512[system.cpu.fuPool.FUList8] 513type=FUDesc 514children=opList 515count=1 516opList=system.cpu.fuPool.FUList8.opList 517 518[system.cpu.fuPool.FUList8.opList] 519type=OpDesc 520issueLat=3 521opClass=IprAccess 522opLat=3 523 524[system.cpu.icache] 525type=BaseCache 526children=tags 527addr_ranges=0:18446744073709551615 528assoc=2 529clk_domain=system.cpu_clk_domain 530forward_snoops=true 531hit_latency=2 532is_top_level=true 533max_miss_count=0 534mshrs=4 535prefetch_on_access=false 536prefetcher=Null 537response_latency=2 538size=131072 539system=system 540tags=system.cpu.icache.tags 541tgts_per_mshr=20 542two_queue=false 543write_buffers=8 544cpu_side=system.cpu.icache_port 545mem_side=system.cpu.toL2Bus.slave[0] 546 547[system.cpu.icache.tags] 548type=LRU 549assoc=2 550block_size=64 551clk_domain=system.cpu_clk_domain 552hit_latency=2 553size=131072 554 555[system.cpu.interrupts] 556type=ArmInterrupts 557 558[system.cpu.isa] 559type=ArmISA 560fpsid=1090793632 561id_isar0=34607377 562id_isar1=34677009 563id_isar2=555950401 564id_isar3=17899825 565id_isar4=268501314 566id_isar5=0 567id_mmfr0=3 568id_mmfr1=0 569id_mmfr2=19070976 570id_mmfr3=4027589137 571id_pfr0=49 572id_pfr1=1 573midr=890224640 574 575[system.cpu.itb] 576type=ArmTLB 577children=walker 578size=64 579walker=system.cpu.itb.walker 580 581[system.cpu.itb.walker] 582type=ArmTableWalker 583clk_domain=system.cpu_clk_domain 584num_squash_per_cycle=2 585sys=system 586port=system.cpu.toL2Bus.slave[2] 587 588[system.cpu.l2cache] 589type=BaseCache 590children=tags 591addr_ranges=0:18446744073709551615 592assoc=8 593clk_domain=system.cpu_clk_domain 594forward_snoops=true 595hit_latency=20 596is_top_level=false 597max_miss_count=0 598mshrs=20 599prefetch_on_access=false 600prefetcher=Null 601response_latency=20 602size=2097152 603system=system 604tags=system.cpu.l2cache.tags 605tgts_per_mshr=12 606two_queue=false 607write_buffers=8 608cpu_side=system.cpu.toL2Bus.master[0] 609mem_side=system.membus.slave[1] 610 611[system.cpu.l2cache.tags] 612type=LRU 613assoc=8 614block_size=64 615clk_domain=system.cpu_clk_domain 616hit_latency=20 617size=2097152 618 619[system.cpu.toL2Bus] 620type=CoherentBus 621clk_domain=system.cpu_clk_domain 622header_cycles=1 623system=system 624use_default_range=false 625width=32 626master=system.cpu.l2cache.cpu_side 627slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 628 629[system.cpu.tracer] 630type=ExeTracer 631 632[system.cpu.workload] 633type=LiveProcess 634cmd=hello 635cwd= 636egid=100 637env= 638errout=cerr 639euid=100 640executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 641gid=100 642input=cin 643max_stack_size=67108864 644output=cout 645pid=100 646ppid=99 647simpoint=0 648system=system 649uid=100 650 651[system.cpu_clk_domain] 652type=SrcClockDomain 653clock=500 654voltage_domain=system.voltage_domain 655 656[system.membus] 657type=CoherentBus 658clk_domain=system.clk_domain 659header_cycles=1 660system=system 661use_default_range=false 662width=8 663master=system.physmem.port 664slave=system.system_port system.cpu.l2cache.mem_side 665 666[system.physmem] 667type=SimpleDRAM 668activation_limit=4 669addr_mapping=RaBaChCo 670banks_per_rank=8 671burst_length=8 672channels=1 673clk_domain=system.clk_domain 674conf_table_reported=true 675device_bus_width=8 676device_rowbuffer_size=1024 677devices_per_rank=8 678in_addr_map=true 679mem_sched_policy=frfcfs 680null=false 681page_policy=open 682range=0:134217727 683ranks_per_channel=2 684read_buffer_size=32 685static_backend_latency=10000 686static_frontend_latency=10000 687tBURST=5000 688tCL=13750 689tRCD=13750 690tREFI=7800000 691tRFC=300000 692tRP=13750 693tWTR=7500 694tXAW=40000 695write_buffer_size=32 696write_thresh_perc=70 697port=system.membus.master[0] 698 699[system.voltage_domain] 700type=VoltageDomain 701voltage=1.000000 702 703