config.ini revision 9885
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu.branchPred 50cachePorts=200 51checker=system.cpu.checker 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=false 88numIQEntries=64 89numPhysFloatRegs=256 90numPhysIntRegs=256 91numROBEntries=192 92numRobs=1 93numThreads=1 94profile=0 95progress_interval=0 96renameToDecodeDelay=1 97renameToFetchDelay=1 98renameToIEWDelay=2 99renameToROBDelay=1 100renameWidth=8 101simpoint_start_insts= 102smtCommitPolicy=RoundRobin 103smtFetchPolicy=SingleThread 104smtIQPolicy=Partitioned 105smtIQThreshold=100 106smtLSQPolicy=Partitioned 107smtLSQThreshold=100 108smtNumFetchingThreads=1 109smtROBPolicy=Partitioned 110smtROBThreshold=100 111squashWidth=8 112store_set_clear_period=250000 113switched_out=false 114system=system 115tracer=system.cpu.tracer 116trapLatency=13 117wbDepth=1 118wbWidth=8 119workload=system.cpu.workload 120dcache_port=system.cpu.dcache.cpu_side 121icache_port=system.cpu.icache.cpu_side 122 123[system.cpu.branchPred] 124type=BranchPredictor 125BTBEntries=4096 126BTBTagSize=16 127RASSize=16 128choiceCtrBits=2 129choicePredictorSize=8192 130globalCtrBits=2 131globalPredictorSize=8192 132instShiftAmt=2 133localCtrBits=2 134localHistoryTableSize=2048 135localPredictorSize=2048 136numThreads=1 137predType=tournament 138 139[system.cpu.checker] 140type=O3Checker 141children=dtb isa itb tracer 142checker=Null 143clk_domain=system.cpu_clk_domain 144cpu_id=0 145do_checkpoint_insts=true 146do_quiesce=true 147do_statistics_insts=true 148dtb=system.cpu.checker.dtb 149exitOnError=false 150function_trace=false 151function_trace_start=0 152interrupts=Null 153isa=system.cpu.checker.isa 154itb=system.cpu.checker.itb 155max_insts_all_threads=0 156max_insts_any_thread=0 157max_loads_all_threads=0 158max_loads_any_thread=0 159numThreads=1 160profile=0 161progress_interval=0 162simpoint_start_insts= 163switched_out=false 164system=system 165tracer=system.cpu.checker.tracer 166updateOnError=true 167warnOnlyOnLoadError=true 168workload=system.cpu.workload 169 170[system.cpu.checker.dtb] 171type=ArmTLB 172children=walker 173size=64 174walker=system.cpu.checker.dtb.walker 175 176[system.cpu.checker.dtb.walker] 177type=ArmTableWalker 178clk_domain=system.cpu_clk_domain 179num_squash_per_cycle=2 180sys=system 181port=system.cpu.toL2Bus.slave[5] 182 183[system.cpu.checker.isa] 184type=ArmISA 185fpsid=1090793632 186id_isar0=34607377 187id_isar1=34677009 188id_isar2=555950401 189id_isar3=17899825 190id_isar4=268501314 191id_isar5=0 192id_mmfr0=3 193id_mmfr1=0 194id_mmfr2=19070976 195id_mmfr3=4027589137 196id_pfr0=49 197id_pfr1=1 198midr=890224640 199 200[system.cpu.checker.itb] 201type=ArmTLB 202children=walker 203size=64 204walker=system.cpu.checker.itb.walker 205 206[system.cpu.checker.itb.walker] 207type=ArmTableWalker 208clk_domain=system.cpu_clk_domain 209num_squash_per_cycle=2 210sys=system 211port=system.cpu.toL2Bus.slave[4] 212 213[system.cpu.checker.tracer] 214type=ExeTracer 215 216[system.cpu.dcache] 217type=BaseCache 218children=tags 219addr_ranges=0:18446744073709551615 220assoc=2 221clk_domain=system.cpu_clk_domain 222forward_snoops=true 223hit_latency=2 224is_top_level=true 225max_miss_count=0 226mshrs=4 227prefetch_on_access=false 228prefetcher=Null 229response_latency=2 230size=262144 231system=system 232tags=system.cpu.dcache.tags 233tgts_per_mshr=20 234two_queue=false 235write_buffers=8 236cpu_side=system.cpu.dcache_port 237mem_side=system.cpu.toL2Bus.slave[1] 238 239[system.cpu.dcache.tags] 240type=LRU 241assoc=2 242block_size=64 243clk_domain=system.cpu_clk_domain 244hit_latency=2 245size=262144 246 247[system.cpu.dtb] 248type=ArmTLB 249children=walker 250size=64 251walker=system.cpu.dtb.walker 252 253[system.cpu.dtb.walker] 254type=ArmTableWalker 255clk_domain=system.cpu_clk_domain 256num_squash_per_cycle=2 257sys=system 258port=system.cpu.toL2Bus.slave[3] 259 260[system.cpu.fuPool] 261type=FUPool 262children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 263FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 264 265[system.cpu.fuPool.FUList0] 266type=FUDesc 267children=opList 268count=6 269opList=system.cpu.fuPool.FUList0.opList 270 271[system.cpu.fuPool.FUList0.opList] 272type=OpDesc 273issueLat=1 274opClass=IntAlu 275opLat=1 276 277[system.cpu.fuPool.FUList1] 278type=FUDesc 279children=opList0 opList1 280count=2 281opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 282 283[system.cpu.fuPool.FUList1.opList0] 284type=OpDesc 285issueLat=1 286opClass=IntMult 287opLat=3 288 289[system.cpu.fuPool.FUList1.opList1] 290type=OpDesc 291issueLat=19 292opClass=IntDiv 293opLat=20 294 295[system.cpu.fuPool.FUList2] 296type=FUDesc 297children=opList0 opList1 opList2 298count=4 299opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 300 301[system.cpu.fuPool.FUList2.opList0] 302type=OpDesc 303issueLat=1 304opClass=FloatAdd 305opLat=2 306 307[system.cpu.fuPool.FUList2.opList1] 308type=OpDesc 309issueLat=1 310opClass=FloatCmp 311opLat=2 312 313[system.cpu.fuPool.FUList2.opList2] 314type=OpDesc 315issueLat=1 316opClass=FloatCvt 317opLat=2 318 319[system.cpu.fuPool.FUList3] 320type=FUDesc 321children=opList0 opList1 opList2 322count=2 323opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 324 325[system.cpu.fuPool.FUList3.opList0] 326type=OpDesc 327issueLat=1 328opClass=FloatMult 329opLat=4 330 331[system.cpu.fuPool.FUList3.opList1] 332type=OpDesc 333issueLat=12 334opClass=FloatDiv 335opLat=12 336 337[system.cpu.fuPool.FUList3.opList2] 338type=OpDesc 339issueLat=24 340opClass=FloatSqrt 341opLat=24 342 343[system.cpu.fuPool.FUList4] 344type=FUDesc 345children=opList 346count=0 347opList=system.cpu.fuPool.FUList4.opList 348 349[system.cpu.fuPool.FUList4.opList] 350type=OpDesc 351issueLat=1 352opClass=MemRead 353opLat=1 354 355[system.cpu.fuPool.FUList5] 356type=FUDesc 357children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 358count=4 359opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 360 361[system.cpu.fuPool.FUList5.opList00] 362type=OpDesc 363issueLat=1 364opClass=SimdAdd 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList01] 368type=OpDesc 369issueLat=1 370opClass=SimdAddAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList02] 374type=OpDesc 375issueLat=1 376opClass=SimdAlu 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList03] 380type=OpDesc 381issueLat=1 382opClass=SimdCmp 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList04] 386type=OpDesc 387issueLat=1 388opClass=SimdCvt 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList05] 392type=OpDesc 393issueLat=1 394opClass=SimdMisc 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList06] 398type=OpDesc 399issueLat=1 400opClass=SimdMult 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList07] 404type=OpDesc 405issueLat=1 406opClass=SimdMultAcc 407opLat=1 408 409[system.cpu.fuPool.FUList5.opList08] 410type=OpDesc 411issueLat=1 412opClass=SimdShift 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList09] 416type=OpDesc 417issueLat=1 418opClass=SimdShiftAcc 419opLat=1 420 421[system.cpu.fuPool.FUList5.opList10] 422type=OpDesc 423issueLat=1 424opClass=SimdSqrt 425opLat=1 426 427[system.cpu.fuPool.FUList5.opList11] 428type=OpDesc 429issueLat=1 430opClass=SimdFloatAdd 431opLat=1 432 433[system.cpu.fuPool.FUList5.opList12] 434type=OpDesc 435issueLat=1 436opClass=SimdFloatAlu 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList13] 440type=OpDesc 441issueLat=1 442opClass=SimdFloatCmp 443opLat=1 444 445[system.cpu.fuPool.FUList5.opList14] 446type=OpDesc 447issueLat=1 448opClass=SimdFloatCvt 449opLat=1 450 451[system.cpu.fuPool.FUList5.opList15] 452type=OpDesc 453issueLat=1 454opClass=SimdFloatDiv 455opLat=1 456 457[system.cpu.fuPool.FUList5.opList16] 458type=OpDesc 459issueLat=1 460opClass=SimdFloatMisc 461opLat=1 462 463[system.cpu.fuPool.FUList5.opList17] 464type=OpDesc 465issueLat=1 466opClass=SimdFloatMult 467opLat=1 468 469[system.cpu.fuPool.FUList5.opList18] 470type=OpDesc 471issueLat=1 472opClass=SimdFloatMultAcc 473opLat=1 474 475[system.cpu.fuPool.FUList5.opList19] 476type=OpDesc 477issueLat=1 478opClass=SimdFloatSqrt 479opLat=1 480 481[system.cpu.fuPool.FUList6] 482type=FUDesc 483children=opList 484count=0 485opList=system.cpu.fuPool.FUList6.opList 486 487[system.cpu.fuPool.FUList6.opList] 488type=OpDesc 489issueLat=1 490opClass=MemWrite 491opLat=1 492 493[system.cpu.fuPool.FUList7] 494type=FUDesc 495children=opList0 opList1 496count=4 497opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 498 499[system.cpu.fuPool.FUList7.opList0] 500type=OpDesc 501issueLat=1 502opClass=MemRead 503opLat=1 504 505[system.cpu.fuPool.FUList7.opList1] 506type=OpDesc 507issueLat=1 508opClass=MemWrite 509opLat=1 510 511[system.cpu.fuPool.FUList8] 512type=FUDesc 513children=opList 514count=1 515opList=system.cpu.fuPool.FUList8.opList 516 517[system.cpu.fuPool.FUList8.opList] 518type=OpDesc 519issueLat=3 520opClass=IprAccess 521opLat=3 522 523[system.cpu.icache] 524type=BaseCache 525children=tags 526addr_ranges=0:18446744073709551615 527assoc=2 528clk_domain=system.cpu_clk_domain 529forward_snoops=true 530hit_latency=2 531is_top_level=true 532max_miss_count=0 533mshrs=4 534prefetch_on_access=false 535prefetcher=Null 536response_latency=2 537size=131072 538system=system 539tags=system.cpu.icache.tags 540tgts_per_mshr=20 541two_queue=false 542write_buffers=8 543cpu_side=system.cpu.icache_port 544mem_side=system.cpu.toL2Bus.slave[0] 545 546[system.cpu.icache.tags] 547type=LRU 548assoc=2 549block_size=64 550clk_domain=system.cpu_clk_domain 551hit_latency=2 552size=131072 553 554[system.cpu.interrupts] 555type=ArmInterrupts 556 557[system.cpu.isa] 558type=ArmISA 559fpsid=1090793632 560id_isar0=34607377 561id_isar1=34677009 562id_isar2=555950401 563id_isar3=17899825 564id_isar4=268501314 565id_isar5=0 566id_mmfr0=3 567id_mmfr1=0 568id_mmfr2=19070976 569id_mmfr3=4027589137 570id_pfr0=49 571id_pfr1=1 572midr=890224640 573 574[system.cpu.itb] 575type=ArmTLB 576children=walker 577size=64 578walker=system.cpu.itb.walker 579 580[system.cpu.itb.walker] 581type=ArmTableWalker 582clk_domain=system.cpu_clk_domain 583num_squash_per_cycle=2 584sys=system 585port=system.cpu.toL2Bus.slave[2] 586 587[system.cpu.l2cache] 588type=BaseCache 589children=tags 590addr_ranges=0:18446744073709551615 591assoc=8 592clk_domain=system.cpu_clk_domain 593forward_snoops=true 594hit_latency=20 595is_top_level=false 596max_miss_count=0 597mshrs=20 598prefetch_on_access=false 599prefetcher=Null 600response_latency=20 601size=2097152 602system=system 603tags=system.cpu.l2cache.tags 604tgts_per_mshr=12 605two_queue=false 606write_buffers=8 607cpu_side=system.cpu.toL2Bus.master[0] 608mem_side=system.membus.slave[1] 609 610[system.cpu.l2cache.tags] 611type=LRU 612assoc=8 613block_size=64 614clk_domain=system.cpu_clk_domain 615hit_latency=20 616size=2097152 617 618[system.cpu.toL2Bus] 619type=CoherentBus 620clk_domain=system.cpu_clk_domain 621header_cycles=1 622system=system 623use_default_range=false 624width=32 625master=system.cpu.l2cache.cpu_side 626slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 627 628[system.cpu.tracer] 629type=ExeTracer 630 631[system.cpu.workload] 632type=LiveProcess 633cmd=hello 634cwd= 635egid=100 636env= 637errout=cerr 638euid=100 639executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 640gid=100 641input=cin 642max_stack_size=67108864 643output=cout 644pid=100 645ppid=99 646simpoint=0 647system=system 648uid=100 649 650[system.cpu_clk_domain] 651type=SrcClockDomain 652clock=500 653voltage_domain=system.voltage_domain 654 655[system.membus] 656type=CoherentBus 657clk_domain=system.clk_domain 658header_cycles=1 659system=system 660use_default_range=false 661width=8 662master=system.physmem.port 663slave=system.system_port system.cpu.l2cache.mem_side 664 665[system.physmem] 666type=SimpleDRAM 667activation_limit=4 668addr_mapping=RaBaChCo 669banks_per_rank=8 670burst_length=8 671channels=1 672clk_domain=system.clk_domain 673conf_table_reported=true 674device_bus_width=8 675device_rowbuffer_size=1024 676devices_per_rank=8 677in_addr_map=true 678mem_sched_policy=frfcfs 679null=false 680page_policy=open 681range=0:134217727 682ranks_per_channel=2 683read_buffer_size=32 684static_backend_latency=10000 685static_frontend_latency=10000 686tBURST=5000 687tCL=13750 688tRCD=13750 689tREFI=7800000 690tRFC=300000 691tRP=13750 692tWTR=7500 693tXAW=40000 694write_buffer_size=32 695write_thresh_perc=70 696port=system.membus.master[0] 697 698[system.voltage_domain] 699type=VoltageDomain 700voltage=1.000000 701 702