config.ini revision 9055:38f1926fb599
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 28system_port=system.membus.slave[0] 29 30[system.cpu] 31type=DerivO3CPU 32children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39RASSize=16 40SQEntries=32 41SSITSize=1024 42activity=0 43backComSize=5 44cachePorts=200 45checker=system.cpu.checker 46choiceCtrBits=2 47choicePredictorSize=8192 48clock=500 49commitToDecodeDelay=1 50commitToFetchDelay=1 51commitToIEWDelay=1 52commitToRenameDelay=1 53commitWidth=8 54cpu_id=0 55decodeToFetchDelay=1 56decodeToRenameDelay=1 57decodeWidth=8 58defer_registration=false 59dispatchWidth=8 60do_checkpoint_insts=true 61do_quiesce=true 62do_statistics_insts=true 63dtb=system.cpu.dtb 64fetchToDecodeDelay=1 65fetchTrapLatency=1 66fetchWidth=8 67forwardComSize=5 68fuPool=system.cpu.fuPool 69function_trace=false 70function_trace_start=0 71globalCtrBits=2 72globalHistoryBits=13 73globalPredictorSize=8192 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78instShiftAmt=2 79interrupts=system.cpu.interrupts 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83localCtrBits=2 84localHistoryBits=11 85localHistoryTableSize=2048 86localPredictorSize=2048 87max_insts_all_threads=0 88max_insts_any_thread=0 89max_loads_all_threads=0 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 98phase=0 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.checker] 128type=O3Checker 129children=dtb itb tracer 130checker=Null 131clock=1 132cpu_id=-1 133defer_registration=false 134do_checkpoint_insts=true 135do_quiesce=true 136do_statistics_insts=true 137dtb=system.cpu.checker.dtb 138exitOnError=false 139function_trace=false 140function_trace_start=0 141interrupts=Null 142itb=system.cpu.checker.itb 143max_insts_all_threads=0 144max_insts_any_thread=0 145max_loads_all_threads=0 146max_loads_any_thread=0 147numThreads=1 148phase=0 149profile=0 150progress_interval=0 151system=system 152tracer=system.cpu.checker.tracer 153updateOnError=true 154warnOnlyOnLoadError=true 155workload=system.cpu.workload 156 157[system.cpu.checker.dtb] 158type=ArmTLB 159children=walker 160size=64 161walker=system.cpu.checker.dtb.walker 162 163[system.cpu.checker.dtb.walker] 164type=ArmTableWalker 165max_backoff=100000 166min_backoff=0 167sys=system 168port=system.cpu.toL2Bus.slave[5] 169 170[system.cpu.checker.itb] 171type=ArmTLB 172children=walker 173size=64 174walker=system.cpu.checker.itb.walker 175 176[system.cpu.checker.itb.walker] 177type=ArmTableWalker 178max_backoff=100000 179min_backoff=0 180sys=system 181port=system.cpu.toL2Bus.slave[4] 182 183[system.cpu.checker.tracer] 184type=ExeTracer 185 186[system.cpu.dcache] 187type=BaseCache 188addr_ranges=0:18446744073709551615 189assoc=2 190block_size=64 191forward_snoops=true 192hash_delay=1 193is_top_level=true 194latency=1000 195max_miss_count=0 196mshrs=10 197prefetch_on_access=false 198prefetcher=Null 199prioritizeRequests=false 200repl=Null 201size=262144 202subblock_size=0 203system=system 204tgts_per_mshr=20 205trace_addr=0 206two_queue=false 207write_buffers=8 208cpu_side=system.cpu.dcache_port 209mem_side=system.cpu.toL2Bus.slave[1] 210 211[system.cpu.dtb] 212type=ArmTLB 213children=walker 214size=64 215walker=system.cpu.dtb.walker 216 217[system.cpu.dtb.walker] 218type=ArmTableWalker 219max_backoff=100000 220min_backoff=0 221sys=system 222port=system.cpu.toL2Bus.slave[3] 223 224[system.cpu.fuPool] 225type=FUPool 226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 227FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 228 229[system.cpu.fuPool.FUList0] 230type=FUDesc 231children=opList 232count=6 233opList=system.cpu.fuPool.FUList0.opList 234 235[system.cpu.fuPool.FUList0.opList] 236type=OpDesc 237issueLat=1 238opClass=IntAlu 239opLat=1 240 241[system.cpu.fuPool.FUList1] 242type=FUDesc 243children=opList0 opList1 244count=2 245opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 246 247[system.cpu.fuPool.FUList1.opList0] 248type=OpDesc 249issueLat=1 250opClass=IntMult 251opLat=3 252 253[system.cpu.fuPool.FUList1.opList1] 254type=OpDesc 255issueLat=19 256opClass=IntDiv 257opLat=20 258 259[system.cpu.fuPool.FUList2] 260type=FUDesc 261children=opList0 opList1 opList2 262count=4 263opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 264 265[system.cpu.fuPool.FUList2.opList0] 266type=OpDesc 267issueLat=1 268opClass=FloatAdd 269opLat=2 270 271[system.cpu.fuPool.FUList2.opList1] 272type=OpDesc 273issueLat=1 274opClass=FloatCmp 275opLat=2 276 277[system.cpu.fuPool.FUList2.opList2] 278type=OpDesc 279issueLat=1 280opClass=FloatCvt 281opLat=2 282 283[system.cpu.fuPool.FUList3] 284type=FUDesc 285children=opList0 opList1 opList2 286count=2 287opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 288 289[system.cpu.fuPool.FUList3.opList0] 290type=OpDesc 291issueLat=1 292opClass=FloatMult 293opLat=4 294 295[system.cpu.fuPool.FUList3.opList1] 296type=OpDesc 297issueLat=12 298opClass=FloatDiv 299opLat=12 300 301[system.cpu.fuPool.FUList3.opList2] 302type=OpDesc 303issueLat=24 304opClass=FloatSqrt 305opLat=24 306 307[system.cpu.fuPool.FUList4] 308type=FUDesc 309children=opList 310count=0 311opList=system.cpu.fuPool.FUList4.opList 312 313[system.cpu.fuPool.FUList4.opList] 314type=OpDesc 315issueLat=1 316opClass=MemRead 317opLat=1 318 319[system.cpu.fuPool.FUList5] 320type=FUDesc 321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 322count=4 323opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 324 325[system.cpu.fuPool.FUList5.opList00] 326type=OpDesc 327issueLat=1 328opClass=SimdAdd 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList01] 332type=OpDesc 333issueLat=1 334opClass=SimdAddAcc 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList02] 338type=OpDesc 339issueLat=1 340opClass=SimdAlu 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList03] 344type=OpDesc 345issueLat=1 346opClass=SimdCmp 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList04] 350type=OpDesc 351issueLat=1 352opClass=SimdCvt 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList05] 356type=OpDesc 357issueLat=1 358opClass=SimdMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList06] 362type=OpDesc 363issueLat=1 364opClass=SimdMult 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList07] 368type=OpDesc 369issueLat=1 370opClass=SimdMultAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList08] 374type=OpDesc 375issueLat=1 376opClass=SimdShift 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList09] 380type=OpDesc 381issueLat=1 382opClass=SimdShiftAcc 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList10] 386type=OpDesc 387issueLat=1 388opClass=SimdSqrt 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList11] 392type=OpDesc 393issueLat=1 394opClass=SimdFloatAdd 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList12] 398type=OpDesc 399issueLat=1 400opClass=SimdFloatAlu 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList13] 404type=OpDesc 405issueLat=1 406opClass=SimdFloatCmp 407opLat=1 408 409[system.cpu.fuPool.FUList5.opList14] 410type=OpDesc 411issueLat=1 412opClass=SimdFloatCvt 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList15] 416type=OpDesc 417issueLat=1 418opClass=SimdFloatDiv 419opLat=1 420 421[system.cpu.fuPool.FUList5.opList16] 422type=OpDesc 423issueLat=1 424opClass=SimdFloatMisc 425opLat=1 426 427[system.cpu.fuPool.FUList5.opList17] 428type=OpDesc 429issueLat=1 430opClass=SimdFloatMult 431opLat=1 432 433[system.cpu.fuPool.FUList5.opList18] 434type=OpDesc 435issueLat=1 436opClass=SimdFloatMultAcc 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList19] 440type=OpDesc 441issueLat=1 442opClass=SimdFloatSqrt 443opLat=1 444 445[system.cpu.fuPool.FUList6] 446type=FUDesc 447children=opList 448count=0 449opList=system.cpu.fuPool.FUList6.opList 450 451[system.cpu.fuPool.FUList6.opList] 452type=OpDesc 453issueLat=1 454opClass=MemWrite 455opLat=1 456 457[system.cpu.fuPool.FUList7] 458type=FUDesc 459children=opList0 opList1 460count=4 461opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 462 463[system.cpu.fuPool.FUList7.opList0] 464type=OpDesc 465issueLat=1 466opClass=MemRead 467opLat=1 468 469[system.cpu.fuPool.FUList7.opList1] 470type=OpDesc 471issueLat=1 472opClass=MemWrite 473opLat=1 474 475[system.cpu.fuPool.FUList8] 476type=FUDesc 477children=opList 478count=1 479opList=system.cpu.fuPool.FUList8.opList 480 481[system.cpu.fuPool.FUList8.opList] 482type=OpDesc 483issueLat=3 484opClass=IprAccess 485opLat=3 486 487[system.cpu.icache] 488type=BaseCache 489addr_ranges=0:18446744073709551615 490assoc=2 491block_size=64 492forward_snoops=true 493hash_delay=1 494is_top_level=true 495latency=1000 496max_miss_count=0 497mshrs=10 498prefetch_on_access=false 499prefetcher=Null 500prioritizeRequests=false 501repl=Null 502size=131072 503subblock_size=0 504system=system 505tgts_per_mshr=20 506trace_addr=0 507two_queue=false 508write_buffers=8 509cpu_side=system.cpu.icache_port 510mem_side=system.cpu.toL2Bus.slave[0] 511 512[system.cpu.interrupts] 513type=ArmInterrupts 514 515[system.cpu.itb] 516type=ArmTLB 517children=walker 518size=64 519walker=system.cpu.itb.walker 520 521[system.cpu.itb.walker] 522type=ArmTableWalker 523max_backoff=100000 524min_backoff=0 525sys=system 526port=system.cpu.toL2Bus.slave[2] 527 528[system.cpu.l2cache] 529type=BaseCache 530addr_ranges=0:18446744073709551615 531assoc=2 532block_size=64 533forward_snoops=true 534hash_delay=1 535is_top_level=false 536latency=1000 537max_miss_count=0 538mshrs=10 539prefetch_on_access=false 540prefetcher=Null 541prioritizeRequests=false 542repl=Null 543size=2097152 544subblock_size=0 545system=system 546tgts_per_mshr=5 547trace_addr=0 548two_queue=false 549write_buffers=8 550cpu_side=system.cpu.toL2Bus.master[0] 551mem_side=system.membus.slave[1] 552 553[system.cpu.toL2Bus] 554type=CoherentBus 555block_size=64 556clock=1000 557header_cycles=1 558use_default_range=false 559width=64 560master=system.cpu.l2cache.cpu_side 561slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 562 563[system.cpu.tracer] 564type=ExeTracer 565 566[system.cpu.workload] 567type=LiveProcess 568cmd=hello 569cwd= 570egid=100 571env= 572errout=cerr 573euid=100 574executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 575gid=100 576input=cin 577max_stack_size=67108864 578output=cout 579pid=100 580ppid=99 581simpoint=0 582system=system 583uid=100 584 585[system.membus] 586type=CoherentBus 587block_size=64 588clock=1000 589header_cycles=1 590use_default_range=false 591width=64 592master=system.physmem.port[0] 593slave=system.system_port system.cpu.l2cache.mem_side 594 595[system.physmem] 596type=SimpleMemory 597conf_table_reported=false 598file= 599in_addr_map=true 600latency=30000 601latency_var=0 602null=false 603range=0:134217727 604zero=false 605port=system.membus.master[0] 606 607