config.ini revision 11570:4aac82f10951
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cachePorts=200 69checker=system.cpu.checker 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dstage2_mmu=system.cpu.dstage2_mmu 86dtb=system.cpu.dtb 87eventq_index=0 88fetchBufferSize=64 89fetchQueueSize=32 90fetchToDecodeDelay=1 91fetchTrapLatency=1 92fetchWidth=8 93forwardComSize=5 94fuPool=system.cpu.fuPool 95function_trace=false 96function_trace_start=0 97iewToCommitDelay=1 98iewToDecodeDelay=1 99iewToFetchDelay=1 100iewToRenameDelay=1 101interrupts=system.cpu.interrupts 102isa=system.cpu.isa 103issueToExecuteDelay=1 104issueWidth=8 105istage2_mmu=system.cpu.istage2_mmu 106itb=system.cpu.itb 107max_insts_all_threads=0 108max_insts_any_thread=0 109max_loads_all_threads=0 110max_loads_any_thread=0 111needsTSO=false 112numIQEntries=64 113numPhysCCRegs=1280 114numPhysFloatRegs=256 115numPhysIntRegs=256 116numROBEntries=192 117numRobs=1 118numThreads=1 119p_state_clk_gate_bins=20 120p_state_clk_gate_max=1000000000000 121p_state_clk_gate_min=1000 122power_model=Null 123profile=0 124progress_interval=0 125renameToDecodeDelay=1 126renameToFetchDelay=1 127renameToIEWDelay=2 128renameToROBDelay=1 129renameWidth=8 130simpoint_start_insts= 131smtCommitPolicy=RoundRobin 132smtFetchPolicy=SingleThread 133smtIQPolicy=Partitioned 134smtIQThreshold=100 135smtLSQPolicy=Partitioned 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false 144system=system 145tracer=system.cpu.tracer 146trapLatency=13 147wbWidth=8 148workload=system.cpu.workload 149dcache_port=system.cpu.dcache.cpu_side 150icache_port=system.cpu.icache.cpu_side 151 152[system.cpu.branchPred] 153type=TournamentBP 154BTBEntries=4096 155BTBTagSize=16 156RASSize=16 157choiceCtrBits=2 158choicePredictorSize=8192 159eventq_index=0 160globalCtrBits=2 161globalPredictorSize=8192 162indirectHashGHR=true 163indirectHashTargets=true 164indirectPathLength=3 165indirectSets=256 166indirectTagSize=16 167indirectWays=2 168instShiftAmt=2 169localCtrBits=2 170localHistoryTableSize=2048 171localPredictorSize=2048 172numThreads=1 173useIndirect=true 174 175[system.cpu.checker] 176type=O3Checker 177children=dstage2_mmu dtb isa istage2_mmu itb tracer 178checker=Null 179clk_domain=system.cpu_clk_domain 180cpu_id=0 181default_p_state=UNDEFINED 182do_checkpoint_insts=true 183do_quiesce=true 184do_statistics_insts=true 185dstage2_mmu=system.cpu.checker.dstage2_mmu 186dtb=system.cpu.checker.dtb 187eventq_index=0 188exitOnError=false 189function_trace=false 190function_trace_start=0 191interrupts= 192isa=system.cpu.checker.isa 193istage2_mmu=system.cpu.checker.istage2_mmu 194itb=system.cpu.checker.itb 195max_insts_all_threads=0 196max_insts_any_thread=0 197max_loads_all_threads=0 198max_loads_any_thread=0 199numThreads=1 200p_state_clk_gate_bins=20 201p_state_clk_gate_max=1000000000000 202p_state_clk_gate_min=1000 203power_model=Null 204profile=0 205progress_interval=0 206simpoint_start_insts= 207socket_id=0 208switched_out=false 209system=system 210tracer=system.cpu.checker.tracer 211updateOnError=true 212warnOnlyOnLoadError=true 213workload=system.cpu.workload 214 215[system.cpu.checker.dstage2_mmu] 216type=ArmStage2MMU 217children=stage2_tlb 218eventq_index=0 219stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 220sys=system 221tlb=system.cpu.checker.dtb 222 223[system.cpu.checker.dstage2_mmu.stage2_tlb] 224type=ArmTLB 225children=walker 226eventq_index=0 227is_stage2=true 228size=32 229walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 230 231[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 232type=ArmTableWalker 233clk_domain=system.cpu_clk_domain 234default_p_state=UNDEFINED 235eventq_index=0 236is_stage2=true 237num_squash_per_cycle=2 238p_state_clk_gate_bins=20 239p_state_clk_gate_max=1000000000000 240p_state_clk_gate_min=1000 241power_model=Null 242sys=system 243 244[system.cpu.checker.dtb] 245type=ArmTLB 246children=walker 247eventq_index=0 248is_stage2=false 249size=64 250walker=system.cpu.checker.dtb.walker 251 252[system.cpu.checker.dtb.walker] 253type=ArmTableWalker 254clk_domain=system.cpu_clk_domain 255default_p_state=UNDEFINED 256eventq_index=0 257is_stage2=false 258num_squash_per_cycle=2 259p_state_clk_gate_bins=20 260p_state_clk_gate_max=1000000000000 261p_state_clk_gate_min=1000 262power_model=Null 263sys=system 264port=system.cpu.toL2Bus.slave[5] 265 266[system.cpu.checker.isa] 267type=ArmISA 268decoderFlavour=Generic 269eventq_index=0 270fpsid=1090793632 271id_aa64afr0_el1=0 272id_aa64afr1_el1=0 273id_aa64dfr0_el1=1052678 274id_aa64dfr1_el1=0 275id_aa64isar0_el1=0 276id_aa64isar1_el1=0 277id_aa64mmfr0_el1=15728642 278id_aa64mmfr1_el1=0 279id_aa64pfr0_el1=17 280id_aa64pfr1_el1=0 281id_isar0=34607377 282id_isar1=34677009 283id_isar2=555950401 284id_isar3=17899825 285id_isar4=268501314 286id_isar5=0 287id_mmfr0=270536963 288id_mmfr1=0 289id_mmfr2=19070976 290id_mmfr3=34611729 291id_pfr0=49 292id_pfr1=4113 293midr=1091551472 294pmu=Null 295system=system 296 297[system.cpu.checker.istage2_mmu] 298type=ArmStage2MMU 299children=stage2_tlb 300eventq_index=0 301stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 302sys=system 303tlb=system.cpu.checker.itb 304 305[system.cpu.checker.istage2_mmu.stage2_tlb] 306type=ArmTLB 307children=walker 308eventq_index=0 309is_stage2=true 310size=32 311walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 312 313[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 314type=ArmTableWalker 315clk_domain=system.cpu_clk_domain 316default_p_state=UNDEFINED 317eventq_index=0 318is_stage2=true 319num_squash_per_cycle=2 320p_state_clk_gate_bins=20 321p_state_clk_gate_max=1000000000000 322p_state_clk_gate_min=1000 323power_model=Null 324sys=system 325 326[system.cpu.checker.itb] 327type=ArmTLB 328children=walker 329eventq_index=0 330is_stage2=false 331size=64 332walker=system.cpu.checker.itb.walker 333 334[system.cpu.checker.itb.walker] 335type=ArmTableWalker 336clk_domain=system.cpu_clk_domain 337default_p_state=UNDEFINED 338eventq_index=0 339is_stage2=false 340num_squash_per_cycle=2 341p_state_clk_gate_bins=20 342p_state_clk_gate_max=1000000000000 343p_state_clk_gate_min=1000 344power_model=Null 345sys=system 346port=system.cpu.toL2Bus.slave[4] 347 348[system.cpu.checker.tracer] 349type=ExeTracer 350eventq_index=0 351 352[system.cpu.dcache] 353type=Cache 354children=tags 355addr_ranges=0:18446744073709551615 356assoc=2 357clk_domain=system.cpu_clk_domain 358clusivity=mostly_incl 359default_p_state=UNDEFINED 360demand_mshr_reserve=1 361eventq_index=0 362hit_latency=2 363is_read_only=false 364max_miss_count=0 365mshrs=4 366p_state_clk_gate_bins=20 367p_state_clk_gate_max=1000000000000 368p_state_clk_gate_min=1000 369power_model=Null 370prefetch_on_access=false 371prefetcher=Null 372response_latency=2 373sequential_access=false 374size=262144 375system=system 376tags=system.cpu.dcache.tags 377tgts_per_mshr=20 378write_buffers=8 379writeback_clean=false 380cpu_side=system.cpu.dcache_port 381mem_side=system.cpu.toL2Bus.slave[1] 382 383[system.cpu.dcache.tags] 384type=LRU 385assoc=2 386block_size=64 387clk_domain=system.cpu_clk_domain 388default_p_state=UNDEFINED 389eventq_index=0 390hit_latency=2 391p_state_clk_gate_bins=20 392p_state_clk_gate_max=1000000000000 393p_state_clk_gate_min=1000 394power_model=Null 395sequential_access=false 396size=262144 397 398[system.cpu.dstage2_mmu] 399type=ArmStage2MMU 400children=stage2_tlb 401eventq_index=0 402stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 403sys=system 404tlb=system.cpu.dtb 405 406[system.cpu.dstage2_mmu.stage2_tlb] 407type=ArmTLB 408children=walker 409eventq_index=0 410is_stage2=true 411size=32 412walker=system.cpu.dstage2_mmu.stage2_tlb.walker 413 414[system.cpu.dstage2_mmu.stage2_tlb.walker] 415type=ArmTableWalker 416clk_domain=system.cpu_clk_domain 417default_p_state=UNDEFINED 418eventq_index=0 419is_stage2=true 420num_squash_per_cycle=2 421p_state_clk_gate_bins=20 422p_state_clk_gate_max=1000000000000 423p_state_clk_gate_min=1000 424power_model=Null 425sys=system 426 427[system.cpu.dtb] 428type=ArmTLB 429children=walker 430eventq_index=0 431is_stage2=false 432size=64 433walker=system.cpu.dtb.walker 434 435[system.cpu.dtb.walker] 436type=ArmTableWalker 437clk_domain=system.cpu_clk_domain 438default_p_state=UNDEFINED 439eventq_index=0 440is_stage2=false 441num_squash_per_cycle=2 442p_state_clk_gate_bins=20 443p_state_clk_gate_max=1000000000000 444p_state_clk_gate_min=1000 445power_model=Null 446sys=system 447port=system.cpu.toL2Bus.slave[3] 448 449[system.cpu.fuPool] 450type=FUPool 451children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 452FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 453eventq_index=0 454 455[system.cpu.fuPool.FUList0] 456type=FUDesc 457children=opList 458count=6 459eventq_index=0 460opList=system.cpu.fuPool.FUList0.opList 461 462[system.cpu.fuPool.FUList0.opList] 463type=OpDesc 464eventq_index=0 465opClass=IntAlu 466opLat=1 467pipelined=true 468 469[system.cpu.fuPool.FUList1] 470type=FUDesc 471children=opList0 opList1 472count=2 473eventq_index=0 474opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 475 476[system.cpu.fuPool.FUList1.opList0] 477type=OpDesc 478eventq_index=0 479opClass=IntMult 480opLat=3 481pipelined=true 482 483[system.cpu.fuPool.FUList1.opList1] 484type=OpDesc 485eventq_index=0 486opClass=IntDiv 487opLat=20 488pipelined=false 489 490[system.cpu.fuPool.FUList2] 491type=FUDesc 492children=opList0 opList1 opList2 493count=4 494eventq_index=0 495opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 496 497[system.cpu.fuPool.FUList2.opList0] 498type=OpDesc 499eventq_index=0 500opClass=FloatAdd 501opLat=2 502pipelined=true 503 504[system.cpu.fuPool.FUList2.opList1] 505type=OpDesc 506eventq_index=0 507opClass=FloatCmp 508opLat=2 509pipelined=true 510 511[system.cpu.fuPool.FUList2.opList2] 512type=OpDesc 513eventq_index=0 514opClass=FloatCvt 515opLat=2 516pipelined=true 517 518[system.cpu.fuPool.FUList3] 519type=FUDesc 520children=opList0 opList1 opList2 521count=2 522eventq_index=0 523opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 524 525[system.cpu.fuPool.FUList3.opList0] 526type=OpDesc 527eventq_index=0 528opClass=FloatMult 529opLat=4 530pipelined=true 531 532[system.cpu.fuPool.FUList3.opList1] 533type=OpDesc 534eventq_index=0 535opClass=FloatDiv 536opLat=12 537pipelined=false 538 539[system.cpu.fuPool.FUList3.opList2] 540type=OpDesc 541eventq_index=0 542opClass=FloatSqrt 543opLat=24 544pipelined=false 545 546[system.cpu.fuPool.FUList4] 547type=FUDesc 548children=opList 549count=0 550eventq_index=0 551opList=system.cpu.fuPool.FUList4.opList 552 553[system.cpu.fuPool.FUList4.opList] 554type=OpDesc 555eventq_index=0 556opClass=MemRead 557opLat=1 558pipelined=true 559 560[system.cpu.fuPool.FUList5] 561type=FUDesc 562children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 563count=4 564eventq_index=0 565opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 566 567[system.cpu.fuPool.FUList5.opList00] 568type=OpDesc 569eventq_index=0 570opClass=SimdAdd 571opLat=1 572pipelined=true 573 574[system.cpu.fuPool.FUList5.opList01] 575type=OpDesc 576eventq_index=0 577opClass=SimdAddAcc 578opLat=1 579pipelined=true 580 581[system.cpu.fuPool.FUList5.opList02] 582type=OpDesc 583eventq_index=0 584opClass=SimdAlu 585opLat=1 586pipelined=true 587 588[system.cpu.fuPool.FUList5.opList03] 589type=OpDesc 590eventq_index=0 591opClass=SimdCmp 592opLat=1 593pipelined=true 594 595[system.cpu.fuPool.FUList5.opList04] 596type=OpDesc 597eventq_index=0 598opClass=SimdCvt 599opLat=1 600pipelined=true 601 602[system.cpu.fuPool.FUList5.opList05] 603type=OpDesc 604eventq_index=0 605opClass=SimdMisc 606opLat=1 607pipelined=true 608 609[system.cpu.fuPool.FUList5.opList06] 610type=OpDesc 611eventq_index=0 612opClass=SimdMult 613opLat=1 614pipelined=true 615 616[system.cpu.fuPool.FUList5.opList07] 617type=OpDesc 618eventq_index=0 619opClass=SimdMultAcc 620opLat=1 621pipelined=true 622 623[system.cpu.fuPool.FUList5.opList08] 624type=OpDesc 625eventq_index=0 626opClass=SimdShift 627opLat=1 628pipelined=true 629 630[system.cpu.fuPool.FUList5.opList09] 631type=OpDesc 632eventq_index=0 633opClass=SimdShiftAcc 634opLat=1 635pipelined=true 636 637[system.cpu.fuPool.FUList5.opList10] 638type=OpDesc 639eventq_index=0 640opClass=SimdSqrt 641opLat=1 642pipelined=true 643 644[system.cpu.fuPool.FUList5.opList11] 645type=OpDesc 646eventq_index=0 647opClass=SimdFloatAdd 648opLat=1 649pipelined=true 650 651[system.cpu.fuPool.FUList5.opList12] 652type=OpDesc 653eventq_index=0 654opClass=SimdFloatAlu 655opLat=1 656pipelined=true 657 658[system.cpu.fuPool.FUList5.opList13] 659type=OpDesc 660eventq_index=0 661opClass=SimdFloatCmp 662opLat=1 663pipelined=true 664 665[system.cpu.fuPool.FUList5.opList14] 666type=OpDesc 667eventq_index=0 668opClass=SimdFloatCvt 669opLat=1 670pipelined=true 671 672[system.cpu.fuPool.FUList5.opList15] 673type=OpDesc 674eventq_index=0 675opClass=SimdFloatDiv 676opLat=1 677pipelined=true 678 679[system.cpu.fuPool.FUList5.opList16] 680type=OpDesc 681eventq_index=0 682opClass=SimdFloatMisc 683opLat=1 684pipelined=true 685 686[system.cpu.fuPool.FUList5.opList17] 687type=OpDesc 688eventq_index=0 689opClass=SimdFloatMult 690opLat=1 691pipelined=true 692 693[system.cpu.fuPool.FUList5.opList18] 694type=OpDesc 695eventq_index=0 696opClass=SimdFloatMultAcc 697opLat=1 698pipelined=true 699 700[system.cpu.fuPool.FUList5.opList19] 701type=OpDesc 702eventq_index=0 703opClass=SimdFloatSqrt 704opLat=1 705pipelined=true 706 707[system.cpu.fuPool.FUList6] 708type=FUDesc 709children=opList 710count=0 711eventq_index=0 712opList=system.cpu.fuPool.FUList6.opList 713 714[system.cpu.fuPool.FUList6.opList] 715type=OpDesc 716eventq_index=0 717opClass=MemWrite 718opLat=1 719pipelined=true 720 721[system.cpu.fuPool.FUList7] 722type=FUDesc 723children=opList0 opList1 724count=4 725eventq_index=0 726opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 727 728[system.cpu.fuPool.FUList7.opList0] 729type=OpDesc 730eventq_index=0 731opClass=MemRead 732opLat=1 733pipelined=true 734 735[system.cpu.fuPool.FUList7.opList1] 736type=OpDesc 737eventq_index=0 738opClass=MemWrite 739opLat=1 740pipelined=true 741 742[system.cpu.fuPool.FUList8] 743type=FUDesc 744children=opList 745count=1 746eventq_index=0 747opList=system.cpu.fuPool.FUList8.opList 748 749[system.cpu.fuPool.FUList8.opList] 750type=OpDesc 751eventq_index=0 752opClass=IprAccess 753opLat=3 754pipelined=false 755 756[system.cpu.icache] 757type=Cache 758children=tags 759addr_ranges=0:18446744073709551615 760assoc=2 761clk_domain=system.cpu_clk_domain 762clusivity=mostly_incl 763default_p_state=UNDEFINED 764demand_mshr_reserve=1 765eventq_index=0 766hit_latency=2 767is_read_only=true 768max_miss_count=0 769mshrs=4 770p_state_clk_gate_bins=20 771p_state_clk_gate_max=1000000000000 772p_state_clk_gate_min=1000 773power_model=Null 774prefetch_on_access=false 775prefetcher=Null 776response_latency=2 777sequential_access=false 778size=131072 779system=system 780tags=system.cpu.icache.tags 781tgts_per_mshr=20 782write_buffers=8 783writeback_clean=true 784cpu_side=system.cpu.icache_port 785mem_side=system.cpu.toL2Bus.slave[0] 786 787[system.cpu.icache.tags] 788type=LRU 789assoc=2 790block_size=64 791clk_domain=system.cpu_clk_domain 792default_p_state=UNDEFINED 793eventq_index=0 794hit_latency=2 795p_state_clk_gate_bins=20 796p_state_clk_gate_max=1000000000000 797p_state_clk_gate_min=1000 798power_model=Null 799sequential_access=false 800size=131072 801 802[system.cpu.interrupts] 803type=ArmInterrupts 804eventq_index=0 805 806[system.cpu.isa] 807type=ArmISA 808decoderFlavour=Generic 809eventq_index=0 810fpsid=1090793632 811id_aa64afr0_el1=0 812id_aa64afr1_el1=0 813id_aa64dfr0_el1=1052678 814id_aa64dfr1_el1=0 815id_aa64isar0_el1=0 816id_aa64isar1_el1=0 817id_aa64mmfr0_el1=15728642 818id_aa64mmfr1_el1=0 819id_aa64pfr0_el1=17 820id_aa64pfr1_el1=0 821id_isar0=34607377 822id_isar1=34677009 823id_isar2=555950401 824id_isar3=17899825 825id_isar4=268501314 826id_isar5=0 827id_mmfr0=270536963 828id_mmfr1=0 829id_mmfr2=19070976 830id_mmfr3=34611729 831id_pfr0=49 832id_pfr1=4113 833midr=1091551472 834pmu=Null 835system=system 836 837[system.cpu.istage2_mmu] 838type=ArmStage2MMU 839children=stage2_tlb 840eventq_index=0 841stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 842sys=system 843tlb=system.cpu.itb 844 845[system.cpu.istage2_mmu.stage2_tlb] 846type=ArmTLB 847children=walker 848eventq_index=0 849is_stage2=true 850size=32 851walker=system.cpu.istage2_mmu.stage2_tlb.walker 852 853[system.cpu.istage2_mmu.stage2_tlb.walker] 854type=ArmTableWalker 855clk_domain=system.cpu_clk_domain 856default_p_state=UNDEFINED 857eventq_index=0 858is_stage2=true 859num_squash_per_cycle=2 860p_state_clk_gate_bins=20 861p_state_clk_gate_max=1000000000000 862p_state_clk_gate_min=1000 863power_model=Null 864sys=system 865 866[system.cpu.itb] 867type=ArmTLB 868children=walker 869eventq_index=0 870is_stage2=false 871size=64 872walker=system.cpu.itb.walker 873 874[system.cpu.itb.walker] 875type=ArmTableWalker 876clk_domain=system.cpu_clk_domain 877default_p_state=UNDEFINED 878eventq_index=0 879is_stage2=false 880num_squash_per_cycle=2 881p_state_clk_gate_bins=20 882p_state_clk_gate_max=1000000000000 883p_state_clk_gate_min=1000 884power_model=Null 885sys=system 886port=system.cpu.toL2Bus.slave[2] 887 888[system.cpu.l2cache] 889type=Cache 890children=tags 891addr_ranges=0:18446744073709551615 892assoc=8 893clk_domain=system.cpu_clk_domain 894clusivity=mostly_incl 895default_p_state=UNDEFINED 896demand_mshr_reserve=1 897eventq_index=0 898hit_latency=20 899is_read_only=false 900max_miss_count=0 901mshrs=20 902p_state_clk_gate_bins=20 903p_state_clk_gate_max=1000000000000 904p_state_clk_gate_min=1000 905power_model=Null 906prefetch_on_access=false 907prefetcher=Null 908response_latency=20 909sequential_access=false 910size=2097152 911system=system 912tags=system.cpu.l2cache.tags 913tgts_per_mshr=12 914write_buffers=8 915writeback_clean=false 916cpu_side=system.cpu.toL2Bus.master[0] 917mem_side=system.membus.slave[1] 918 919[system.cpu.l2cache.tags] 920type=LRU 921assoc=8 922block_size=64 923clk_domain=system.cpu_clk_domain 924default_p_state=UNDEFINED 925eventq_index=0 926hit_latency=20 927p_state_clk_gate_bins=20 928p_state_clk_gate_max=1000000000000 929p_state_clk_gate_min=1000 930power_model=Null 931sequential_access=false 932size=2097152 933 934[system.cpu.toL2Bus] 935type=CoherentXBar 936children=snoop_filter 937clk_domain=system.cpu_clk_domain 938default_p_state=UNDEFINED 939eventq_index=0 940forward_latency=0 941frontend_latency=1 942p_state_clk_gate_bins=20 943p_state_clk_gate_max=1000000000000 944p_state_clk_gate_min=1000 945point_of_coherency=false 946power_model=Null 947response_latency=1 948snoop_filter=system.cpu.toL2Bus.snoop_filter 949snoop_response_latency=1 950system=system 951use_default_range=false 952width=32 953master=system.cpu.l2cache.cpu_side 954slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 955 956[system.cpu.toL2Bus.snoop_filter] 957type=SnoopFilter 958eventq_index=0 959lookup_latency=0 960max_capacity=8388608 961system=system 962 963[system.cpu.tracer] 964type=ExeTracer 965eventq_index=0 966 967[system.cpu.workload] 968type=LiveProcess 969cmd=hello 970cwd= 971drivers= 972egid=100 973env= 974errout=cerr 975euid=100 976eventq_index=0 977executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello 978gid=100 979input=cin 980kvmInSE=false 981max_stack_size=67108864 982output=cout 983pid=100 984ppid=99 985simpoint=0 986system=system 987uid=100 988useArchPT=false 989 990[system.cpu_clk_domain] 991type=SrcClockDomain 992clock=500 993domain_id=-1 994eventq_index=0 995init_perf_level=0 996voltage_domain=system.voltage_domain 997 998[system.dvfs_handler] 999type=DVFSHandler 1000domains= 1001enable=false 1002eventq_index=0 1003sys_clk_domain=system.clk_domain 1004transition_latency=100000000 1005 1006[system.membus] 1007type=CoherentXBar 1008clk_domain=system.clk_domain 1009default_p_state=UNDEFINED 1010eventq_index=0 1011forward_latency=4 1012frontend_latency=3 1013p_state_clk_gate_bins=20 1014p_state_clk_gate_max=1000000000000 1015p_state_clk_gate_min=1000 1016point_of_coherency=true 1017power_model=Null 1018response_latency=2 1019snoop_filter=Null 1020snoop_response_latency=4 1021system=system 1022use_default_range=false 1023width=16 1024master=system.physmem.port 1025slave=system.system_port system.cpu.l2cache.mem_side 1026 1027[system.physmem] 1028type=DRAMCtrl 1029IDD0=0.075000 1030IDD02=0.000000 1031IDD2N=0.050000 1032IDD2N2=0.000000 1033IDD2P0=0.000000 1034IDD2P02=0.000000 1035IDD2P1=0.000000 1036IDD2P12=0.000000 1037IDD3N=0.057000 1038IDD3N2=0.000000 1039IDD3P0=0.000000 1040IDD3P02=0.000000 1041IDD3P1=0.000000 1042IDD3P12=0.000000 1043IDD4R=0.187000 1044IDD4R2=0.000000 1045IDD4W=0.165000 1046IDD4W2=0.000000 1047IDD5=0.220000 1048IDD52=0.000000 1049IDD6=0.000000 1050IDD62=0.000000 1051VDD=1.500000 1052VDD2=0.000000 1053activation_limit=4 1054addr_mapping=RoRaBaCoCh 1055bank_groups_per_rank=0 1056banks_per_rank=8 1057burst_length=8 1058channels=1 1059clk_domain=system.clk_domain 1060conf_table_reported=true 1061default_p_state=UNDEFINED 1062device_bus_width=8 1063device_rowbuffer_size=1024 1064device_size=536870912 1065devices_per_rank=8 1066dll=true 1067eventq_index=0 1068in_addr_map=true 1069max_accesses_per_row=16 1070mem_sched_policy=frfcfs 1071min_writes_per_switch=16 1072null=false 1073p_state_clk_gate_bins=20 1074p_state_clk_gate_max=1000000000000 1075p_state_clk_gate_min=1000 1076page_policy=open_adaptive 1077power_model=Null 1078range=0:134217727 1079ranks_per_channel=2 1080read_buffer_size=32 1081static_backend_latency=10000 1082static_frontend_latency=10000 1083tBURST=5000 1084tCCD_L=0 1085tCK=1250 1086tCL=13750 1087tCS=2500 1088tRAS=35000 1089tRCD=13750 1090tREFI=7800000 1091tRFC=260000 1092tRP=13750 1093tRRD=6000 1094tRRD_L=0 1095tRTP=7500 1096tRTW=2500 1097tWR=15000 1098tWTR=7500 1099tXAW=30000 1100tXP=0 1101tXPDLL=0 1102tXS=0 1103tXSDLL=0 1104write_buffer_size=64 1105write_high_thresh_perc=85 1106write_low_thresh_perc=50 1107port=system.membus.master[0] 1108 1109[system.voltage_domain] 1110type=VoltageDomain 1111eventq_index=0 1112voltage=1.000000 1113 1114