config.ini revision 11440:76b5639162af
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[0] 42 43[system.clk_domain] 44type=SrcClockDomain 45clock=1000 46domain_id=-1 47eventq_index=0 48init_perf_level=0 49voltage_domain=system.voltage_domain 50 51[system.cpu] 52type=DerivO3CPU 53children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 54LFSTSize=1024 55LQEntries=32 56LSQCheckLoads=true 57LSQDepCheckShift=4 58SQEntries=32 59SSITSize=1024 60activity=0 61backComSize=5 62branchPred=system.cpu.branchPred 63cachePorts=200 64checker=system.cpu.checker 65clk_domain=system.cpu_clk_domain 66commitToDecodeDelay=1 67commitToFetchDelay=1 68commitToIEWDelay=1 69commitToRenameDelay=1 70commitWidth=8 71cpu_id=0 72decodeToFetchDelay=1 73decodeToRenameDelay=1 74decodeWidth=8 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dstage2_mmu=system.cpu.dstage2_mmu 80dtb=system.cpu.dtb 81eventq_index=0 82fetchBufferSize=64 83fetchQueueSize=32 84fetchToDecodeDelay=1 85fetchTrapLatency=1 86fetchWidth=8 87forwardComSize=5 88fuPool=system.cpu.fuPool 89function_trace=false 90function_trace_start=0 91iewToCommitDelay=1 92iewToDecodeDelay=1 93iewToFetchDelay=1 94iewToRenameDelay=1 95interrupts=system.cpu.interrupts 96isa=system.cpu.isa 97issueToExecuteDelay=1 98issueWidth=8 99istage2_mmu=system.cpu.istage2_mmu 100itb=system.cpu.itb 101max_insts_all_threads=0 102max_insts_any_thread=0 103max_loads_all_threads=0 104max_loads_any_thread=0 105needsTSO=false 106numIQEntries=64 107numPhysCCRegs=1280 108numPhysFloatRegs=256 109numPhysIntRegs=256 110numROBEntries=192 111numRobs=1 112numThreads=1 113profile=0 114progress_interval=0 115renameToDecodeDelay=1 116renameToFetchDelay=1 117renameToIEWDelay=2 118renameToROBDelay=1 119renameWidth=8 120simpoint_start_insts= 121smtCommitPolicy=RoundRobin 122smtFetchPolicy=SingleThread 123smtIQPolicy=Partitioned 124smtIQThreshold=100 125smtLSQPolicy=Partitioned 126smtLSQThreshold=100 127smtNumFetchingThreads=1 128smtROBPolicy=Partitioned 129smtROBThreshold=100 130socket_id=0 131squashWidth=8 132store_set_clear_period=250000 133switched_out=false 134system=system 135tracer=system.cpu.tracer 136trapLatency=13 137wbWidth=8 138workload=system.cpu.workload 139dcache_port=system.cpu.dcache.cpu_side 140icache_port=system.cpu.icache.cpu_side 141 142[system.cpu.branchPred] 143type=TournamentBP 144BTBEntries=4096 145BTBTagSize=16 146RASSize=16 147choiceCtrBits=2 148choicePredictorSize=8192 149eventq_index=0 150globalCtrBits=2 151globalPredictorSize=8192 152indirectHashGHR=true 153indirectHashTargets=true 154indirectPathLength=3 155indirectSets=256 156indirectTagSize=16 157indirectWays=2 158instShiftAmt=2 159localCtrBits=2 160localHistoryTableSize=2048 161localPredictorSize=2048 162numThreads=1 163useIndirect=true 164 165[system.cpu.checker] 166type=O3Checker 167children=dstage2_mmu dtb isa istage2_mmu itb tracer 168checker=Null 169clk_domain=system.cpu_clk_domain 170cpu_id=0 171do_checkpoint_insts=true 172do_quiesce=true 173do_statistics_insts=true 174dstage2_mmu=system.cpu.checker.dstage2_mmu 175dtb=system.cpu.checker.dtb 176eventq_index=0 177exitOnError=false 178function_trace=false 179function_trace_start=0 180interrupts= 181isa=system.cpu.checker.isa 182istage2_mmu=system.cpu.checker.istage2_mmu 183itb=system.cpu.checker.itb 184max_insts_all_threads=0 185max_insts_any_thread=0 186max_loads_all_threads=0 187max_loads_any_thread=0 188numThreads=1 189profile=0 190progress_interval=0 191simpoint_start_insts= 192socket_id=0 193switched_out=false 194system=system 195tracer=system.cpu.checker.tracer 196updateOnError=true 197warnOnlyOnLoadError=true 198workload=system.cpu.workload 199 200[system.cpu.checker.dstage2_mmu] 201type=ArmStage2MMU 202children=stage2_tlb 203eventq_index=0 204stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 205sys=system 206tlb=system.cpu.checker.dtb 207 208[system.cpu.checker.dstage2_mmu.stage2_tlb] 209type=ArmTLB 210children=walker 211eventq_index=0 212is_stage2=true 213size=32 214walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 215 216[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 217type=ArmTableWalker 218clk_domain=system.cpu_clk_domain 219eventq_index=0 220is_stage2=true 221num_squash_per_cycle=2 222sys=system 223 224[system.cpu.checker.dtb] 225type=ArmTLB 226children=walker 227eventq_index=0 228is_stage2=false 229size=64 230walker=system.cpu.checker.dtb.walker 231 232[system.cpu.checker.dtb.walker] 233type=ArmTableWalker 234clk_domain=system.cpu_clk_domain 235eventq_index=0 236is_stage2=false 237num_squash_per_cycle=2 238sys=system 239port=system.cpu.toL2Bus.slave[5] 240 241[system.cpu.checker.isa] 242type=ArmISA 243decoderFlavour=Generic 244eventq_index=0 245fpsid=1090793632 246id_aa64afr0_el1=0 247id_aa64afr1_el1=0 248id_aa64dfr0_el1=1052678 249id_aa64dfr1_el1=0 250id_aa64isar0_el1=0 251id_aa64isar1_el1=0 252id_aa64mmfr0_el1=15728642 253id_aa64mmfr1_el1=0 254id_aa64pfr0_el1=17 255id_aa64pfr1_el1=0 256id_isar0=34607377 257id_isar1=34677009 258id_isar2=555950401 259id_isar3=17899825 260id_isar4=268501314 261id_isar5=0 262id_mmfr0=270536963 263id_mmfr1=0 264id_mmfr2=19070976 265id_mmfr3=34611729 266id_pfr0=49 267id_pfr1=4113 268midr=1091551472 269pmu=Null 270system=system 271 272[system.cpu.checker.istage2_mmu] 273type=ArmStage2MMU 274children=stage2_tlb 275eventq_index=0 276stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 277sys=system 278tlb=system.cpu.checker.itb 279 280[system.cpu.checker.istage2_mmu.stage2_tlb] 281type=ArmTLB 282children=walker 283eventq_index=0 284is_stage2=true 285size=32 286walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 287 288[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 289type=ArmTableWalker 290clk_domain=system.cpu_clk_domain 291eventq_index=0 292is_stage2=true 293num_squash_per_cycle=2 294sys=system 295 296[system.cpu.checker.itb] 297type=ArmTLB 298children=walker 299eventq_index=0 300is_stage2=false 301size=64 302walker=system.cpu.checker.itb.walker 303 304[system.cpu.checker.itb.walker] 305type=ArmTableWalker 306clk_domain=system.cpu_clk_domain 307eventq_index=0 308is_stage2=false 309num_squash_per_cycle=2 310sys=system 311port=system.cpu.toL2Bus.slave[4] 312 313[system.cpu.checker.tracer] 314type=ExeTracer 315eventq_index=0 316 317[system.cpu.dcache] 318type=Cache 319children=tags 320addr_ranges=0:18446744073709551615 321assoc=2 322clk_domain=system.cpu_clk_domain 323clusivity=mostly_incl 324demand_mshr_reserve=1 325eventq_index=0 326hit_latency=2 327is_read_only=false 328max_miss_count=0 329mshrs=4 330prefetch_on_access=false 331prefetcher=Null 332response_latency=2 333sequential_access=false 334size=262144 335system=system 336tags=system.cpu.dcache.tags 337tgts_per_mshr=20 338write_buffers=8 339writeback_clean=false 340cpu_side=system.cpu.dcache_port 341mem_side=system.cpu.toL2Bus.slave[1] 342 343[system.cpu.dcache.tags] 344type=LRU 345assoc=2 346block_size=64 347clk_domain=system.cpu_clk_domain 348eventq_index=0 349hit_latency=2 350sequential_access=false 351size=262144 352 353[system.cpu.dstage2_mmu] 354type=ArmStage2MMU 355children=stage2_tlb 356eventq_index=0 357stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 358sys=system 359tlb=system.cpu.dtb 360 361[system.cpu.dstage2_mmu.stage2_tlb] 362type=ArmTLB 363children=walker 364eventq_index=0 365is_stage2=true 366size=32 367walker=system.cpu.dstage2_mmu.stage2_tlb.walker 368 369[system.cpu.dstage2_mmu.stage2_tlb.walker] 370type=ArmTableWalker 371clk_domain=system.cpu_clk_domain 372eventq_index=0 373is_stage2=true 374num_squash_per_cycle=2 375sys=system 376 377[system.cpu.dtb] 378type=ArmTLB 379children=walker 380eventq_index=0 381is_stage2=false 382size=64 383walker=system.cpu.dtb.walker 384 385[system.cpu.dtb.walker] 386type=ArmTableWalker 387clk_domain=system.cpu_clk_domain 388eventq_index=0 389is_stage2=false 390num_squash_per_cycle=2 391sys=system 392port=system.cpu.toL2Bus.slave[3] 393 394[system.cpu.fuPool] 395type=FUPool 396children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 397FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 398eventq_index=0 399 400[system.cpu.fuPool.FUList0] 401type=FUDesc 402children=opList 403count=6 404eventq_index=0 405opList=system.cpu.fuPool.FUList0.opList 406 407[system.cpu.fuPool.FUList0.opList] 408type=OpDesc 409eventq_index=0 410opClass=IntAlu 411opLat=1 412pipelined=true 413 414[system.cpu.fuPool.FUList1] 415type=FUDesc 416children=opList0 opList1 417count=2 418eventq_index=0 419opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 420 421[system.cpu.fuPool.FUList1.opList0] 422type=OpDesc 423eventq_index=0 424opClass=IntMult 425opLat=3 426pipelined=true 427 428[system.cpu.fuPool.FUList1.opList1] 429type=OpDesc 430eventq_index=0 431opClass=IntDiv 432opLat=20 433pipelined=false 434 435[system.cpu.fuPool.FUList2] 436type=FUDesc 437children=opList0 opList1 opList2 438count=4 439eventq_index=0 440opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 441 442[system.cpu.fuPool.FUList2.opList0] 443type=OpDesc 444eventq_index=0 445opClass=FloatAdd 446opLat=2 447pipelined=true 448 449[system.cpu.fuPool.FUList2.opList1] 450type=OpDesc 451eventq_index=0 452opClass=FloatCmp 453opLat=2 454pipelined=true 455 456[system.cpu.fuPool.FUList2.opList2] 457type=OpDesc 458eventq_index=0 459opClass=FloatCvt 460opLat=2 461pipelined=true 462 463[system.cpu.fuPool.FUList3] 464type=FUDesc 465children=opList0 opList1 opList2 466count=2 467eventq_index=0 468opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 469 470[system.cpu.fuPool.FUList3.opList0] 471type=OpDesc 472eventq_index=0 473opClass=FloatMult 474opLat=4 475pipelined=true 476 477[system.cpu.fuPool.FUList3.opList1] 478type=OpDesc 479eventq_index=0 480opClass=FloatDiv 481opLat=12 482pipelined=false 483 484[system.cpu.fuPool.FUList3.opList2] 485type=OpDesc 486eventq_index=0 487opClass=FloatSqrt 488opLat=24 489pipelined=false 490 491[system.cpu.fuPool.FUList4] 492type=FUDesc 493children=opList 494count=0 495eventq_index=0 496opList=system.cpu.fuPool.FUList4.opList 497 498[system.cpu.fuPool.FUList4.opList] 499type=OpDesc 500eventq_index=0 501opClass=MemRead 502opLat=1 503pipelined=true 504 505[system.cpu.fuPool.FUList5] 506type=FUDesc 507children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 508count=4 509eventq_index=0 510opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 511 512[system.cpu.fuPool.FUList5.opList00] 513type=OpDesc 514eventq_index=0 515opClass=SimdAdd 516opLat=1 517pipelined=true 518 519[system.cpu.fuPool.FUList5.opList01] 520type=OpDesc 521eventq_index=0 522opClass=SimdAddAcc 523opLat=1 524pipelined=true 525 526[system.cpu.fuPool.FUList5.opList02] 527type=OpDesc 528eventq_index=0 529opClass=SimdAlu 530opLat=1 531pipelined=true 532 533[system.cpu.fuPool.FUList5.opList03] 534type=OpDesc 535eventq_index=0 536opClass=SimdCmp 537opLat=1 538pipelined=true 539 540[system.cpu.fuPool.FUList5.opList04] 541type=OpDesc 542eventq_index=0 543opClass=SimdCvt 544opLat=1 545pipelined=true 546 547[system.cpu.fuPool.FUList5.opList05] 548type=OpDesc 549eventq_index=0 550opClass=SimdMisc 551opLat=1 552pipelined=true 553 554[system.cpu.fuPool.FUList5.opList06] 555type=OpDesc 556eventq_index=0 557opClass=SimdMult 558opLat=1 559pipelined=true 560 561[system.cpu.fuPool.FUList5.opList07] 562type=OpDesc 563eventq_index=0 564opClass=SimdMultAcc 565opLat=1 566pipelined=true 567 568[system.cpu.fuPool.FUList5.opList08] 569type=OpDesc 570eventq_index=0 571opClass=SimdShift 572opLat=1 573pipelined=true 574 575[system.cpu.fuPool.FUList5.opList09] 576type=OpDesc 577eventq_index=0 578opClass=SimdShiftAcc 579opLat=1 580pipelined=true 581 582[system.cpu.fuPool.FUList5.opList10] 583type=OpDesc 584eventq_index=0 585opClass=SimdSqrt 586opLat=1 587pipelined=true 588 589[system.cpu.fuPool.FUList5.opList11] 590type=OpDesc 591eventq_index=0 592opClass=SimdFloatAdd 593opLat=1 594pipelined=true 595 596[system.cpu.fuPool.FUList5.opList12] 597type=OpDesc 598eventq_index=0 599opClass=SimdFloatAlu 600opLat=1 601pipelined=true 602 603[system.cpu.fuPool.FUList5.opList13] 604type=OpDesc 605eventq_index=0 606opClass=SimdFloatCmp 607opLat=1 608pipelined=true 609 610[system.cpu.fuPool.FUList5.opList14] 611type=OpDesc 612eventq_index=0 613opClass=SimdFloatCvt 614opLat=1 615pipelined=true 616 617[system.cpu.fuPool.FUList5.opList15] 618type=OpDesc 619eventq_index=0 620opClass=SimdFloatDiv 621opLat=1 622pipelined=true 623 624[system.cpu.fuPool.FUList5.opList16] 625type=OpDesc 626eventq_index=0 627opClass=SimdFloatMisc 628opLat=1 629pipelined=true 630 631[system.cpu.fuPool.FUList5.opList17] 632type=OpDesc 633eventq_index=0 634opClass=SimdFloatMult 635opLat=1 636pipelined=true 637 638[system.cpu.fuPool.FUList5.opList18] 639type=OpDesc 640eventq_index=0 641opClass=SimdFloatMultAcc 642opLat=1 643pipelined=true 644 645[system.cpu.fuPool.FUList5.opList19] 646type=OpDesc 647eventq_index=0 648opClass=SimdFloatSqrt 649opLat=1 650pipelined=true 651 652[system.cpu.fuPool.FUList6] 653type=FUDesc 654children=opList 655count=0 656eventq_index=0 657opList=system.cpu.fuPool.FUList6.opList 658 659[system.cpu.fuPool.FUList6.opList] 660type=OpDesc 661eventq_index=0 662opClass=MemWrite 663opLat=1 664pipelined=true 665 666[system.cpu.fuPool.FUList7] 667type=FUDesc 668children=opList0 opList1 669count=4 670eventq_index=0 671opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 672 673[system.cpu.fuPool.FUList7.opList0] 674type=OpDesc 675eventq_index=0 676opClass=MemRead 677opLat=1 678pipelined=true 679 680[system.cpu.fuPool.FUList7.opList1] 681type=OpDesc 682eventq_index=0 683opClass=MemWrite 684opLat=1 685pipelined=true 686 687[system.cpu.fuPool.FUList8] 688type=FUDesc 689children=opList 690count=1 691eventq_index=0 692opList=system.cpu.fuPool.FUList8.opList 693 694[system.cpu.fuPool.FUList8.opList] 695type=OpDesc 696eventq_index=0 697opClass=IprAccess 698opLat=3 699pipelined=false 700 701[system.cpu.icache] 702type=Cache 703children=tags 704addr_ranges=0:18446744073709551615 705assoc=2 706clk_domain=system.cpu_clk_domain 707clusivity=mostly_incl 708demand_mshr_reserve=1 709eventq_index=0 710hit_latency=2 711is_read_only=true 712max_miss_count=0 713mshrs=4 714prefetch_on_access=false 715prefetcher=Null 716response_latency=2 717sequential_access=false 718size=131072 719system=system 720tags=system.cpu.icache.tags 721tgts_per_mshr=20 722write_buffers=8 723writeback_clean=true 724cpu_side=system.cpu.icache_port 725mem_side=system.cpu.toL2Bus.slave[0] 726 727[system.cpu.icache.tags] 728type=LRU 729assoc=2 730block_size=64 731clk_domain=system.cpu_clk_domain 732eventq_index=0 733hit_latency=2 734sequential_access=false 735size=131072 736 737[system.cpu.interrupts] 738type=ArmInterrupts 739eventq_index=0 740 741[system.cpu.isa] 742type=ArmISA 743decoderFlavour=Generic 744eventq_index=0 745fpsid=1090793632 746id_aa64afr0_el1=0 747id_aa64afr1_el1=0 748id_aa64dfr0_el1=1052678 749id_aa64dfr1_el1=0 750id_aa64isar0_el1=0 751id_aa64isar1_el1=0 752id_aa64mmfr0_el1=15728642 753id_aa64mmfr1_el1=0 754id_aa64pfr0_el1=17 755id_aa64pfr1_el1=0 756id_isar0=34607377 757id_isar1=34677009 758id_isar2=555950401 759id_isar3=17899825 760id_isar4=268501314 761id_isar5=0 762id_mmfr0=270536963 763id_mmfr1=0 764id_mmfr2=19070976 765id_mmfr3=34611729 766id_pfr0=49 767id_pfr1=4113 768midr=1091551472 769pmu=Null 770system=system 771 772[system.cpu.istage2_mmu] 773type=ArmStage2MMU 774children=stage2_tlb 775eventq_index=0 776stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 777sys=system 778tlb=system.cpu.itb 779 780[system.cpu.istage2_mmu.stage2_tlb] 781type=ArmTLB 782children=walker 783eventq_index=0 784is_stage2=true 785size=32 786walker=system.cpu.istage2_mmu.stage2_tlb.walker 787 788[system.cpu.istage2_mmu.stage2_tlb.walker] 789type=ArmTableWalker 790clk_domain=system.cpu_clk_domain 791eventq_index=0 792is_stage2=true 793num_squash_per_cycle=2 794sys=system 795 796[system.cpu.itb] 797type=ArmTLB 798children=walker 799eventq_index=0 800is_stage2=false 801size=64 802walker=system.cpu.itb.walker 803 804[system.cpu.itb.walker] 805type=ArmTableWalker 806clk_domain=system.cpu_clk_domain 807eventq_index=0 808is_stage2=false 809num_squash_per_cycle=2 810sys=system 811port=system.cpu.toL2Bus.slave[2] 812 813[system.cpu.l2cache] 814type=Cache 815children=tags 816addr_ranges=0:18446744073709551615 817assoc=8 818clk_domain=system.cpu_clk_domain 819clusivity=mostly_incl 820demand_mshr_reserve=1 821eventq_index=0 822hit_latency=20 823is_read_only=false 824max_miss_count=0 825mshrs=20 826prefetch_on_access=false 827prefetcher=Null 828response_latency=20 829sequential_access=false 830size=2097152 831system=system 832tags=system.cpu.l2cache.tags 833tgts_per_mshr=12 834write_buffers=8 835writeback_clean=false 836cpu_side=system.cpu.toL2Bus.master[0] 837mem_side=system.membus.slave[1] 838 839[system.cpu.l2cache.tags] 840type=LRU 841assoc=8 842block_size=64 843clk_domain=system.cpu_clk_domain 844eventq_index=0 845hit_latency=20 846sequential_access=false 847size=2097152 848 849[system.cpu.toL2Bus] 850type=CoherentXBar 851children=snoop_filter 852clk_domain=system.cpu_clk_domain 853eventq_index=0 854forward_latency=0 855frontend_latency=1 856point_of_coherency=false 857response_latency=1 858snoop_filter=system.cpu.toL2Bus.snoop_filter 859snoop_response_latency=1 860system=system 861use_default_range=false 862width=32 863master=system.cpu.l2cache.cpu_side 864slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 865 866[system.cpu.toL2Bus.snoop_filter] 867type=SnoopFilter 868eventq_index=0 869lookup_latency=0 870max_capacity=8388608 871system=system 872 873[system.cpu.tracer] 874type=ExeTracer 875eventq_index=0 876 877[system.cpu.workload] 878type=LiveProcess 879cmd=hello 880cwd= 881drivers= 882egid=100 883env= 884errout=cerr 885euid=100 886eventq_index=0 887executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello 888gid=100 889input=cin 890kvmInSE=false 891max_stack_size=67108864 892output=cout 893pid=100 894ppid=99 895simpoint=0 896system=system 897uid=100 898useArchPT=false 899 900[system.cpu_clk_domain] 901type=SrcClockDomain 902clock=500 903domain_id=-1 904eventq_index=0 905init_perf_level=0 906voltage_domain=system.voltage_domain 907 908[system.dvfs_handler] 909type=DVFSHandler 910domains= 911enable=false 912eventq_index=0 913sys_clk_domain=system.clk_domain 914transition_latency=100000000 915 916[system.membus] 917type=CoherentXBar 918clk_domain=system.clk_domain 919eventq_index=0 920forward_latency=4 921frontend_latency=3 922point_of_coherency=true 923response_latency=2 924snoop_filter=Null 925snoop_response_latency=4 926system=system 927use_default_range=false 928width=16 929master=system.physmem.port 930slave=system.system_port system.cpu.l2cache.mem_side 931 932[system.physmem] 933type=DRAMCtrl 934IDD0=0.075000 935IDD02=0.000000 936IDD2N=0.050000 937IDD2N2=0.000000 938IDD2P0=0.000000 939IDD2P02=0.000000 940IDD2P1=0.000000 941IDD2P12=0.000000 942IDD3N=0.057000 943IDD3N2=0.000000 944IDD3P0=0.000000 945IDD3P02=0.000000 946IDD3P1=0.000000 947IDD3P12=0.000000 948IDD4R=0.187000 949IDD4R2=0.000000 950IDD4W=0.165000 951IDD4W2=0.000000 952IDD5=0.220000 953IDD52=0.000000 954IDD6=0.000000 955IDD62=0.000000 956VDD=1.500000 957VDD2=0.000000 958activation_limit=4 959addr_mapping=RoRaBaCoCh 960bank_groups_per_rank=0 961banks_per_rank=8 962burst_length=8 963channels=1 964clk_domain=system.clk_domain 965conf_table_reported=true 966device_bus_width=8 967device_rowbuffer_size=1024 968device_size=536870912 969devices_per_rank=8 970dll=true 971eventq_index=0 972in_addr_map=true 973max_accesses_per_row=16 974mem_sched_policy=frfcfs 975min_writes_per_switch=16 976null=false 977page_policy=open_adaptive 978range=0:134217727 979ranks_per_channel=2 980read_buffer_size=32 981static_backend_latency=10000 982static_frontend_latency=10000 983tBURST=5000 984tCCD_L=0 985tCK=1250 986tCL=13750 987tCS=2500 988tRAS=35000 989tRCD=13750 990tREFI=7800000 991tRFC=260000 992tRP=13750 993tRRD=6000 994tRRD_L=0 995tRTP=7500 996tRTW=2500 997tWR=15000 998tWTR=7500 999tXAW=30000 1000tXP=0 1001tXPDLL=0 1002tXS=0 1003tXSDLL=0 1004write_buffer_size=64 1005write_high_thresh_perc=85 1006write_low_thresh_perc=50 1007port=system.membus.master[0] 1008 1009[system.voltage_domain] 1010type=VoltageDomain 1011eventq_index=0 1012voltage=1.000000 1013 1014