config.ini revision 11384
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=DerivO3CPU 51children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu.branchPred 61cachePorts=200 62checker=system.cpu.checker 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=1 72decodeWidth=8 73dispatchWidth=8 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dstage2_mmu=system.cpu.dstage2_mmu 78dtb=system.cpu.dtb 79eventq_index=0 80fetchBufferSize=64 81fetchQueueSize=32 82fetchToDecodeDelay=1 83fetchTrapLatency=1 84fetchWidth=8 85forwardComSize=5 86fuPool=system.cpu.fuPool 87function_trace=false 88function_trace_start=0 89iewToCommitDelay=1 90iewToDecodeDelay=1 91iewToFetchDelay=1 92iewToRenameDelay=1 93interrupts=system.cpu.interrupts 94isa=system.cpu.isa 95issueToExecuteDelay=1 96issueWidth=8 97istage2_mmu=system.cpu.istage2_mmu 98itb=system.cpu.itb 99max_insts_all_threads=0 100max_insts_any_thread=0 101max_loads_all_threads=0 102max_loads_any_thread=0 103needsTSO=false 104numIQEntries=64 105numPhysCCRegs=1280 106numPhysFloatRegs=256 107numPhysIntRegs=256 108numROBEntries=192 109numRobs=1 110numThreads=1 111profile=0 112progress_interval=0 113renameToDecodeDelay=1 114renameToFetchDelay=1 115renameToIEWDelay=2 116renameToROBDelay=1 117renameWidth=8 118simpoint_start_insts= 119smtCommitPolicy=RoundRobin 120smtFetchPolicy=SingleThread 121smtIQPolicy=Partitioned 122smtIQThreshold=100 123smtLSQPolicy=Partitioned 124smtLSQThreshold=100 125smtNumFetchingThreads=1 126smtROBPolicy=Partitioned 127smtROBThreshold=100 128socket_id=0 129squashWidth=8 130store_set_clear_period=250000 131switched_out=false 132system=system 133tracer=system.cpu.tracer 134trapLatency=13 135wbWidth=8 136workload=system.cpu.workload 137dcache_port=system.cpu.dcache.cpu_side 138icache_port=system.cpu.icache.cpu_side 139 140[system.cpu.branchPred] 141type=TournamentBP 142BTBEntries=4096 143BTBTagSize=16 144RASSize=16 145choiceCtrBits=2 146choicePredictorSize=8192 147eventq_index=0 148globalCtrBits=2 149globalPredictorSize=8192 150instShiftAmt=2 151localCtrBits=2 152localHistoryTableSize=2048 153localPredictorSize=2048 154numThreads=1 155 156[system.cpu.checker] 157type=O3Checker 158children=dstage2_mmu dtb isa istage2_mmu itb tracer 159checker=Null 160clk_domain=system.cpu_clk_domain 161cpu_id=0 162do_checkpoint_insts=true 163do_quiesce=true 164do_statistics_insts=true 165dstage2_mmu=system.cpu.checker.dstage2_mmu 166dtb=system.cpu.checker.dtb 167eventq_index=0 168exitOnError=false 169function_trace=false 170function_trace_start=0 171interrupts= 172isa=system.cpu.checker.isa 173istage2_mmu=system.cpu.checker.istage2_mmu 174itb=system.cpu.checker.itb 175max_insts_all_threads=0 176max_insts_any_thread=0 177max_loads_all_threads=0 178max_loads_any_thread=0 179numThreads=1 180profile=0 181progress_interval=0 182simpoint_start_insts= 183socket_id=0 184switched_out=false 185system=system 186tracer=system.cpu.checker.tracer 187updateOnError=true 188warnOnlyOnLoadError=true 189workload=system.cpu.workload 190 191[system.cpu.checker.dstage2_mmu] 192type=ArmStage2MMU 193children=stage2_tlb 194eventq_index=0 195stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 196sys=system 197tlb=system.cpu.checker.dtb 198 199[system.cpu.checker.dstage2_mmu.stage2_tlb] 200type=ArmTLB 201children=walker 202eventq_index=0 203is_stage2=true 204size=32 205walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 206 207[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 208type=ArmTableWalker 209clk_domain=system.cpu_clk_domain 210eventq_index=0 211is_stage2=true 212num_squash_per_cycle=2 213sys=system 214 215[system.cpu.checker.dtb] 216type=ArmTLB 217children=walker 218eventq_index=0 219is_stage2=false 220size=64 221walker=system.cpu.checker.dtb.walker 222 223[system.cpu.checker.dtb.walker] 224type=ArmTableWalker 225clk_domain=system.cpu_clk_domain 226eventq_index=0 227is_stage2=false 228num_squash_per_cycle=2 229sys=system 230port=system.cpu.toL2Bus.slave[5] 231 232[system.cpu.checker.isa] 233type=ArmISA 234decoderFlavour=Generic 235eventq_index=0 236fpsid=1090793632 237id_aa64afr0_el1=0 238id_aa64afr1_el1=0 239id_aa64dfr0_el1=1052678 240id_aa64dfr1_el1=0 241id_aa64isar0_el1=0 242id_aa64isar1_el1=0 243id_aa64mmfr0_el1=15728642 244id_aa64mmfr1_el1=0 245id_aa64pfr0_el1=17 246id_aa64pfr1_el1=0 247id_isar0=34607377 248id_isar1=34677009 249id_isar2=555950401 250id_isar3=17899825 251id_isar4=268501314 252id_isar5=0 253id_mmfr0=270536963 254id_mmfr1=0 255id_mmfr2=19070976 256id_mmfr3=34611729 257id_pfr0=49 258id_pfr1=4113 259midr=1091551472 260pmu=Null 261system=system 262 263[system.cpu.checker.istage2_mmu] 264type=ArmStage2MMU 265children=stage2_tlb 266eventq_index=0 267stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 268sys=system 269tlb=system.cpu.checker.itb 270 271[system.cpu.checker.istage2_mmu.stage2_tlb] 272type=ArmTLB 273children=walker 274eventq_index=0 275is_stage2=true 276size=32 277walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 278 279[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 280type=ArmTableWalker 281clk_domain=system.cpu_clk_domain 282eventq_index=0 283is_stage2=true 284num_squash_per_cycle=2 285sys=system 286 287[system.cpu.checker.itb] 288type=ArmTLB 289children=walker 290eventq_index=0 291is_stage2=false 292size=64 293walker=system.cpu.checker.itb.walker 294 295[system.cpu.checker.itb.walker] 296type=ArmTableWalker 297clk_domain=system.cpu_clk_domain 298eventq_index=0 299is_stage2=false 300num_squash_per_cycle=2 301sys=system 302port=system.cpu.toL2Bus.slave[4] 303 304[system.cpu.checker.tracer] 305type=ExeTracer 306eventq_index=0 307 308[system.cpu.dcache] 309type=Cache 310children=tags 311addr_ranges=0:18446744073709551615 312assoc=2 313clk_domain=system.cpu_clk_domain 314clusivity=mostly_incl 315demand_mshr_reserve=1 316eventq_index=0 317hit_latency=2 318is_read_only=false 319max_miss_count=0 320mshrs=4 321prefetch_on_access=false 322prefetcher=Null 323response_latency=2 324sequential_access=false 325size=262144 326system=system 327tags=system.cpu.dcache.tags 328tgts_per_mshr=20 329write_buffers=8 330writeback_clean=false 331cpu_side=system.cpu.dcache_port 332mem_side=system.cpu.toL2Bus.slave[1] 333 334[system.cpu.dcache.tags] 335type=LRU 336assoc=2 337block_size=64 338clk_domain=system.cpu_clk_domain 339eventq_index=0 340hit_latency=2 341sequential_access=false 342size=262144 343 344[system.cpu.dstage2_mmu] 345type=ArmStage2MMU 346children=stage2_tlb 347eventq_index=0 348stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 349sys=system 350tlb=system.cpu.dtb 351 352[system.cpu.dstage2_mmu.stage2_tlb] 353type=ArmTLB 354children=walker 355eventq_index=0 356is_stage2=true 357size=32 358walker=system.cpu.dstage2_mmu.stage2_tlb.walker 359 360[system.cpu.dstage2_mmu.stage2_tlb.walker] 361type=ArmTableWalker 362clk_domain=system.cpu_clk_domain 363eventq_index=0 364is_stage2=true 365num_squash_per_cycle=2 366sys=system 367 368[system.cpu.dtb] 369type=ArmTLB 370children=walker 371eventq_index=0 372is_stage2=false 373size=64 374walker=system.cpu.dtb.walker 375 376[system.cpu.dtb.walker] 377type=ArmTableWalker 378clk_domain=system.cpu_clk_domain 379eventq_index=0 380is_stage2=false 381num_squash_per_cycle=2 382sys=system 383port=system.cpu.toL2Bus.slave[3] 384 385[system.cpu.fuPool] 386type=FUPool 387children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 388FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 389eventq_index=0 390 391[system.cpu.fuPool.FUList0] 392type=FUDesc 393children=opList 394count=6 395eventq_index=0 396opList=system.cpu.fuPool.FUList0.opList 397 398[system.cpu.fuPool.FUList0.opList] 399type=OpDesc 400eventq_index=0 401opClass=IntAlu 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList1] 406type=FUDesc 407children=opList0 opList1 408count=2 409eventq_index=0 410opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 411 412[system.cpu.fuPool.FUList1.opList0] 413type=OpDesc 414eventq_index=0 415opClass=IntMult 416opLat=3 417pipelined=true 418 419[system.cpu.fuPool.FUList1.opList1] 420type=OpDesc 421eventq_index=0 422opClass=IntDiv 423opLat=20 424pipelined=false 425 426[system.cpu.fuPool.FUList2] 427type=FUDesc 428children=opList0 opList1 opList2 429count=4 430eventq_index=0 431opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 432 433[system.cpu.fuPool.FUList2.opList0] 434type=OpDesc 435eventq_index=0 436opClass=FloatAdd 437opLat=2 438pipelined=true 439 440[system.cpu.fuPool.FUList2.opList1] 441type=OpDesc 442eventq_index=0 443opClass=FloatCmp 444opLat=2 445pipelined=true 446 447[system.cpu.fuPool.FUList2.opList2] 448type=OpDesc 449eventq_index=0 450opClass=FloatCvt 451opLat=2 452pipelined=true 453 454[system.cpu.fuPool.FUList3] 455type=FUDesc 456children=opList0 opList1 opList2 457count=2 458eventq_index=0 459opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 460 461[system.cpu.fuPool.FUList3.opList0] 462type=OpDesc 463eventq_index=0 464opClass=FloatMult 465opLat=4 466pipelined=true 467 468[system.cpu.fuPool.FUList3.opList1] 469type=OpDesc 470eventq_index=0 471opClass=FloatDiv 472opLat=12 473pipelined=false 474 475[system.cpu.fuPool.FUList3.opList2] 476type=OpDesc 477eventq_index=0 478opClass=FloatSqrt 479opLat=24 480pipelined=false 481 482[system.cpu.fuPool.FUList4] 483type=FUDesc 484children=opList 485count=0 486eventq_index=0 487opList=system.cpu.fuPool.FUList4.opList 488 489[system.cpu.fuPool.FUList4.opList] 490type=OpDesc 491eventq_index=0 492opClass=MemRead 493opLat=1 494pipelined=true 495 496[system.cpu.fuPool.FUList5] 497type=FUDesc 498children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 499count=4 500eventq_index=0 501opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 502 503[system.cpu.fuPool.FUList5.opList00] 504type=OpDesc 505eventq_index=0 506opClass=SimdAdd 507opLat=1 508pipelined=true 509 510[system.cpu.fuPool.FUList5.opList01] 511type=OpDesc 512eventq_index=0 513opClass=SimdAddAcc 514opLat=1 515pipelined=true 516 517[system.cpu.fuPool.FUList5.opList02] 518type=OpDesc 519eventq_index=0 520opClass=SimdAlu 521opLat=1 522pipelined=true 523 524[system.cpu.fuPool.FUList5.opList03] 525type=OpDesc 526eventq_index=0 527opClass=SimdCmp 528opLat=1 529pipelined=true 530 531[system.cpu.fuPool.FUList5.opList04] 532type=OpDesc 533eventq_index=0 534opClass=SimdCvt 535opLat=1 536pipelined=true 537 538[system.cpu.fuPool.FUList5.opList05] 539type=OpDesc 540eventq_index=0 541opClass=SimdMisc 542opLat=1 543pipelined=true 544 545[system.cpu.fuPool.FUList5.opList06] 546type=OpDesc 547eventq_index=0 548opClass=SimdMult 549opLat=1 550pipelined=true 551 552[system.cpu.fuPool.FUList5.opList07] 553type=OpDesc 554eventq_index=0 555opClass=SimdMultAcc 556opLat=1 557pipelined=true 558 559[system.cpu.fuPool.FUList5.opList08] 560type=OpDesc 561eventq_index=0 562opClass=SimdShift 563opLat=1 564pipelined=true 565 566[system.cpu.fuPool.FUList5.opList09] 567type=OpDesc 568eventq_index=0 569opClass=SimdShiftAcc 570opLat=1 571pipelined=true 572 573[system.cpu.fuPool.FUList5.opList10] 574type=OpDesc 575eventq_index=0 576opClass=SimdSqrt 577opLat=1 578pipelined=true 579 580[system.cpu.fuPool.FUList5.opList11] 581type=OpDesc 582eventq_index=0 583opClass=SimdFloatAdd 584opLat=1 585pipelined=true 586 587[system.cpu.fuPool.FUList5.opList12] 588type=OpDesc 589eventq_index=0 590opClass=SimdFloatAlu 591opLat=1 592pipelined=true 593 594[system.cpu.fuPool.FUList5.opList13] 595type=OpDesc 596eventq_index=0 597opClass=SimdFloatCmp 598opLat=1 599pipelined=true 600 601[system.cpu.fuPool.FUList5.opList14] 602type=OpDesc 603eventq_index=0 604opClass=SimdFloatCvt 605opLat=1 606pipelined=true 607 608[system.cpu.fuPool.FUList5.opList15] 609type=OpDesc 610eventq_index=0 611opClass=SimdFloatDiv 612opLat=1 613pipelined=true 614 615[system.cpu.fuPool.FUList5.opList16] 616type=OpDesc 617eventq_index=0 618opClass=SimdFloatMisc 619opLat=1 620pipelined=true 621 622[system.cpu.fuPool.FUList5.opList17] 623type=OpDesc 624eventq_index=0 625opClass=SimdFloatMult 626opLat=1 627pipelined=true 628 629[system.cpu.fuPool.FUList5.opList18] 630type=OpDesc 631eventq_index=0 632opClass=SimdFloatMultAcc 633opLat=1 634pipelined=true 635 636[system.cpu.fuPool.FUList5.opList19] 637type=OpDesc 638eventq_index=0 639opClass=SimdFloatSqrt 640opLat=1 641pipelined=true 642 643[system.cpu.fuPool.FUList6] 644type=FUDesc 645children=opList 646count=0 647eventq_index=0 648opList=system.cpu.fuPool.FUList6.opList 649 650[system.cpu.fuPool.FUList6.opList] 651type=OpDesc 652eventq_index=0 653opClass=MemWrite 654opLat=1 655pipelined=true 656 657[system.cpu.fuPool.FUList7] 658type=FUDesc 659children=opList0 opList1 660count=4 661eventq_index=0 662opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 663 664[system.cpu.fuPool.FUList7.opList0] 665type=OpDesc 666eventq_index=0 667opClass=MemRead 668opLat=1 669pipelined=true 670 671[system.cpu.fuPool.FUList7.opList1] 672type=OpDesc 673eventq_index=0 674opClass=MemWrite 675opLat=1 676pipelined=true 677 678[system.cpu.fuPool.FUList8] 679type=FUDesc 680children=opList 681count=1 682eventq_index=0 683opList=system.cpu.fuPool.FUList8.opList 684 685[system.cpu.fuPool.FUList8.opList] 686type=OpDesc 687eventq_index=0 688opClass=IprAccess 689opLat=3 690pipelined=false 691 692[system.cpu.icache] 693type=Cache 694children=tags 695addr_ranges=0:18446744073709551615 696assoc=2 697clk_domain=system.cpu_clk_domain 698clusivity=mostly_incl 699demand_mshr_reserve=1 700eventq_index=0 701hit_latency=2 702is_read_only=true 703max_miss_count=0 704mshrs=4 705prefetch_on_access=false 706prefetcher=Null 707response_latency=2 708sequential_access=false 709size=131072 710system=system 711tags=system.cpu.icache.tags 712tgts_per_mshr=20 713write_buffers=8 714writeback_clean=true 715cpu_side=system.cpu.icache_port 716mem_side=system.cpu.toL2Bus.slave[0] 717 718[system.cpu.icache.tags] 719type=LRU 720assoc=2 721block_size=64 722clk_domain=system.cpu_clk_domain 723eventq_index=0 724hit_latency=2 725sequential_access=false 726size=131072 727 728[system.cpu.interrupts] 729type=ArmInterrupts 730eventq_index=0 731 732[system.cpu.isa] 733type=ArmISA 734decoderFlavour=Generic 735eventq_index=0 736fpsid=1090793632 737id_aa64afr0_el1=0 738id_aa64afr1_el1=0 739id_aa64dfr0_el1=1052678 740id_aa64dfr1_el1=0 741id_aa64isar0_el1=0 742id_aa64isar1_el1=0 743id_aa64mmfr0_el1=15728642 744id_aa64mmfr1_el1=0 745id_aa64pfr0_el1=17 746id_aa64pfr1_el1=0 747id_isar0=34607377 748id_isar1=34677009 749id_isar2=555950401 750id_isar3=17899825 751id_isar4=268501314 752id_isar5=0 753id_mmfr0=270536963 754id_mmfr1=0 755id_mmfr2=19070976 756id_mmfr3=34611729 757id_pfr0=49 758id_pfr1=4113 759midr=1091551472 760pmu=Null 761system=system 762 763[system.cpu.istage2_mmu] 764type=ArmStage2MMU 765children=stage2_tlb 766eventq_index=0 767stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 768sys=system 769tlb=system.cpu.itb 770 771[system.cpu.istage2_mmu.stage2_tlb] 772type=ArmTLB 773children=walker 774eventq_index=0 775is_stage2=true 776size=32 777walker=system.cpu.istage2_mmu.stage2_tlb.walker 778 779[system.cpu.istage2_mmu.stage2_tlb.walker] 780type=ArmTableWalker 781clk_domain=system.cpu_clk_domain 782eventq_index=0 783is_stage2=true 784num_squash_per_cycle=2 785sys=system 786 787[system.cpu.itb] 788type=ArmTLB 789children=walker 790eventq_index=0 791is_stage2=false 792size=64 793walker=system.cpu.itb.walker 794 795[system.cpu.itb.walker] 796type=ArmTableWalker 797clk_domain=system.cpu_clk_domain 798eventq_index=0 799is_stage2=false 800num_squash_per_cycle=2 801sys=system 802port=system.cpu.toL2Bus.slave[2] 803 804[system.cpu.l2cache] 805type=Cache 806children=tags 807addr_ranges=0:18446744073709551615 808assoc=8 809clk_domain=system.cpu_clk_domain 810clusivity=mostly_incl 811demand_mshr_reserve=1 812eventq_index=0 813hit_latency=20 814is_read_only=false 815max_miss_count=0 816mshrs=20 817prefetch_on_access=false 818prefetcher=Null 819response_latency=20 820sequential_access=false 821size=2097152 822system=system 823tags=system.cpu.l2cache.tags 824tgts_per_mshr=12 825write_buffers=8 826writeback_clean=false 827cpu_side=system.cpu.toL2Bus.master[0] 828mem_side=system.membus.slave[1] 829 830[system.cpu.l2cache.tags] 831type=LRU 832assoc=8 833block_size=64 834clk_domain=system.cpu_clk_domain 835eventq_index=0 836hit_latency=20 837sequential_access=false 838size=2097152 839 840[system.cpu.toL2Bus] 841type=CoherentXBar 842children=snoop_filter 843clk_domain=system.cpu_clk_domain 844eventq_index=0 845forward_latency=0 846frontend_latency=1 847point_of_coherency=false 848response_latency=1 849snoop_filter=system.cpu.toL2Bus.snoop_filter 850snoop_response_latency=1 851system=system 852use_default_range=false 853width=32 854master=system.cpu.l2cache.cpu_side 855slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 856 857[system.cpu.toL2Bus.snoop_filter] 858type=SnoopFilter 859eventq_index=0 860lookup_latency=0 861max_capacity=8388608 862system=system 863 864[system.cpu.tracer] 865type=ExeTracer 866eventq_index=0 867 868[system.cpu.workload] 869type=LiveProcess 870cmd=hello 871cwd= 872drivers= 873egid=100 874env= 875errout=cerr 876euid=100 877eventq_index=0 878executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello 879gid=100 880input=cin 881kvmInSE=false 882max_stack_size=67108864 883output=cout 884pid=100 885ppid=99 886simpoint=0 887system=system 888uid=100 889useArchPT=false 890 891[system.cpu_clk_domain] 892type=SrcClockDomain 893clock=500 894domain_id=-1 895eventq_index=0 896init_perf_level=0 897voltage_domain=system.voltage_domain 898 899[system.dvfs_handler] 900type=DVFSHandler 901domains= 902enable=false 903eventq_index=0 904sys_clk_domain=system.clk_domain 905transition_latency=100000000 906 907[system.membus] 908type=CoherentXBar 909clk_domain=system.clk_domain 910eventq_index=0 911forward_latency=4 912frontend_latency=3 913point_of_coherency=true 914response_latency=2 915snoop_filter=Null 916snoop_response_latency=4 917system=system 918use_default_range=false 919width=16 920master=system.physmem.port 921slave=system.system_port system.cpu.l2cache.mem_side 922 923[system.physmem] 924type=DRAMCtrl 925IDD0=0.075000 926IDD02=0.000000 927IDD2N=0.050000 928IDD2N2=0.000000 929IDD2P0=0.000000 930IDD2P02=0.000000 931IDD2P1=0.000000 932IDD2P12=0.000000 933IDD3N=0.057000 934IDD3N2=0.000000 935IDD3P0=0.000000 936IDD3P02=0.000000 937IDD3P1=0.000000 938IDD3P12=0.000000 939IDD4R=0.187000 940IDD4R2=0.000000 941IDD4W=0.165000 942IDD4W2=0.000000 943IDD5=0.220000 944IDD52=0.000000 945IDD6=0.000000 946IDD62=0.000000 947VDD=1.500000 948VDD2=0.000000 949activation_limit=4 950addr_mapping=RoRaBaCoCh 951bank_groups_per_rank=0 952banks_per_rank=8 953burst_length=8 954channels=1 955clk_domain=system.clk_domain 956conf_table_reported=true 957device_bus_width=8 958device_rowbuffer_size=1024 959device_size=536870912 960devices_per_rank=8 961dll=true 962eventq_index=0 963in_addr_map=true 964max_accesses_per_row=16 965mem_sched_policy=frfcfs 966min_writes_per_switch=16 967null=false 968page_policy=open_adaptive 969range=0:134217727 970ranks_per_channel=2 971read_buffer_size=32 972static_backend_latency=10000 973static_frontend_latency=10000 974tBURST=5000 975tCCD_L=0 976tCK=1250 977tCL=13750 978tCS=2500 979tRAS=35000 980tRCD=13750 981tREFI=7800000 982tRFC=260000 983tRP=13750 984tRRD=6000 985tRRD_L=0 986tRTP=7500 987tRTW=2500 988tWR=15000 989tWTR=7500 990tXAW=30000 991tXP=0 992tXPDLL=0 993tXS=0 994tXSDLL=0 995write_buffer_size=64 996write_high_thresh_perc=85 997write_low_thresh_perc=50 998port=system.membus.master[0] 999 1000[system.voltage_domain] 1001type=VoltageDomain 1002eventq_index=0 1003voltage=1.000000 1004 1005