config.ini revision 11312
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=DerivO3CPU 51children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu.branchPred 61cachePorts=200 62checker=system.cpu.checker 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=1 72decodeWidth=8 73dispatchWidth=8 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dstage2_mmu=system.cpu.dstage2_mmu 78dtb=system.cpu.dtb 79eventq_index=0 80fetchBufferSize=64 81fetchQueueSize=32 82fetchToDecodeDelay=1 83fetchTrapLatency=1 84fetchWidth=8 85forwardComSize=5 86fuPool=system.cpu.fuPool 87function_trace=false 88function_trace_start=0 89iewToCommitDelay=1 90iewToDecodeDelay=1 91iewToFetchDelay=1 92iewToRenameDelay=1 93interrupts=system.cpu.interrupts 94isa=system.cpu.isa 95issueToExecuteDelay=1 96issueWidth=8 97istage2_mmu=system.cpu.istage2_mmu 98itb=system.cpu.itb 99max_insts_all_threads=0 100max_insts_any_thread=0 101max_loads_all_threads=0 102max_loads_any_thread=0 103needsTSO=false 104numIQEntries=64 105numPhysCCRegs=1280 106numPhysFloatRegs=256 107numPhysIntRegs=256 108numROBEntries=192 109numRobs=1 110numThreads=1 111profile=0 112progress_interval=0 113renameToDecodeDelay=1 114renameToFetchDelay=1 115renameToIEWDelay=2 116renameToROBDelay=1 117renameWidth=8 118simpoint_start_insts= 119smtCommitPolicy=RoundRobin 120smtFetchPolicy=SingleThread 121smtIQPolicy=Partitioned 122smtIQThreshold=100 123smtLSQPolicy=Partitioned 124smtLSQThreshold=100 125smtNumFetchingThreads=1 126smtROBPolicy=Partitioned 127smtROBThreshold=100 128socket_id=0 129squashWidth=8 130store_set_clear_period=250000 131switched_out=false 132system=system 133tracer=system.cpu.tracer 134trapLatency=13 135wbWidth=8 136workload=system.cpu.workload 137dcache_port=system.cpu.dcache.cpu_side 138icache_port=system.cpu.icache.cpu_side 139 140[system.cpu.branchPred] 141type=TournamentBP 142BTBEntries=4096 143BTBTagSize=16 144RASSize=16 145choiceCtrBits=2 146choicePredictorSize=8192 147eventq_index=0 148globalCtrBits=2 149globalPredictorSize=8192 150instShiftAmt=2 151localCtrBits=2 152localHistoryTableSize=2048 153localPredictorSize=2048 154numThreads=1 155 156[system.cpu.checker] 157type=O3Checker 158children=dstage2_mmu dtb isa istage2_mmu itb tracer 159checker=Null 160clk_domain=system.cpu_clk_domain 161cpu_id=0 162do_checkpoint_insts=true 163do_quiesce=true 164do_statistics_insts=true 165dstage2_mmu=system.cpu.checker.dstage2_mmu 166dtb=system.cpu.checker.dtb 167eventq_index=0 168exitOnError=false 169function_trace=false 170function_trace_start=0 171interrupts= 172isa=system.cpu.checker.isa 173istage2_mmu=system.cpu.checker.istage2_mmu 174itb=system.cpu.checker.itb 175max_insts_all_threads=0 176max_insts_any_thread=0 177max_loads_all_threads=0 178max_loads_any_thread=0 179numThreads=1 180profile=0 181progress_interval=0 182simpoint_start_insts= 183socket_id=0 184switched_out=false 185system=system 186tracer=system.cpu.checker.tracer 187updateOnError=true 188warnOnlyOnLoadError=true 189workload=system.cpu.workload 190 191[system.cpu.checker.dstage2_mmu] 192type=ArmStage2MMU 193children=stage2_tlb 194eventq_index=0 195stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 196sys=system 197tlb=system.cpu.checker.dtb 198 199[system.cpu.checker.dstage2_mmu.stage2_tlb] 200type=ArmTLB 201children=walker 202eventq_index=0 203is_stage2=true 204size=32 205walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 206 207[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 208type=ArmTableWalker 209clk_domain=system.cpu_clk_domain 210eventq_index=0 211is_stage2=true 212num_squash_per_cycle=2 213sys=system 214 215[system.cpu.checker.dtb] 216type=ArmTLB 217children=walker 218eventq_index=0 219is_stage2=false 220size=64 221walker=system.cpu.checker.dtb.walker 222 223[system.cpu.checker.dtb.walker] 224type=ArmTableWalker 225clk_domain=system.cpu_clk_domain 226eventq_index=0 227is_stage2=false 228num_squash_per_cycle=2 229sys=system 230port=system.cpu.toL2Bus.slave[5] 231 232[system.cpu.checker.isa] 233type=ArmISA 234decoderFlavour=Generic 235eventq_index=0 236fpsid=1090793632 237id_aa64afr0_el1=0 238id_aa64afr1_el1=0 239id_aa64dfr0_el1=1052678 240id_aa64dfr1_el1=0 241id_aa64isar0_el1=0 242id_aa64isar1_el1=0 243id_aa64mmfr0_el1=15728642 244id_aa64mmfr1_el1=0 245id_aa64pfr0_el1=17 246id_aa64pfr1_el1=0 247id_isar0=34607377 248id_isar1=34677009 249id_isar2=555950401 250id_isar3=17899825 251id_isar4=268501314 252id_isar5=0 253id_mmfr0=270536963 254id_mmfr1=0 255id_mmfr2=19070976 256id_mmfr3=34611729 257id_pfr0=49 258id_pfr1=4113 259midr=1091551472 260pmu=Null 261system=system 262 263[system.cpu.checker.istage2_mmu] 264type=ArmStage2MMU 265children=stage2_tlb 266eventq_index=0 267stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 268sys=system 269tlb=system.cpu.checker.itb 270 271[system.cpu.checker.istage2_mmu.stage2_tlb] 272type=ArmTLB 273children=walker 274eventq_index=0 275is_stage2=true 276size=32 277walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 278 279[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 280type=ArmTableWalker 281clk_domain=system.cpu_clk_domain 282eventq_index=0 283is_stage2=true 284num_squash_per_cycle=2 285sys=system 286 287[system.cpu.checker.itb] 288type=ArmTLB 289children=walker 290eventq_index=0 291is_stage2=false 292size=64 293walker=system.cpu.checker.itb.walker 294 295[system.cpu.checker.itb.walker] 296type=ArmTableWalker 297clk_domain=system.cpu_clk_domain 298eventq_index=0 299is_stage2=false 300num_squash_per_cycle=2 301sys=system 302port=system.cpu.toL2Bus.slave[4] 303 304[system.cpu.checker.tracer] 305type=ExeTracer 306eventq_index=0 307 308[system.cpu.dcache] 309type=Cache 310children=tags 311addr_ranges=0:18446744073709551615 312assoc=2 313clk_domain=system.cpu_clk_domain 314clusivity=mostly_incl 315demand_mshr_reserve=1 316eventq_index=0 317forward_snoops=true 318hit_latency=2 319is_read_only=false 320max_miss_count=0 321mshrs=4 322prefetch_on_access=false 323prefetcher=Null 324response_latency=2 325sequential_access=false 326size=262144 327system=system 328tags=system.cpu.dcache.tags 329tgts_per_mshr=20 330write_buffers=8 331writeback_clean=false 332cpu_side=system.cpu.dcache_port 333mem_side=system.cpu.toL2Bus.slave[1] 334 335[system.cpu.dcache.tags] 336type=LRU 337assoc=2 338block_size=64 339clk_domain=system.cpu_clk_domain 340eventq_index=0 341hit_latency=2 342sequential_access=false 343size=262144 344 345[system.cpu.dstage2_mmu] 346type=ArmStage2MMU 347children=stage2_tlb 348eventq_index=0 349stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 350sys=system 351tlb=system.cpu.dtb 352 353[system.cpu.dstage2_mmu.stage2_tlb] 354type=ArmTLB 355children=walker 356eventq_index=0 357is_stage2=true 358size=32 359walker=system.cpu.dstage2_mmu.stage2_tlb.walker 360 361[system.cpu.dstage2_mmu.stage2_tlb.walker] 362type=ArmTableWalker 363clk_domain=system.cpu_clk_domain 364eventq_index=0 365is_stage2=true 366num_squash_per_cycle=2 367sys=system 368 369[system.cpu.dtb] 370type=ArmTLB 371children=walker 372eventq_index=0 373is_stage2=false 374size=64 375walker=system.cpu.dtb.walker 376 377[system.cpu.dtb.walker] 378type=ArmTableWalker 379clk_domain=system.cpu_clk_domain 380eventq_index=0 381is_stage2=false 382num_squash_per_cycle=2 383sys=system 384port=system.cpu.toL2Bus.slave[3] 385 386[system.cpu.fuPool] 387type=FUPool 388children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 389FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 390eventq_index=0 391 392[system.cpu.fuPool.FUList0] 393type=FUDesc 394children=opList 395count=6 396eventq_index=0 397opList=system.cpu.fuPool.FUList0.opList 398 399[system.cpu.fuPool.FUList0.opList] 400type=OpDesc 401eventq_index=0 402opClass=IntAlu 403opLat=1 404pipelined=true 405 406[system.cpu.fuPool.FUList1] 407type=FUDesc 408children=opList0 opList1 409count=2 410eventq_index=0 411opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 412 413[system.cpu.fuPool.FUList1.opList0] 414type=OpDesc 415eventq_index=0 416opClass=IntMult 417opLat=3 418pipelined=true 419 420[system.cpu.fuPool.FUList1.opList1] 421type=OpDesc 422eventq_index=0 423opClass=IntDiv 424opLat=20 425pipelined=false 426 427[system.cpu.fuPool.FUList2] 428type=FUDesc 429children=opList0 opList1 opList2 430count=4 431eventq_index=0 432opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 433 434[system.cpu.fuPool.FUList2.opList0] 435type=OpDesc 436eventq_index=0 437opClass=FloatAdd 438opLat=2 439pipelined=true 440 441[system.cpu.fuPool.FUList2.opList1] 442type=OpDesc 443eventq_index=0 444opClass=FloatCmp 445opLat=2 446pipelined=true 447 448[system.cpu.fuPool.FUList2.opList2] 449type=OpDesc 450eventq_index=0 451opClass=FloatCvt 452opLat=2 453pipelined=true 454 455[system.cpu.fuPool.FUList3] 456type=FUDesc 457children=opList0 opList1 opList2 458count=2 459eventq_index=0 460opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 461 462[system.cpu.fuPool.FUList3.opList0] 463type=OpDesc 464eventq_index=0 465opClass=FloatMult 466opLat=4 467pipelined=true 468 469[system.cpu.fuPool.FUList3.opList1] 470type=OpDesc 471eventq_index=0 472opClass=FloatDiv 473opLat=12 474pipelined=false 475 476[system.cpu.fuPool.FUList3.opList2] 477type=OpDesc 478eventq_index=0 479opClass=FloatSqrt 480opLat=24 481pipelined=false 482 483[system.cpu.fuPool.FUList4] 484type=FUDesc 485children=opList 486count=0 487eventq_index=0 488opList=system.cpu.fuPool.FUList4.opList 489 490[system.cpu.fuPool.FUList4.opList] 491type=OpDesc 492eventq_index=0 493opClass=MemRead 494opLat=1 495pipelined=true 496 497[system.cpu.fuPool.FUList5] 498type=FUDesc 499children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 500count=4 501eventq_index=0 502opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 503 504[system.cpu.fuPool.FUList5.opList00] 505type=OpDesc 506eventq_index=0 507opClass=SimdAdd 508opLat=1 509pipelined=true 510 511[system.cpu.fuPool.FUList5.opList01] 512type=OpDesc 513eventq_index=0 514opClass=SimdAddAcc 515opLat=1 516pipelined=true 517 518[system.cpu.fuPool.FUList5.opList02] 519type=OpDesc 520eventq_index=0 521opClass=SimdAlu 522opLat=1 523pipelined=true 524 525[system.cpu.fuPool.FUList5.opList03] 526type=OpDesc 527eventq_index=0 528opClass=SimdCmp 529opLat=1 530pipelined=true 531 532[system.cpu.fuPool.FUList5.opList04] 533type=OpDesc 534eventq_index=0 535opClass=SimdCvt 536opLat=1 537pipelined=true 538 539[system.cpu.fuPool.FUList5.opList05] 540type=OpDesc 541eventq_index=0 542opClass=SimdMisc 543opLat=1 544pipelined=true 545 546[system.cpu.fuPool.FUList5.opList06] 547type=OpDesc 548eventq_index=0 549opClass=SimdMult 550opLat=1 551pipelined=true 552 553[system.cpu.fuPool.FUList5.opList07] 554type=OpDesc 555eventq_index=0 556opClass=SimdMultAcc 557opLat=1 558pipelined=true 559 560[system.cpu.fuPool.FUList5.opList08] 561type=OpDesc 562eventq_index=0 563opClass=SimdShift 564opLat=1 565pipelined=true 566 567[system.cpu.fuPool.FUList5.opList09] 568type=OpDesc 569eventq_index=0 570opClass=SimdShiftAcc 571opLat=1 572pipelined=true 573 574[system.cpu.fuPool.FUList5.opList10] 575type=OpDesc 576eventq_index=0 577opClass=SimdSqrt 578opLat=1 579pipelined=true 580 581[system.cpu.fuPool.FUList5.opList11] 582type=OpDesc 583eventq_index=0 584opClass=SimdFloatAdd 585opLat=1 586pipelined=true 587 588[system.cpu.fuPool.FUList5.opList12] 589type=OpDesc 590eventq_index=0 591opClass=SimdFloatAlu 592opLat=1 593pipelined=true 594 595[system.cpu.fuPool.FUList5.opList13] 596type=OpDesc 597eventq_index=0 598opClass=SimdFloatCmp 599opLat=1 600pipelined=true 601 602[system.cpu.fuPool.FUList5.opList14] 603type=OpDesc 604eventq_index=0 605opClass=SimdFloatCvt 606opLat=1 607pipelined=true 608 609[system.cpu.fuPool.FUList5.opList15] 610type=OpDesc 611eventq_index=0 612opClass=SimdFloatDiv 613opLat=1 614pipelined=true 615 616[system.cpu.fuPool.FUList5.opList16] 617type=OpDesc 618eventq_index=0 619opClass=SimdFloatMisc 620opLat=1 621pipelined=true 622 623[system.cpu.fuPool.FUList5.opList17] 624type=OpDesc 625eventq_index=0 626opClass=SimdFloatMult 627opLat=1 628pipelined=true 629 630[system.cpu.fuPool.FUList5.opList18] 631type=OpDesc 632eventq_index=0 633opClass=SimdFloatMultAcc 634opLat=1 635pipelined=true 636 637[system.cpu.fuPool.FUList5.opList19] 638type=OpDesc 639eventq_index=0 640opClass=SimdFloatSqrt 641opLat=1 642pipelined=true 643 644[system.cpu.fuPool.FUList6] 645type=FUDesc 646children=opList 647count=0 648eventq_index=0 649opList=system.cpu.fuPool.FUList6.opList 650 651[system.cpu.fuPool.FUList6.opList] 652type=OpDesc 653eventq_index=0 654opClass=MemWrite 655opLat=1 656pipelined=true 657 658[system.cpu.fuPool.FUList7] 659type=FUDesc 660children=opList0 opList1 661count=4 662eventq_index=0 663opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 664 665[system.cpu.fuPool.FUList7.opList0] 666type=OpDesc 667eventq_index=0 668opClass=MemRead 669opLat=1 670pipelined=true 671 672[system.cpu.fuPool.FUList7.opList1] 673type=OpDesc 674eventq_index=0 675opClass=MemWrite 676opLat=1 677pipelined=true 678 679[system.cpu.fuPool.FUList8] 680type=FUDesc 681children=opList 682count=1 683eventq_index=0 684opList=system.cpu.fuPool.FUList8.opList 685 686[system.cpu.fuPool.FUList8.opList] 687type=OpDesc 688eventq_index=0 689opClass=IprAccess 690opLat=3 691pipelined=false 692 693[system.cpu.icache] 694type=Cache 695children=tags 696addr_ranges=0:18446744073709551615 697assoc=2 698clk_domain=system.cpu_clk_domain 699clusivity=mostly_incl 700demand_mshr_reserve=1 701eventq_index=0 702forward_snoops=true 703hit_latency=2 704is_read_only=true 705max_miss_count=0 706mshrs=4 707prefetch_on_access=false 708prefetcher=Null 709response_latency=2 710sequential_access=false 711size=131072 712system=system 713tags=system.cpu.icache.tags 714tgts_per_mshr=20 715write_buffers=8 716writeback_clean=true 717cpu_side=system.cpu.icache_port 718mem_side=system.cpu.toL2Bus.slave[0] 719 720[system.cpu.icache.tags] 721type=LRU 722assoc=2 723block_size=64 724clk_domain=system.cpu_clk_domain 725eventq_index=0 726hit_latency=2 727sequential_access=false 728size=131072 729 730[system.cpu.interrupts] 731type=ArmInterrupts 732eventq_index=0 733 734[system.cpu.isa] 735type=ArmISA 736decoderFlavour=Generic 737eventq_index=0 738fpsid=1090793632 739id_aa64afr0_el1=0 740id_aa64afr1_el1=0 741id_aa64dfr0_el1=1052678 742id_aa64dfr1_el1=0 743id_aa64isar0_el1=0 744id_aa64isar1_el1=0 745id_aa64mmfr0_el1=15728642 746id_aa64mmfr1_el1=0 747id_aa64pfr0_el1=17 748id_aa64pfr1_el1=0 749id_isar0=34607377 750id_isar1=34677009 751id_isar2=555950401 752id_isar3=17899825 753id_isar4=268501314 754id_isar5=0 755id_mmfr0=270536963 756id_mmfr1=0 757id_mmfr2=19070976 758id_mmfr3=34611729 759id_pfr0=49 760id_pfr1=4113 761midr=1091551472 762pmu=Null 763system=system 764 765[system.cpu.istage2_mmu] 766type=ArmStage2MMU 767children=stage2_tlb 768eventq_index=0 769stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 770sys=system 771tlb=system.cpu.itb 772 773[system.cpu.istage2_mmu.stage2_tlb] 774type=ArmTLB 775children=walker 776eventq_index=0 777is_stage2=true 778size=32 779walker=system.cpu.istage2_mmu.stage2_tlb.walker 780 781[system.cpu.istage2_mmu.stage2_tlb.walker] 782type=ArmTableWalker 783clk_domain=system.cpu_clk_domain 784eventq_index=0 785is_stage2=true 786num_squash_per_cycle=2 787sys=system 788 789[system.cpu.itb] 790type=ArmTLB 791children=walker 792eventq_index=0 793is_stage2=false 794size=64 795walker=system.cpu.itb.walker 796 797[system.cpu.itb.walker] 798type=ArmTableWalker 799clk_domain=system.cpu_clk_domain 800eventq_index=0 801is_stage2=false 802num_squash_per_cycle=2 803sys=system 804port=system.cpu.toL2Bus.slave[2] 805 806[system.cpu.l2cache] 807type=Cache 808children=tags 809addr_ranges=0:18446744073709551615 810assoc=8 811clk_domain=system.cpu_clk_domain 812clusivity=mostly_incl 813demand_mshr_reserve=1 814eventq_index=0 815forward_snoops=true 816hit_latency=20 817is_read_only=false 818max_miss_count=0 819mshrs=20 820prefetch_on_access=false 821prefetcher=Null 822response_latency=20 823sequential_access=false 824size=2097152 825system=system 826tags=system.cpu.l2cache.tags 827tgts_per_mshr=12 828write_buffers=8 829writeback_clean=false 830cpu_side=system.cpu.toL2Bus.master[0] 831mem_side=system.membus.slave[1] 832 833[system.cpu.l2cache.tags] 834type=LRU 835assoc=8 836block_size=64 837clk_domain=system.cpu_clk_domain 838eventq_index=0 839hit_latency=20 840sequential_access=false 841size=2097152 842 843[system.cpu.toL2Bus] 844type=CoherentXBar 845children=snoop_filter 846clk_domain=system.cpu_clk_domain 847eventq_index=0 848forward_latency=0 849frontend_latency=1 850response_latency=1 851snoop_filter=system.cpu.toL2Bus.snoop_filter 852snoop_response_latency=1 853system=system 854use_default_range=false 855width=32 856master=system.cpu.l2cache.cpu_side 857slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 858 859[system.cpu.toL2Bus.snoop_filter] 860type=SnoopFilter 861eventq_index=0 862lookup_latency=0 863max_capacity=8388608 864system=system 865 866[system.cpu.tracer] 867type=ExeTracer 868eventq_index=0 869 870[system.cpu.workload] 871type=LiveProcess 872cmd=hello 873cwd= 874drivers= 875egid=100 876env= 877errout=cerr 878euid=100 879eventq_index=0 880executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 881gid=100 882input=cin 883kvmInSE=false 884max_stack_size=67108864 885output=cout 886pid=100 887ppid=99 888simpoint=0 889system=system 890uid=100 891useArchPT=false 892 893[system.cpu_clk_domain] 894type=SrcClockDomain 895clock=500 896domain_id=-1 897eventq_index=0 898init_perf_level=0 899voltage_domain=system.voltage_domain 900 901[system.dvfs_handler] 902type=DVFSHandler 903domains= 904enable=false 905eventq_index=0 906sys_clk_domain=system.clk_domain 907transition_latency=100000000 908 909[system.membus] 910type=CoherentXBar 911clk_domain=system.clk_domain 912eventq_index=0 913forward_latency=4 914frontend_latency=3 915response_latency=2 916snoop_filter=Null 917snoop_response_latency=4 918system=system 919use_default_range=false 920width=16 921master=system.physmem.port 922slave=system.system_port system.cpu.l2cache.mem_side 923 924[system.physmem] 925type=DRAMCtrl 926IDD0=0.075000 927IDD02=0.000000 928IDD2N=0.050000 929IDD2N2=0.000000 930IDD2P0=0.000000 931IDD2P02=0.000000 932IDD2P1=0.000000 933IDD2P12=0.000000 934IDD3N=0.057000 935IDD3N2=0.000000 936IDD3P0=0.000000 937IDD3P02=0.000000 938IDD3P1=0.000000 939IDD3P12=0.000000 940IDD4R=0.187000 941IDD4R2=0.000000 942IDD4W=0.165000 943IDD4W2=0.000000 944IDD5=0.220000 945IDD52=0.000000 946IDD6=0.000000 947IDD62=0.000000 948VDD=1.500000 949VDD2=0.000000 950activation_limit=4 951addr_mapping=RoRaBaCoCh 952bank_groups_per_rank=0 953banks_per_rank=8 954burst_length=8 955channels=1 956clk_domain=system.clk_domain 957conf_table_reported=true 958device_bus_width=8 959device_rowbuffer_size=1024 960device_size=536870912 961devices_per_rank=8 962dll=true 963eventq_index=0 964in_addr_map=true 965max_accesses_per_row=16 966mem_sched_policy=frfcfs 967min_writes_per_switch=16 968null=false 969page_policy=open_adaptive 970range=0:134217727 971ranks_per_channel=2 972read_buffer_size=32 973static_backend_latency=10000 974static_frontend_latency=10000 975tBURST=5000 976tCCD_L=0 977tCK=1250 978tCL=13750 979tCS=2500 980tRAS=35000 981tRCD=13750 982tREFI=7800000 983tRFC=260000 984tRP=13750 985tRRD=6000 986tRRD_L=0 987tRTP=7500 988tRTW=2500 989tWR=15000 990tWTR=7500 991tXAW=30000 992tXP=0 993tXPDLL=0 994tXS=0 995tXSDLL=0 996write_buffer_size=64 997write_high_thresh_perc=85 998write_low_thresh_perc=50 999port=system.membus.master[0] 1000 1001[system.voltage_domain] 1002type=VoltageDomain 1003eventq_index=0 1004voltage=1.000000 1005 1006