config.ini revision 11066
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=system.cpu.checker 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dstage2_mmu=system.cpu.dstage2_mmu 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=64 79fetchQueueSize=32 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95istage2_mmu=system.cpu.istage2_mmu 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=64 103numPhysCCRegs=1280 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] 139type=TournamentBP 140BTBEntries=4096 141BTBTagSize=16 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153 154[system.cpu.checker] 155type=O3Checker 156children=dstage2_mmu dtb isa istage2_mmu itb tracer 157checker=Null 158clk_domain=system.cpu_clk_domain 159cpu_id=0 160do_checkpoint_insts=true 161do_quiesce=true 162do_statistics_insts=true 163dstage2_mmu=system.cpu.checker.dstage2_mmu 164dtb=system.cpu.checker.dtb 165eventq_index=0 166exitOnError=false 167function_trace=false 168function_trace_start=0 169interrupts=Null 170isa=system.cpu.checker.isa 171istage2_mmu=system.cpu.checker.istage2_mmu 172itb=system.cpu.checker.itb 173max_insts_all_threads=0 174max_insts_any_thread=0 175max_loads_all_threads=0 176max_loads_any_thread=0 177numThreads=1 178profile=0 179progress_interval=0 180simpoint_start_insts= 181socket_id=0 182switched_out=false 183system=system 184tracer=system.cpu.checker.tracer 185updateOnError=true 186warnOnlyOnLoadError=true 187workload=system.cpu.workload 188 189[system.cpu.checker.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 194sys=system 195tlb=system.cpu.checker.dtb 196 197[system.cpu.checker.dstage2_mmu.stage2_tlb] 198type=ArmTLB 199children=walker 200eventq_index=0 201is_stage2=true 202size=32 203walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 204 205[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 206type=ArmTableWalker 207clk_domain=system.cpu_clk_domain 208eventq_index=0 209is_stage2=true 210num_squash_per_cycle=2 211sys=system 212 213[system.cpu.checker.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.checker.dtb.walker 220 221[system.cpu.checker.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system 228port=system.cpu.toL2Bus.slave[5] 229 230[system.cpu.checker.isa] 231type=ArmISA 232eventq_index=0 233fpsid=1090793632 234id_aa64afr0_el1=0 235id_aa64afr1_el1=0 236id_aa64dfr0_el1=1052678 237id_aa64dfr1_el1=0 238id_aa64isar0_el1=0 239id_aa64isar1_el1=0 240id_aa64mmfr0_el1=15728642 241id_aa64mmfr1_el1=0 242id_aa64pfr0_el1=17 243id_aa64pfr1_el1=0 244id_isar0=34607377 245id_isar1=34677009 246id_isar2=555950401 247id_isar3=17899825 248id_isar4=268501314 249id_isar5=0 250id_mmfr0=270536963 251id_mmfr1=0 252id_mmfr2=19070976 253id_mmfr3=34611729 254id_pfr0=49 255id_pfr1=4113 256midr=1091551472 257pmu=Null 258system=system 259 260[system.cpu.checker.istage2_mmu] 261type=ArmStage2MMU 262children=stage2_tlb 263eventq_index=0 264stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 265sys=system 266tlb=system.cpu.checker.itb 267 268[system.cpu.checker.istage2_mmu.stage2_tlb] 269type=ArmTLB 270children=walker 271eventq_index=0 272is_stage2=true 273size=32 274walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 275 276[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 277type=ArmTableWalker 278clk_domain=system.cpu_clk_domain 279eventq_index=0 280is_stage2=true 281num_squash_per_cycle=2 282sys=system 283 284[system.cpu.checker.itb] 285type=ArmTLB 286children=walker 287eventq_index=0 288is_stage2=false 289size=64 290walker=system.cpu.checker.itb.walker 291 292[system.cpu.checker.itb.walker] 293type=ArmTableWalker 294clk_domain=system.cpu_clk_domain 295eventq_index=0 296is_stage2=false 297num_squash_per_cycle=2 298sys=system 299port=system.cpu.toL2Bus.slave[4] 300 301[system.cpu.checker.tracer] 302type=ExeTracer 303eventq_index=0 304 305[system.cpu.dcache] 306type=Cache 307children=tags 308addr_ranges=0:18446744073709551615 309assoc=2 310clk_domain=system.cpu_clk_domain 311demand_mshr_reserve=1 312eventq_index=0 313forward_snoops=true 314hit_latency=2 315is_read_only=false 316max_miss_count=0 317mshrs=4 318prefetch_on_access=false 319prefetcher=Null 320response_latency=2 321sequential_access=false 322size=262144 323system=system 324tags=system.cpu.dcache.tags 325tgts_per_mshr=20 326write_buffers=8 327cpu_side=system.cpu.dcache_port 328mem_side=system.cpu.toL2Bus.slave[1] 329 330[system.cpu.dcache.tags] 331type=LRU 332assoc=2 333block_size=64 334clk_domain=system.cpu_clk_domain 335eventq_index=0 336hit_latency=2 337sequential_access=false 338size=262144 339 340[system.cpu.dstage2_mmu] 341type=ArmStage2MMU 342children=stage2_tlb 343eventq_index=0 344stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 345sys=system 346tlb=system.cpu.dtb 347 348[system.cpu.dstage2_mmu.stage2_tlb] 349type=ArmTLB 350children=walker 351eventq_index=0 352is_stage2=true 353size=32 354walker=system.cpu.dstage2_mmu.stage2_tlb.walker 355 356[system.cpu.dstage2_mmu.stage2_tlb.walker] 357type=ArmTableWalker 358clk_domain=system.cpu_clk_domain 359eventq_index=0 360is_stage2=true 361num_squash_per_cycle=2 362sys=system 363 364[system.cpu.dtb] 365type=ArmTLB 366children=walker 367eventq_index=0 368is_stage2=false 369size=64 370walker=system.cpu.dtb.walker 371 372[system.cpu.dtb.walker] 373type=ArmTableWalker 374clk_domain=system.cpu_clk_domain 375eventq_index=0 376is_stage2=false 377num_squash_per_cycle=2 378sys=system 379port=system.cpu.toL2Bus.slave[3] 380 381[system.cpu.fuPool] 382type=FUPool 383children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 384FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 385eventq_index=0 386 387[system.cpu.fuPool.FUList0] 388type=FUDesc 389children=opList 390count=6 391eventq_index=0 392opList=system.cpu.fuPool.FUList0.opList 393 394[system.cpu.fuPool.FUList0.opList] 395type=OpDesc 396eventq_index=0 397opClass=IntAlu 398opLat=1 399pipelined=true 400 401[system.cpu.fuPool.FUList1] 402type=FUDesc 403children=opList0 opList1 404count=2 405eventq_index=0 406opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 407 408[system.cpu.fuPool.FUList1.opList0] 409type=OpDesc 410eventq_index=0 411opClass=IntMult 412opLat=3 413pipelined=true 414 415[system.cpu.fuPool.FUList1.opList1] 416type=OpDesc 417eventq_index=0 418opClass=IntDiv 419opLat=20 420pipelined=false 421 422[system.cpu.fuPool.FUList2] 423type=FUDesc 424children=opList0 opList1 opList2 425count=4 426eventq_index=0 427opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 428 429[system.cpu.fuPool.FUList2.opList0] 430type=OpDesc 431eventq_index=0 432opClass=FloatAdd 433opLat=2 434pipelined=true 435 436[system.cpu.fuPool.FUList2.opList1] 437type=OpDesc 438eventq_index=0 439opClass=FloatCmp 440opLat=2 441pipelined=true 442 443[system.cpu.fuPool.FUList2.opList2] 444type=OpDesc 445eventq_index=0 446opClass=FloatCvt 447opLat=2 448pipelined=true 449 450[system.cpu.fuPool.FUList3] 451type=FUDesc 452children=opList0 opList1 opList2 453count=2 454eventq_index=0 455opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 456 457[system.cpu.fuPool.FUList3.opList0] 458type=OpDesc 459eventq_index=0 460opClass=FloatMult 461opLat=4 462pipelined=true 463 464[system.cpu.fuPool.FUList3.opList1] 465type=OpDesc 466eventq_index=0 467opClass=FloatDiv 468opLat=12 469pipelined=false 470 471[system.cpu.fuPool.FUList3.opList2] 472type=OpDesc 473eventq_index=0 474opClass=FloatSqrt 475opLat=24 476pipelined=false 477 478[system.cpu.fuPool.FUList4] 479type=FUDesc 480children=opList 481count=0 482eventq_index=0 483opList=system.cpu.fuPool.FUList4.opList 484 485[system.cpu.fuPool.FUList4.opList] 486type=OpDesc 487eventq_index=0 488opClass=MemRead 489opLat=1 490pipelined=true 491 492[system.cpu.fuPool.FUList5] 493type=FUDesc 494children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 495count=4 496eventq_index=0 497opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 498 499[system.cpu.fuPool.FUList5.opList00] 500type=OpDesc 501eventq_index=0 502opClass=SimdAdd 503opLat=1 504pipelined=true 505 506[system.cpu.fuPool.FUList5.opList01] 507type=OpDesc 508eventq_index=0 509opClass=SimdAddAcc 510opLat=1 511pipelined=true 512 513[system.cpu.fuPool.FUList5.opList02] 514type=OpDesc 515eventq_index=0 516opClass=SimdAlu 517opLat=1 518pipelined=true 519 520[system.cpu.fuPool.FUList5.opList03] 521type=OpDesc 522eventq_index=0 523opClass=SimdCmp 524opLat=1 525pipelined=true 526 527[system.cpu.fuPool.FUList5.opList04] 528type=OpDesc 529eventq_index=0 530opClass=SimdCvt 531opLat=1 532pipelined=true 533 534[system.cpu.fuPool.FUList5.opList05] 535type=OpDesc 536eventq_index=0 537opClass=SimdMisc 538opLat=1 539pipelined=true 540 541[system.cpu.fuPool.FUList5.opList06] 542type=OpDesc 543eventq_index=0 544opClass=SimdMult 545opLat=1 546pipelined=true 547 548[system.cpu.fuPool.FUList5.opList07] 549type=OpDesc 550eventq_index=0 551opClass=SimdMultAcc 552opLat=1 553pipelined=true 554 555[system.cpu.fuPool.FUList5.opList08] 556type=OpDesc 557eventq_index=0 558opClass=SimdShift 559opLat=1 560pipelined=true 561 562[system.cpu.fuPool.FUList5.opList09] 563type=OpDesc 564eventq_index=0 565opClass=SimdShiftAcc 566opLat=1 567pipelined=true 568 569[system.cpu.fuPool.FUList5.opList10] 570type=OpDesc 571eventq_index=0 572opClass=SimdSqrt 573opLat=1 574pipelined=true 575 576[system.cpu.fuPool.FUList5.opList11] 577type=OpDesc 578eventq_index=0 579opClass=SimdFloatAdd 580opLat=1 581pipelined=true 582 583[system.cpu.fuPool.FUList5.opList12] 584type=OpDesc 585eventq_index=0 586opClass=SimdFloatAlu 587opLat=1 588pipelined=true 589 590[system.cpu.fuPool.FUList5.opList13] 591type=OpDesc 592eventq_index=0 593opClass=SimdFloatCmp 594opLat=1 595pipelined=true 596 597[system.cpu.fuPool.FUList5.opList14] 598type=OpDesc 599eventq_index=0 600opClass=SimdFloatCvt 601opLat=1 602pipelined=true 603 604[system.cpu.fuPool.FUList5.opList15] 605type=OpDesc 606eventq_index=0 607opClass=SimdFloatDiv 608opLat=1 609pipelined=true 610 611[system.cpu.fuPool.FUList5.opList16] 612type=OpDesc 613eventq_index=0 614opClass=SimdFloatMisc 615opLat=1 616pipelined=true 617 618[system.cpu.fuPool.FUList5.opList17] 619type=OpDesc 620eventq_index=0 621opClass=SimdFloatMult 622opLat=1 623pipelined=true 624 625[system.cpu.fuPool.FUList5.opList18] 626type=OpDesc 627eventq_index=0 628opClass=SimdFloatMultAcc 629opLat=1 630pipelined=true 631 632[system.cpu.fuPool.FUList5.opList19] 633type=OpDesc 634eventq_index=0 635opClass=SimdFloatSqrt 636opLat=1 637pipelined=true 638 639[system.cpu.fuPool.FUList6] 640type=FUDesc 641children=opList 642count=0 643eventq_index=0 644opList=system.cpu.fuPool.FUList6.opList 645 646[system.cpu.fuPool.FUList6.opList] 647type=OpDesc 648eventq_index=0 649opClass=MemWrite 650opLat=1 651pipelined=true 652 653[system.cpu.fuPool.FUList7] 654type=FUDesc 655children=opList0 opList1 656count=4 657eventq_index=0 658opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 659 660[system.cpu.fuPool.FUList7.opList0] 661type=OpDesc 662eventq_index=0 663opClass=MemRead 664opLat=1 665pipelined=true 666 667[system.cpu.fuPool.FUList7.opList1] 668type=OpDesc 669eventq_index=0 670opClass=MemWrite 671opLat=1 672pipelined=true 673 674[system.cpu.fuPool.FUList8] 675type=FUDesc 676children=opList 677count=1 678eventq_index=0 679opList=system.cpu.fuPool.FUList8.opList 680 681[system.cpu.fuPool.FUList8.opList] 682type=OpDesc 683eventq_index=0 684opClass=IprAccess 685opLat=3 686pipelined=false 687 688[system.cpu.icache] 689type=Cache 690children=tags 691addr_ranges=0:18446744073709551615 692assoc=2 693clk_domain=system.cpu_clk_domain 694demand_mshr_reserve=1 695eventq_index=0 696forward_snoops=true 697hit_latency=2 698is_read_only=true 699max_miss_count=0 700mshrs=4 701prefetch_on_access=false 702prefetcher=Null 703response_latency=2 704sequential_access=false 705size=131072 706system=system 707tags=system.cpu.icache.tags 708tgts_per_mshr=20 709write_buffers=8 710cpu_side=system.cpu.icache_port 711mem_side=system.cpu.toL2Bus.slave[0] 712 713[system.cpu.icache.tags] 714type=LRU 715assoc=2 716block_size=64 717clk_domain=system.cpu_clk_domain 718eventq_index=0 719hit_latency=2 720sequential_access=false 721size=131072 722 723[system.cpu.interrupts] 724type=ArmInterrupts 725eventq_index=0 726 727[system.cpu.isa] 728type=ArmISA 729eventq_index=0 730fpsid=1090793632 731id_aa64afr0_el1=0 732id_aa64afr1_el1=0 733id_aa64dfr0_el1=1052678 734id_aa64dfr1_el1=0 735id_aa64isar0_el1=0 736id_aa64isar1_el1=0 737id_aa64mmfr0_el1=15728642 738id_aa64mmfr1_el1=0 739id_aa64pfr0_el1=17 740id_aa64pfr1_el1=0 741id_isar0=34607377 742id_isar1=34677009 743id_isar2=555950401 744id_isar3=17899825 745id_isar4=268501314 746id_isar5=0 747id_mmfr0=270536963 748id_mmfr1=0 749id_mmfr2=19070976 750id_mmfr3=34611729 751id_pfr0=49 752id_pfr1=4113 753midr=1091551472 754pmu=Null 755system=system 756 757[system.cpu.istage2_mmu] 758type=ArmStage2MMU 759children=stage2_tlb 760eventq_index=0 761stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 762sys=system 763tlb=system.cpu.itb 764 765[system.cpu.istage2_mmu.stage2_tlb] 766type=ArmTLB 767children=walker 768eventq_index=0 769is_stage2=true 770size=32 771walker=system.cpu.istage2_mmu.stage2_tlb.walker 772 773[system.cpu.istage2_mmu.stage2_tlb.walker] 774type=ArmTableWalker 775clk_domain=system.cpu_clk_domain 776eventq_index=0 777is_stage2=true 778num_squash_per_cycle=2 779sys=system 780 781[system.cpu.itb] 782type=ArmTLB 783children=walker 784eventq_index=0 785is_stage2=false 786size=64 787walker=system.cpu.itb.walker 788 789[system.cpu.itb.walker] 790type=ArmTableWalker 791clk_domain=system.cpu_clk_domain 792eventq_index=0 793is_stage2=false 794num_squash_per_cycle=2 795sys=system 796port=system.cpu.toL2Bus.slave[2] 797 798[system.cpu.l2cache] 799type=Cache 800children=tags 801addr_ranges=0:18446744073709551615 802assoc=8 803clk_domain=system.cpu_clk_domain 804demand_mshr_reserve=1 805eventq_index=0 806forward_snoops=true 807hit_latency=20 808is_read_only=false 809max_miss_count=0 810mshrs=20 811prefetch_on_access=false 812prefetcher=Null 813response_latency=20 814sequential_access=false 815size=2097152 816system=system 817tags=system.cpu.l2cache.tags 818tgts_per_mshr=12 819write_buffers=8 820cpu_side=system.cpu.toL2Bus.master[0] 821mem_side=system.membus.slave[1] 822 823[system.cpu.l2cache.tags] 824type=LRU 825assoc=8 826block_size=64 827clk_domain=system.cpu_clk_domain 828eventq_index=0 829hit_latency=20 830sequential_access=false 831size=2097152 832 833[system.cpu.toL2Bus] 834type=CoherentXBar 835clk_domain=system.cpu_clk_domain 836eventq_index=0 837forward_latency=0 838frontend_latency=1 839response_latency=1 840snoop_filter=Null 841snoop_response_latency=1 842system=system 843use_default_range=false 844width=32 845master=system.cpu.l2cache.cpu_side 846slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 847 848[system.cpu.tracer] 849type=ExeTracer 850eventq_index=0 851 852[system.cpu.workload] 853type=LiveProcess 854cmd=hello 855cwd= 856drivers= 857egid=100 858env= 859errout=cerr 860euid=100 861eventq_index=0 862executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 863gid=100 864input=cin 865kvmInSE=false 866max_stack_size=67108864 867output=cout 868pid=100 869ppid=99 870simpoint=0 871system=system 872uid=100 873useArchPT=false 874 875[system.cpu_clk_domain] 876type=SrcClockDomain 877clock=500 878domain_id=-1 879eventq_index=0 880init_perf_level=0 881voltage_domain=system.voltage_domain 882 883[system.dvfs_handler] 884type=DVFSHandler 885domains= 886enable=false 887eventq_index=0 888sys_clk_domain=system.clk_domain 889transition_latency=100000000 890 891[system.membus] 892type=CoherentXBar 893clk_domain=system.clk_domain 894eventq_index=0 895forward_latency=4 896frontend_latency=3 897response_latency=2 898snoop_filter=Null 899snoop_response_latency=4 900system=system 901use_default_range=false 902width=16 903master=system.physmem.port 904slave=system.system_port system.cpu.l2cache.mem_side 905 906[system.physmem] 907type=DRAMCtrl 908IDD0=0.075000 909IDD02=0.000000 910IDD2N=0.050000 911IDD2N2=0.000000 912IDD2P0=0.000000 913IDD2P02=0.000000 914IDD2P1=0.000000 915IDD2P12=0.000000 916IDD3N=0.057000 917IDD3N2=0.000000 918IDD3P0=0.000000 919IDD3P02=0.000000 920IDD3P1=0.000000 921IDD3P12=0.000000 922IDD4R=0.187000 923IDD4R2=0.000000 924IDD4W=0.165000 925IDD4W2=0.000000 926IDD5=0.220000 927IDD52=0.000000 928IDD6=0.000000 929IDD62=0.000000 930VDD=1.500000 931VDD2=0.000000 932activation_limit=4 933addr_mapping=RoRaBaCoCh 934bank_groups_per_rank=0 935banks_per_rank=8 936burst_length=8 937channels=1 938clk_domain=system.clk_domain 939conf_table_reported=true 940device_bus_width=8 941device_rowbuffer_size=1024 942device_size=536870912 943devices_per_rank=8 944dll=true 945eventq_index=0 946in_addr_map=true 947max_accesses_per_row=16 948mem_sched_policy=frfcfs 949min_writes_per_switch=16 950null=false 951page_policy=open_adaptive 952range=0:134217727 953ranks_per_channel=2 954read_buffer_size=32 955static_backend_latency=10000 956static_frontend_latency=10000 957tBURST=5000 958tCCD_L=0 959tCK=1250 960tCL=13750 961tCS=2500 962tRAS=35000 963tRCD=13750 964tREFI=7800000 965tRFC=260000 966tRP=13750 967tRRD=6000 968tRRD_L=0 969tRTP=7500 970tRTW=2500 971tWR=15000 972tWTR=7500 973tXAW=30000 974tXP=0 975tXPDLL=0 976tXS=0 977tXSDLL=0 978write_buffer_size=64 979write_high_thresh_perc=85 980write_low_thresh_perc=50 981port=system.membus.master[0] 982 983[system.voltage_domain] 984type=VoltageDomain 985eventq_index=0 986voltage=1.000000 987 988