config.ini revision 10798
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=system.cpu.checker 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dstage2_mmu=system.cpu.dstage2_mmu 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=64 79fetchQueueSize=32 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95istage2_mmu=system.cpu.istage2_mmu 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=64 103numPhysCCRegs=1280 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] 139type=TournamentBP 140BTBEntries=4096 141BTBTagSize=16 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153 154[system.cpu.checker] 155type=O3Checker 156children=dstage2_mmu dtb isa istage2_mmu itb tracer 157checker=Null 158clk_domain=system.cpu_clk_domain 159cpu_id=0 160do_checkpoint_insts=true 161do_quiesce=true 162do_statistics_insts=true 163dstage2_mmu=system.cpu.checker.dstage2_mmu 164dtb=system.cpu.checker.dtb 165eventq_index=0 166exitOnError=false 167function_trace=false 168function_trace_start=0 169interrupts=Null 170isa=system.cpu.checker.isa 171istage2_mmu=system.cpu.checker.istage2_mmu 172itb=system.cpu.checker.itb 173max_insts_all_threads=0 174max_insts_any_thread=0 175max_loads_all_threads=0 176max_loads_any_thread=0 177numThreads=1 178profile=0 179progress_interval=0 180simpoint_start_insts= 181socket_id=0 182switched_out=false 183system=system 184tracer=system.cpu.checker.tracer 185updateOnError=true 186warnOnlyOnLoadError=true 187workload=system.cpu.workload 188 189[system.cpu.checker.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 194sys=system 195tlb=system.cpu.checker.dtb 196 197[system.cpu.checker.dstage2_mmu.stage2_tlb] 198type=ArmTLB 199children=walker 200eventq_index=0 201is_stage2=true 202size=32 203walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 204 205[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 206type=ArmTableWalker 207clk_domain=system.cpu_clk_domain 208eventq_index=0 209is_stage2=true 210num_squash_per_cycle=2 211sys=system 212 213[system.cpu.checker.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.checker.dtb.walker 220 221[system.cpu.checker.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system 228port=system.cpu.toL2Bus.slave[5] 229 230[system.cpu.checker.isa] 231type=ArmISA 232eventq_index=0 233fpsid=1090793632 234id_aa64afr0_el1=0 235id_aa64afr1_el1=0 236id_aa64dfr0_el1=1052678 237id_aa64dfr1_el1=0 238id_aa64isar0_el1=0 239id_aa64isar1_el1=0 240id_aa64mmfr0_el1=15728642 241id_aa64mmfr1_el1=0 242id_aa64pfr0_el1=17 243id_aa64pfr1_el1=0 244id_isar0=34607377 245id_isar1=34677009 246id_isar2=555950401 247id_isar3=17899825 248id_isar4=268501314 249id_isar5=0 250id_mmfr0=270536963 251id_mmfr1=0 252id_mmfr2=19070976 253id_mmfr3=34611729 254id_pfr0=49 255id_pfr1=4113 256midr=1091551472 257pmu=Null 258system=system 259 260[system.cpu.checker.istage2_mmu] 261type=ArmStage2MMU 262children=stage2_tlb 263eventq_index=0 264stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 265sys=system 266tlb=system.cpu.checker.itb 267 268[system.cpu.checker.istage2_mmu.stage2_tlb] 269type=ArmTLB 270children=walker 271eventq_index=0 272is_stage2=true 273size=32 274walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 275 276[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 277type=ArmTableWalker 278clk_domain=system.cpu_clk_domain 279eventq_index=0 280is_stage2=true 281num_squash_per_cycle=2 282sys=system 283 284[system.cpu.checker.itb] 285type=ArmTLB 286children=walker 287eventq_index=0 288is_stage2=false 289size=64 290walker=system.cpu.checker.itb.walker 291 292[system.cpu.checker.itb.walker] 293type=ArmTableWalker 294clk_domain=system.cpu_clk_domain 295eventq_index=0 296is_stage2=false 297num_squash_per_cycle=2 298sys=system 299port=system.cpu.toL2Bus.slave[4] 300 301[system.cpu.checker.tracer] 302type=ExeTracer 303eventq_index=0 304 305[system.cpu.dcache] 306type=BaseCache 307children=tags 308addr_ranges=0:18446744073709551615 309assoc=2 310clk_domain=system.cpu_clk_domain 311demand_mshr_reserve=1 312eventq_index=0 313forward_snoops=true 314hit_latency=2 315is_top_level=true 316max_miss_count=0 317mshrs=4 318prefetch_on_access=false 319prefetcher=Null 320response_latency=2 321sequential_access=false 322size=262144 323system=system 324tags=system.cpu.dcache.tags 325tgts_per_mshr=20 326two_queue=false 327write_buffers=8 328cpu_side=system.cpu.dcache_port 329mem_side=system.cpu.toL2Bus.slave[1] 330 331[system.cpu.dcache.tags] 332type=LRU 333assoc=2 334block_size=64 335clk_domain=system.cpu_clk_domain 336eventq_index=0 337hit_latency=2 338sequential_access=false 339size=262144 340 341[system.cpu.dstage2_mmu] 342type=ArmStage2MMU 343children=stage2_tlb 344eventq_index=0 345stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 346sys=system 347tlb=system.cpu.dtb 348 349[system.cpu.dstage2_mmu.stage2_tlb] 350type=ArmTLB 351children=walker 352eventq_index=0 353is_stage2=true 354size=32 355walker=system.cpu.dstage2_mmu.stage2_tlb.walker 356 357[system.cpu.dstage2_mmu.stage2_tlb.walker] 358type=ArmTableWalker 359clk_domain=system.cpu_clk_domain 360eventq_index=0 361is_stage2=true 362num_squash_per_cycle=2 363sys=system 364 365[system.cpu.dtb] 366type=ArmTLB 367children=walker 368eventq_index=0 369is_stage2=false 370size=64 371walker=system.cpu.dtb.walker 372 373[system.cpu.dtb.walker] 374type=ArmTableWalker 375clk_domain=system.cpu_clk_domain 376eventq_index=0 377is_stage2=false 378num_squash_per_cycle=2 379sys=system 380port=system.cpu.toL2Bus.slave[3] 381 382[system.cpu.fuPool] 383type=FUPool 384children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 385FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 386eventq_index=0 387 388[system.cpu.fuPool.FUList0] 389type=FUDesc 390children=opList 391count=6 392eventq_index=0 393opList=system.cpu.fuPool.FUList0.opList 394 395[system.cpu.fuPool.FUList0.opList] 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=IntAlu 400opLat=1 401 402[system.cpu.fuPool.FUList1] 403type=FUDesc 404children=opList0 opList1 405count=2 406eventq_index=0 407opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 408 409[system.cpu.fuPool.FUList1.opList0] 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=IntMult 414opLat=3 415 416[system.cpu.fuPool.FUList1.opList1] 417type=OpDesc 418eventq_index=0 419issueLat=19 420opClass=IntDiv 421opLat=20 422 423[system.cpu.fuPool.FUList2] 424type=FUDesc 425children=opList0 opList1 opList2 426count=4 427eventq_index=0 428opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 429 430[system.cpu.fuPool.FUList2.opList0] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=FloatAdd 435opLat=2 436 437[system.cpu.fuPool.FUList2.opList1] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=FloatCmp 442opLat=2 443 444[system.cpu.fuPool.FUList2.opList2] 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=FloatCvt 449opLat=2 450 451[system.cpu.fuPool.FUList3] 452type=FUDesc 453children=opList0 opList1 opList2 454count=2 455eventq_index=0 456opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 457 458[system.cpu.fuPool.FUList3.opList0] 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=FloatMult 463opLat=4 464 465[system.cpu.fuPool.FUList3.opList1] 466type=OpDesc 467eventq_index=0 468issueLat=12 469opClass=FloatDiv 470opLat=12 471 472[system.cpu.fuPool.FUList3.opList2] 473type=OpDesc 474eventq_index=0 475issueLat=24 476opClass=FloatSqrt 477opLat=24 478 479[system.cpu.fuPool.FUList4] 480type=FUDesc 481children=opList 482count=0 483eventq_index=0 484opList=system.cpu.fuPool.FUList4.opList 485 486[system.cpu.fuPool.FUList4.opList] 487type=OpDesc 488eventq_index=0 489issueLat=1 490opClass=MemRead 491opLat=1 492 493[system.cpu.fuPool.FUList5] 494type=FUDesc 495children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 496count=4 497eventq_index=0 498opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 499 500[system.cpu.fuPool.FUList5.opList00] 501type=OpDesc 502eventq_index=0 503issueLat=1 504opClass=SimdAdd 505opLat=1 506 507[system.cpu.fuPool.FUList5.opList01] 508type=OpDesc 509eventq_index=0 510issueLat=1 511opClass=SimdAddAcc 512opLat=1 513 514[system.cpu.fuPool.FUList5.opList02] 515type=OpDesc 516eventq_index=0 517issueLat=1 518opClass=SimdAlu 519opLat=1 520 521[system.cpu.fuPool.FUList5.opList03] 522type=OpDesc 523eventq_index=0 524issueLat=1 525opClass=SimdCmp 526opLat=1 527 528[system.cpu.fuPool.FUList5.opList04] 529type=OpDesc 530eventq_index=0 531issueLat=1 532opClass=SimdCvt 533opLat=1 534 535[system.cpu.fuPool.FUList5.opList05] 536type=OpDesc 537eventq_index=0 538issueLat=1 539opClass=SimdMisc 540opLat=1 541 542[system.cpu.fuPool.FUList5.opList06] 543type=OpDesc 544eventq_index=0 545issueLat=1 546opClass=SimdMult 547opLat=1 548 549[system.cpu.fuPool.FUList5.opList07] 550type=OpDesc 551eventq_index=0 552issueLat=1 553opClass=SimdMultAcc 554opLat=1 555 556[system.cpu.fuPool.FUList5.opList08] 557type=OpDesc 558eventq_index=0 559issueLat=1 560opClass=SimdShift 561opLat=1 562 563[system.cpu.fuPool.FUList5.opList09] 564type=OpDesc 565eventq_index=0 566issueLat=1 567opClass=SimdShiftAcc 568opLat=1 569 570[system.cpu.fuPool.FUList5.opList10] 571type=OpDesc 572eventq_index=0 573issueLat=1 574opClass=SimdSqrt 575opLat=1 576 577[system.cpu.fuPool.FUList5.opList11] 578type=OpDesc 579eventq_index=0 580issueLat=1 581opClass=SimdFloatAdd 582opLat=1 583 584[system.cpu.fuPool.FUList5.opList12] 585type=OpDesc 586eventq_index=0 587issueLat=1 588opClass=SimdFloatAlu 589opLat=1 590 591[system.cpu.fuPool.FUList5.opList13] 592type=OpDesc 593eventq_index=0 594issueLat=1 595opClass=SimdFloatCmp 596opLat=1 597 598[system.cpu.fuPool.FUList5.opList14] 599type=OpDesc 600eventq_index=0 601issueLat=1 602opClass=SimdFloatCvt 603opLat=1 604 605[system.cpu.fuPool.FUList5.opList15] 606type=OpDesc 607eventq_index=0 608issueLat=1 609opClass=SimdFloatDiv 610opLat=1 611 612[system.cpu.fuPool.FUList5.opList16] 613type=OpDesc 614eventq_index=0 615issueLat=1 616opClass=SimdFloatMisc 617opLat=1 618 619[system.cpu.fuPool.FUList5.opList17] 620type=OpDesc 621eventq_index=0 622issueLat=1 623opClass=SimdFloatMult 624opLat=1 625 626[system.cpu.fuPool.FUList5.opList18] 627type=OpDesc 628eventq_index=0 629issueLat=1 630opClass=SimdFloatMultAcc 631opLat=1 632 633[system.cpu.fuPool.FUList5.opList19] 634type=OpDesc 635eventq_index=0 636issueLat=1 637opClass=SimdFloatSqrt 638opLat=1 639 640[system.cpu.fuPool.FUList6] 641type=FUDesc 642children=opList 643count=0 644eventq_index=0 645opList=system.cpu.fuPool.FUList6.opList 646 647[system.cpu.fuPool.FUList6.opList] 648type=OpDesc 649eventq_index=0 650issueLat=1 651opClass=MemWrite 652opLat=1 653 654[system.cpu.fuPool.FUList7] 655type=FUDesc 656children=opList0 opList1 657count=4 658eventq_index=0 659opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 660 661[system.cpu.fuPool.FUList7.opList0] 662type=OpDesc 663eventq_index=0 664issueLat=1 665opClass=MemRead 666opLat=1 667 668[system.cpu.fuPool.FUList7.opList1] 669type=OpDesc 670eventq_index=0 671issueLat=1 672opClass=MemWrite 673opLat=1 674 675[system.cpu.fuPool.FUList8] 676type=FUDesc 677children=opList 678count=1 679eventq_index=0 680opList=system.cpu.fuPool.FUList8.opList 681 682[system.cpu.fuPool.FUList8.opList] 683type=OpDesc 684eventq_index=0 685issueLat=3 686opClass=IprAccess 687opLat=3 688 689[system.cpu.icache] 690type=BaseCache 691children=tags 692addr_ranges=0:18446744073709551615 693assoc=2 694clk_domain=system.cpu_clk_domain 695demand_mshr_reserve=1 696eventq_index=0 697forward_snoops=true 698hit_latency=2 699is_top_level=true 700max_miss_count=0 701mshrs=4 702prefetch_on_access=false 703prefetcher=Null 704response_latency=2 705sequential_access=false 706size=131072 707system=system 708tags=system.cpu.icache.tags 709tgts_per_mshr=20 710two_queue=false 711write_buffers=8 712cpu_side=system.cpu.icache_port 713mem_side=system.cpu.toL2Bus.slave[0] 714 715[system.cpu.icache.tags] 716type=LRU 717assoc=2 718block_size=64 719clk_domain=system.cpu_clk_domain 720eventq_index=0 721hit_latency=2 722sequential_access=false 723size=131072 724 725[system.cpu.interrupts] 726type=ArmInterrupts 727eventq_index=0 728 729[system.cpu.isa] 730type=ArmISA 731eventq_index=0 732fpsid=1090793632 733id_aa64afr0_el1=0 734id_aa64afr1_el1=0 735id_aa64dfr0_el1=1052678 736id_aa64dfr1_el1=0 737id_aa64isar0_el1=0 738id_aa64isar1_el1=0 739id_aa64mmfr0_el1=15728642 740id_aa64mmfr1_el1=0 741id_aa64pfr0_el1=17 742id_aa64pfr1_el1=0 743id_isar0=34607377 744id_isar1=34677009 745id_isar2=555950401 746id_isar3=17899825 747id_isar4=268501314 748id_isar5=0 749id_mmfr0=270536963 750id_mmfr1=0 751id_mmfr2=19070976 752id_mmfr3=34611729 753id_pfr0=49 754id_pfr1=4113 755midr=1091551472 756pmu=Null 757system=system 758 759[system.cpu.istage2_mmu] 760type=ArmStage2MMU 761children=stage2_tlb 762eventq_index=0 763stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 764sys=system 765tlb=system.cpu.itb 766 767[system.cpu.istage2_mmu.stage2_tlb] 768type=ArmTLB 769children=walker 770eventq_index=0 771is_stage2=true 772size=32 773walker=system.cpu.istage2_mmu.stage2_tlb.walker 774 775[system.cpu.istage2_mmu.stage2_tlb.walker] 776type=ArmTableWalker 777clk_domain=system.cpu_clk_domain 778eventq_index=0 779is_stage2=true 780num_squash_per_cycle=2 781sys=system 782 783[system.cpu.itb] 784type=ArmTLB 785children=walker 786eventq_index=0 787is_stage2=false 788size=64 789walker=system.cpu.itb.walker 790 791[system.cpu.itb.walker] 792type=ArmTableWalker 793clk_domain=system.cpu_clk_domain 794eventq_index=0 795is_stage2=false 796num_squash_per_cycle=2 797sys=system 798port=system.cpu.toL2Bus.slave[2] 799 800[system.cpu.l2cache] 801type=BaseCache 802children=tags 803addr_ranges=0:18446744073709551615 804assoc=8 805clk_domain=system.cpu_clk_domain 806demand_mshr_reserve=1 807eventq_index=0 808forward_snoops=true 809hit_latency=20 810is_top_level=false 811max_miss_count=0 812mshrs=20 813prefetch_on_access=false 814prefetcher=Null 815response_latency=20 816sequential_access=false 817size=2097152 818system=system 819tags=system.cpu.l2cache.tags 820tgts_per_mshr=12 821two_queue=false 822write_buffers=8 823cpu_side=system.cpu.toL2Bus.master[0] 824mem_side=system.membus.slave[1] 825 826[system.cpu.l2cache.tags] 827type=LRU 828assoc=8 829block_size=64 830clk_domain=system.cpu_clk_domain 831eventq_index=0 832hit_latency=20 833sequential_access=false 834size=2097152 835 836[system.cpu.toL2Bus] 837type=CoherentXBar 838clk_domain=system.cpu_clk_domain 839eventq_index=0 840forward_latency=0 841frontend_latency=1 842response_latency=1 843snoop_filter=Null 844snoop_response_latency=1 845system=system 846use_default_range=false 847width=32 848master=system.cpu.l2cache.cpu_side 849slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 850 851[system.cpu.tracer] 852type=ExeTracer 853eventq_index=0 854 855[system.cpu.workload] 856type=LiveProcess 857cmd=hello 858cwd= 859drivers= 860egid=100 861env= 862errout=cerr 863euid=100 864eventq_index=0 865executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello 866gid=100 867input=cin 868kvmInSE=false 869max_stack_size=67108864 870output=cout 871pid=100 872ppid=99 873simpoint=0 874system=system 875uid=100 876useArchPT=false 877 878[system.cpu_clk_domain] 879type=SrcClockDomain 880clock=500 881domain_id=-1 882eventq_index=0 883init_perf_level=0 884voltage_domain=system.voltage_domain 885 886[system.dvfs_handler] 887type=DVFSHandler 888domains= 889enable=false 890eventq_index=0 891sys_clk_domain=system.clk_domain 892transition_latency=100000000 893 894[system.membus] 895type=CoherentXBar 896clk_domain=system.clk_domain 897eventq_index=0 898forward_latency=4 899frontend_latency=3 900response_latency=2 901snoop_filter=Null 902snoop_response_latency=4 903system=system 904use_default_range=false 905width=16 906master=system.physmem.port 907slave=system.system_port system.cpu.l2cache.mem_side 908 909[system.physmem] 910type=DRAMCtrl 911IDD0=0.075000 912IDD02=0.000000 913IDD2N=0.050000 914IDD2N2=0.000000 915IDD2P0=0.000000 916IDD2P02=0.000000 917IDD2P1=0.000000 918IDD2P12=0.000000 919IDD3N=0.057000 920IDD3N2=0.000000 921IDD3P0=0.000000 922IDD3P02=0.000000 923IDD3P1=0.000000 924IDD3P12=0.000000 925IDD4R=0.187000 926IDD4R2=0.000000 927IDD4W=0.165000 928IDD4W2=0.000000 929IDD5=0.220000 930IDD52=0.000000 931IDD6=0.000000 932IDD62=0.000000 933VDD=1.500000 934VDD2=0.000000 935activation_limit=4 936addr_mapping=RoRaBaCoCh 937bank_groups_per_rank=0 938banks_per_rank=8 939burst_length=8 940channels=1 941clk_domain=system.clk_domain 942conf_table_reported=true 943device_bus_width=8 944device_rowbuffer_size=1024 945device_size=536870912 946devices_per_rank=8 947dll=true 948eventq_index=0 949in_addr_map=true 950max_accesses_per_row=16 951mem_sched_policy=frfcfs 952min_writes_per_switch=16 953null=false 954page_policy=open_adaptive 955range=0:134217727 956ranks_per_channel=2 957read_buffer_size=32 958static_backend_latency=10000 959static_frontend_latency=10000 960tBURST=5000 961tCCD_L=0 962tCK=1250 963tCL=13750 964tCS=2500 965tRAS=35000 966tRCD=13750 967tREFI=7800000 968tRFC=260000 969tRP=13750 970tRRD=6000 971tRRD_L=0 972tRTP=7500 973tRTW=2500 974tWR=15000 975tWTR=7500 976tXAW=30000 977tXP=0 978tXPDLL=0 979tXS=0 980tXSDLL=0 981write_buffer_size=64 982write_high_thresh_perc=85 983write_low_thresh_perc=50 984port=system.membus.master[0] 985 986[system.voltage_domain] 987type=VoltageDomain 988eventq_index=0 989voltage=1.000000 990 991