config.ini revision 10451
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=system.cpu.checker 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dstage2_mmu=system.cpu.dstage2_mmu 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94istage2_mmu=system.cpu.istage2_mmu 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=64 102numPhysCCRegs=1280 103numPhysFloatRegs=256 104numPhysIntRegs=256 105numROBEntries=192 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=2 113renameToROBDelay=1 114renameWidth=8 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=BranchPredictor 139BTBEntries=4096 140BTBTagSize=16 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152predType=tournament 153 154[system.cpu.checker] 155type=O3Checker 156children=dstage2_mmu dtb isa istage2_mmu itb tracer 157checker=Null 158clk_domain=system.cpu_clk_domain 159cpu_id=0 160do_checkpoint_insts=true 161do_quiesce=true 162do_statistics_insts=true 163dstage2_mmu=system.cpu.checker.dstage2_mmu 164dtb=system.cpu.checker.dtb 165eventq_index=0 166exitOnError=false 167function_trace=false 168function_trace_start=0 169interrupts=Null 170isa=system.cpu.checker.isa 171istage2_mmu=system.cpu.checker.istage2_mmu 172itb=system.cpu.checker.itb 173max_insts_all_threads=0 174max_insts_any_thread=0 175max_loads_all_threads=0 176max_loads_any_thread=0 177numThreads=1 178profile=0 179progress_interval=0 180simpoint_start_insts= 181socket_id=0 182switched_out=false 183system=system 184tracer=system.cpu.checker.tracer 185updateOnError=true 186warnOnlyOnLoadError=true 187workload=system.cpu.workload 188 189[system.cpu.checker.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 194tlb=system.cpu.checker.dtb 195 196[system.cpu.checker.dstage2_mmu.stage2_tlb] 197type=ArmTLB 198children=walker 199eventq_index=0 200is_stage2=true 201size=32 202walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 203 204[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 205type=ArmTableWalker 206clk_domain=system.cpu_clk_domain 207eventq_index=0 208is_stage2=true 209num_squash_per_cycle=2 210sys=system 211port=system.cpu.toL2Bus.slave[9] 212 213[system.cpu.checker.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.checker.dtb.walker 220 221[system.cpu.checker.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system 228port=system.cpu.toL2Bus.slave[7] 229 230[system.cpu.checker.isa] 231type=ArmISA 232eventq_index=0 233fpsid=1090793632 234id_aa64afr0_el1=0 235id_aa64afr1_el1=0 236id_aa64dfr0_el1=1052678 237id_aa64dfr1_el1=0 238id_aa64isar0_el1=0 239id_aa64isar1_el1=0 240id_aa64mmfr0_el1=15728642 241id_aa64mmfr1_el1=0 242id_aa64pfr0_el1=17 243id_aa64pfr1_el1=0 244id_isar0=34607377 245id_isar1=34677009 246id_isar2=555950401 247id_isar3=17899825 248id_isar4=268501314 249id_isar5=0 250id_mmfr0=270536963 251id_mmfr1=0 252id_mmfr2=19070976 253id_mmfr3=34611729 254id_pfr0=49 255id_pfr1=4113 256midr=1091551472 257system=system 258 259[system.cpu.checker.istage2_mmu] 260type=ArmStage2MMU 261children=stage2_tlb 262eventq_index=0 263stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 264tlb=system.cpu.checker.itb 265 266[system.cpu.checker.istage2_mmu.stage2_tlb] 267type=ArmTLB 268children=walker 269eventq_index=0 270is_stage2=true 271size=32 272walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 273 274[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 275type=ArmTableWalker 276clk_domain=system.cpu_clk_domain 277eventq_index=0 278is_stage2=true 279num_squash_per_cycle=2 280sys=system 281port=system.cpu.toL2Bus.slave[8] 282 283[system.cpu.checker.itb] 284type=ArmTLB 285children=walker 286eventq_index=0 287is_stage2=false 288size=64 289walker=system.cpu.checker.itb.walker 290 291[system.cpu.checker.itb.walker] 292type=ArmTableWalker 293clk_domain=system.cpu_clk_domain 294eventq_index=0 295is_stage2=false 296num_squash_per_cycle=2 297sys=system 298port=system.cpu.toL2Bus.slave[6] 299 300[system.cpu.checker.tracer] 301type=ExeTracer 302eventq_index=0 303 304[system.cpu.dcache] 305type=BaseCache 306children=tags 307addr_ranges=0:18446744073709551615 308assoc=2 309clk_domain=system.cpu_clk_domain 310eventq_index=0 311forward_snoops=true 312hit_latency=2 313is_top_level=true 314max_miss_count=0 315mshrs=4 316prefetch_on_access=false 317prefetcher=Null 318response_latency=2 319sequential_access=false 320size=262144 321system=system 322tags=system.cpu.dcache.tags 323tgts_per_mshr=20 324two_queue=false 325write_buffers=8 326cpu_side=system.cpu.dcache_port 327mem_side=system.cpu.toL2Bus.slave[1] 328 329[system.cpu.dcache.tags] 330type=LRU 331assoc=2 332block_size=64 333clk_domain=system.cpu_clk_domain 334eventq_index=0 335hit_latency=2 336sequential_access=false 337size=262144 338 339[system.cpu.dstage2_mmu] 340type=ArmStage2MMU 341children=stage2_tlb 342eventq_index=0 343stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 344tlb=system.cpu.dtb 345 346[system.cpu.dstage2_mmu.stage2_tlb] 347type=ArmTLB 348children=walker 349eventq_index=0 350is_stage2=true 351size=32 352walker=system.cpu.dstage2_mmu.stage2_tlb.walker 353 354[system.cpu.dstage2_mmu.stage2_tlb.walker] 355type=ArmTableWalker 356clk_domain=system.cpu_clk_domain 357eventq_index=0 358is_stage2=true 359num_squash_per_cycle=2 360sys=system 361port=system.cpu.toL2Bus.slave[5] 362 363[system.cpu.dtb] 364type=ArmTLB 365children=walker 366eventq_index=0 367is_stage2=false 368size=64 369walker=system.cpu.dtb.walker 370 371[system.cpu.dtb.walker] 372type=ArmTableWalker 373clk_domain=system.cpu_clk_domain 374eventq_index=0 375is_stage2=false 376num_squash_per_cycle=2 377sys=system 378port=system.cpu.toL2Bus.slave[3] 379 380[system.cpu.fuPool] 381type=FUPool 382children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 383FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 384eventq_index=0 385 386[system.cpu.fuPool.FUList0] 387type=FUDesc 388children=opList 389count=6 390eventq_index=0 391opList=system.cpu.fuPool.FUList0.opList 392 393[system.cpu.fuPool.FUList0.opList] 394type=OpDesc 395eventq_index=0 396issueLat=1 397opClass=IntAlu 398opLat=1 399 400[system.cpu.fuPool.FUList1] 401type=FUDesc 402children=opList0 opList1 403count=2 404eventq_index=0 405opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 406 407[system.cpu.fuPool.FUList1.opList0] 408type=OpDesc 409eventq_index=0 410issueLat=1 411opClass=IntMult 412opLat=3 413 414[system.cpu.fuPool.FUList1.opList1] 415type=OpDesc 416eventq_index=0 417issueLat=19 418opClass=IntDiv 419opLat=20 420 421[system.cpu.fuPool.FUList2] 422type=FUDesc 423children=opList0 opList1 opList2 424count=4 425eventq_index=0 426opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 427 428[system.cpu.fuPool.FUList2.opList0] 429type=OpDesc 430eventq_index=0 431issueLat=1 432opClass=FloatAdd 433opLat=2 434 435[system.cpu.fuPool.FUList2.opList1] 436type=OpDesc 437eventq_index=0 438issueLat=1 439opClass=FloatCmp 440opLat=2 441 442[system.cpu.fuPool.FUList2.opList2] 443type=OpDesc 444eventq_index=0 445issueLat=1 446opClass=FloatCvt 447opLat=2 448 449[system.cpu.fuPool.FUList3] 450type=FUDesc 451children=opList0 opList1 opList2 452count=2 453eventq_index=0 454opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 455 456[system.cpu.fuPool.FUList3.opList0] 457type=OpDesc 458eventq_index=0 459issueLat=1 460opClass=FloatMult 461opLat=4 462 463[system.cpu.fuPool.FUList3.opList1] 464type=OpDesc 465eventq_index=0 466issueLat=12 467opClass=FloatDiv 468opLat=12 469 470[system.cpu.fuPool.FUList3.opList2] 471type=OpDesc 472eventq_index=0 473issueLat=24 474opClass=FloatSqrt 475opLat=24 476 477[system.cpu.fuPool.FUList4] 478type=FUDesc 479children=opList 480count=0 481eventq_index=0 482opList=system.cpu.fuPool.FUList4.opList 483 484[system.cpu.fuPool.FUList4.opList] 485type=OpDesc 486eventq_index=0 487issueLat=1 488opClass=MemRead 489opLat=1 490 491[system.cpu.fuPool.FUList5] 492type=FUDesc 493children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 494count=4 495eventq_index=0 496opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 497 498[system.cpu.fuPool.FUList5.opList00] 499type=OpDesc 500eventq_index=0 501issueLat=1 502opClass=SimdAdd 503opLat=1 504 505[system.cpu.fuPool.FUList5.opList01] 506type=OpDesc 507eventq_index=0 508issueLat=1 509opClass=SimdAddAcc 510opLat=1 511 512[system.cpu.fuPool.FUList5.opList02] 513type=OpDesc 514eventq_index=0 515issueLat=1 516opClass=SimdAlu 517opLat=1 518 519[system.cpu.fuPool.FUList5.opList03] 520type=OpDesc 521eventq_index=0 522issueLat=1 523opClass=SimdCmp 524opLat=1 525 526[system.cpu.fuPool.FUList5.opList04] 527type=OpDesc 528eventq_index=0 529issueLat=1 530opClass=SimdCvt 531opLat=1 532 533[system.cpu.fuPool.FUList5.opList05] 534type=OpDesc 535eventq_index=0 536issueLat=1 537opClass=SimdMisc 538opLat=1 539 540[system.cpu.fuPool.FUList5.opList06] 541type=OpDesc 542eventq_index=0 543issueLat=1 544opClass=SimdMult 545opLat=1 546 547[system.cpu.fuPool.FUList5.opList07] 548type=OpDesc 549eventq_index=0 550issueLat=1 551opClass=SimdMultAcc 552opLat=1 553 554[system.cpu.fuPool.FUList5.opList08] 555type=OpDesc 556eventq_index=0 557issueLat=1 558opClass=SimdShift 559opLat=1 560 561[system.cpu.fuPool.FUList5.opList09] 562type=OpDesc 563eventq_index=0 564issueLat=1 565opClass=SimdShiftAcc 566opLat=1 567 568[system.cpu.fuPool.FUList5.opList10] 569type=OpDesc 570eventq_index=0 571issueLat=1 572opClass=SimdSqrt 573opLat=1 574 575[system.cpu.fuPool.FUList5.opList11] 576type=OpDesc 577eventq_index=0 578issueLat=1 579opClass=SimdFloatAdd 580opLat=1 581 582[system.cpu.fuPool.FUList5.opList12] 583type=OpDesc 584eventq_index=0 585issueLat=1 586opClass=SimdFloatAlu 587opLat=1 588 589[system.cpu.fuPool.FUList5.opList13] 590type=OpDesc 591eventq_index=0 592issueLat=1 593opClass=SimdFloatCmp 594opLat=1 595 596[system.cpu.fuPool.FUList5.opList14] 597type=OpDesc 598eventq_index=0 599issueLat=1 600opClass=SimdFloatCvt 601opLat=1 602 603[system.cpu.fuPool.FUList5.opList15] 604type=OpDesc 605eventq_index=0 606issueLat=1 607opClass=SimdFloatDiv 608opLat=1 609 610[system.cpu.fuPool.FUList5.opList16] 611type=OpDesc 612eventq_index=0 613issueLat=1 614opClass=SimdFloatMisc 615opLat=1 616 617[system.cpu.fuPool.FUList5.opList17] 618type=OpDesc 619eventq_index=0 620issueLat=1 621opClass=SimdFloatMult 622opLat=1 623 624[system.cpu.fuPool.FUList5.opList18] 625type=OpDesc 626eventq_index=0 627issueLat=1 628opClass=SimdFloatMultAcc 629opLat=1 630 631[system.cpu.fuPool.FUList5.opList19] 632type=OpDesc 633eventq_index=0 634issueLat=1 635opClass=SimdFloatSqrt 636opLat=1 637 638[system.cpu.fuPool.FUList6] 639type=FUDesc 640children=opList 641count=0 642eventq_index=0 643opList=system.cpu.fuPool.FUList6.opList 644 645[system.cpu.fuPool.FUList6.opList] 646type=OpDesc 647eventq_index=0 648issueLat=1 649opClass=MemWrite 650opLat=1 651 652[system.cpu.fuPool.FUList7] 653type=FUDesc 654children=opList0 opList1 655count=4 656eventq_index=0 657opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 658 659[system.cpu.fuPool.FUList7.opList0] 660type=OpDesc 661eventq_index=0 662issueLat=1 663opClass=MemRead 664opLat=1 665 666[system.cpu.fuPool.FUList7.opList1] 667type=OpDesc 668eventq_index=0 669issueLat=1 670opClass=MemWrite 671opLat=1 672 673[system.cpu.fuPool.FUList8] 674type=FUDesc 675children=opList 676count=1 677eventq_index=0 678opList=system.cpu.fuPool.FUList8.opList 679 680[system.cpu.fuPool.FUList8.opList] 681type=OpDesc 682eventq_index=0 683issueLat=3 684opClass=IprAccess 685opLat=3 686 687[system.cpu.icache] 688type=BaseCache 689children=tags 690addr_ranges=0:18446744073709551615 691assoc=2 692clk_domain=system.cpu_clk_domain 693eventq_index=0 694forward_snoops=true 695hit_latency=2 696is_top_level=true 697max_miss_count=0 698mshrs=4 699prefetch_on_access=false 700prefetcher=Null 701response_latency=2 702sequential_access=false 703size=131072 704system=system 705tags=system.cpu.icache.tags 706tgts_per_mshr=20 707two_queue=false 708write_buffers=8 709cpu_side=system.cpu.icache_port 710mem_side=system.cpu.toL2Bus.slave[0] 711 712[system.cpu.icache.tags] 713type=LRU 714assoc=2 715block_size=64 716clk_domain=system.cpu_clk_domain 717eventq_index=0 718hit_latency=2 719sequential_access=false 720size=131072 721 722[system.cpu.interrupts] 723type=ArmInterrupts 724eventq_index=0 725 726[system.cpu.isa] 727type=ArmISA 728eventq_index=0 729fpsid=1090793632 730id_aa64afr0_el1=0 731id_aa64afr1_el1=0 732id_aa64dfr0_el1=1052678 733id_aa64dfr1_el1=0 734id_aa64isar0_el1=0 735id_aa64isar1_el1=0 736id_aa64mmfr0_el1=15728642 737id_aa64mmfr1_el1=0 738id_aa64pfr0_el1=17 739id_aa64pfr1_el1=0 740id_isar0=34607377 741id_isar1=34677009 742id_isar2=555950401 743id_isar3=17899825 744id_isar4=268501314 745id_isar5=0 746id_mmfr0=270536963 747id_mmfr1=0 748id_mmfr2=19070976 749id_mmfr3=34611729 750id_pfr0=49 751id_pfr1=4113 752midr=1091551472 753system=system 754 755[system.cpu.istage2_mmu] 756type=ArmStage2MMU 757children=stage2_tlb 758eventq_index=0 759stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 760tlb=system.cpu.itb 761 762[system.cpu.istage2_mmu.stage2_tlb] 763type=ArmTLB 764children=walker 765eventq_index=0 766is_stage2=true 767size=32 768walker=system.cpu.istage2_mmu.stage2_tlb.walker 769 770[system.cpu.istage2_mmu.stage2_tlb.walker] 771type=ArmTableWalker 772clk_domain=system.cpu_clk_domain 773eventq_index=0 774is_stage2=true 775num_squash_per_cycle=2 776sys=system 777port=system.cpu.toL2Bus.slave[4] 778 779[system.cpu.itb] 780type=ArmTLB 781children=walker 782eventq_index=0 783is_stage2=false 784size=64 785walker=system.cpu.itb.walker 786 787[system.cpu.itb.walker] 788type=ArmTableWalker 789clk_domain=system.cpu_clk_domain 790eventq_index=0 791is_stage2=false 792num_squash_per_cycle=2 793sys=system 794port=system.cpu.toL2Bus.slave[2] 795 796[system.cpu.l2cache] 797type=BaseCache 798children=tags 799addr_ranges=0:18446744073709551615 800assoc=8 801clk_domain=system.cpu_clk_domain 802eventq_index=0 803forward_snoops=true 804hit_latency=20 805is_top_level=false 806max_miss_count=0 807mshrs=20 808prefetch_on_access=false 809prefetcher=Null 810response_latency=20 811sequential_access=false 812size=2097152 813system=system 814tags=system.cpu.l2cache.tags 815tgts_per_mshr=12 816two_queue=false 817write_buffers=8 818cpu_side=system.cpu.toL2Bus.master[0] 819mem_side=system.membus.slave[1] 820 821[system.cpu.l2cache.tags] 822type=LRU 823assoc=8 824block_size=64 825clk_domain=system.cpu_clk_domain 826eventq_index=0 827hit_latency=20 828sequential_access=false 829size=2097152 830 831[system.cpu.toL2Bus] 832type=CoherentXBar 833clk_domain=system.cpu_clk_domain 834eventq_index=0 835header_cycles=1 836snoop_filter=Null 837system=system 838use_default_range=false 839width=32 840master=system.cpu.l2cache.cpu_side 841slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port 842 843[system.cpu.tracer] 844type=ExeTracer 845eventq_index=0 846 847[system.cpu.workload] 848type=LiveProcess 849cmd=hello 850cwd= 851egid=100 852env= 853errout=cerr 854euid=100 855eventq_index=0 856executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 857gid=100 858input=cin 859max_stack_size=67108864 860output=cout 861pid=100 862ppid=99 863simpoint=0 864system=system 865uid=100 866useArchPT=false 867 868[system.cpu_clk_domain] 869type=SrcClockDomain 870clock=500 871domain_id=-1 872eventq_index=0 873init_perf_level=0 874voltage_domain=system.voltage_domain 875 876[system.dvfs_handler] 877type=DVFSHandler 878domains= 879enable=false 880eventq_index=0 881sys_clk_domain=system.clk_domain 882transition_latency=100000000 883 884[system.membus] 885type=CoherentXBar 886clk_domain=system.clk_domain 887eventq_index=0 888header_cycles=1 889snoop_filter=Null 890system=system 891use_default_range=false 892width=8 893master=system.physmem.port 894slave=system.system_port system.cpu.l2cache.mem_side 895 896[system.physmem] 897type=DRAMCtrl 898IDD0=0.075000 899IDD02=0.000000 900IDD2N=0.050000 901IDD2N2=0.000000 902IDD2P0=0.000000 903IDD2P02=0.000000 904IDD2P1=0.000000 905IDD2P12=0.000000 906IDD3N=0.057000 907IDD3N2=0.000000 908IDD3P0=0.000000 909IDD3P02=0.000000 910IDD3P1=0.000000 911IDD3P12=0.000000 912IDD4R=0.187000 913IDD4R2=0.000000 914IDD4W=0.165000 915IDD4W2=0.000000 916IDD5=0.220000 917IDD52=0.000000 918IDD6=0.000000 919IDD62=0.000000 920VDD=1.500000 921VDD2=0.000000 922activation_limit=4 923addr_mapping=RoRaBaChCo 924bank_groups_per_rank=0 925banks_per_rank=8 926burst_length=8 927channels=1 928clk_domain=system.clk_domain 929conf_table_reported=true 930device_bus_width=8 931device_rowbuffer_size=1024 932devices_per_rank=8 933dll=true 934eventq_index=0 935in_addr_map=true 936max_accesses_per_row=16 937mem_sched_policy=frfcfs 938min_writes_per_switch=16 939null=false 940page_policy=open_adaptive 941range=0:134217727 942ranks_per_channel=2 943read_buffer_size=32 944static_backend_latency=10000 945static_frontend_latency=10000 946tBURST=5000 947tCCD_L=0 948tCK=1250 949tCL=13750 950tCS=2500 951tRAS=35000 952tRCD=13750 953tREFI=7800000 954tRFC=260000 955tRP=13750 956tRRD=6000 957tRRD_L=0 958tRTP=7500 959tRTW=2500 960tWR=15000 961tWTR=7500 962tXAW=30000 963tXP=0 964tXPDLL=0 965tXS=0 966tXSDLL=0 967write_buffer_size=64 968write_high_thresh_perc=85 969write_low_thresh_perc=50 970port=system.membus.master[0] 971 972[system.voltage_domain] 973type=VoltageDomain 974eventq_index=0 975voltage=1.000000 976 977