config.ini revision 10242
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=DerivO3CPU 45children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52activity=0 53backComSize=5 54branchPred=system.cpu.branchPred 55cachePorts=200 56checker=system.cpu.checker 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dstage2_mmu=system.cpu.dstage2_mmu 72dtb=system.cpu.dtb 73eventq_index=0 74fetchBufferSize=64 75fetchToDecodeDelay=1 76fetchTrapLatency=1 77fetchWidth=8 78forwardComSize=5 79fuPool=system.cpu.fuPool 80function_trace=false 81function_trace_start=0 82iewToCommitDelay=1 83iewToDecodeDelay=1 84iewToFetchDelay=1 85iewToRenameDelay=1 86interrupts=system.cpu.interrupts 87isa=system.cpu.isa 88issueToExecuteDelay=1 89issueWidth=8 90istage2_mmu=system.cpu.istage2_mmu 91itb=system.cpu.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysCCRegs=0 99numPhysFloatRegs=256 100numPhysIntRegs=256 101numROBEntries=192 102numRobs=1 103numThreads=1 104profile=0 105progress_interval=0 106renameToDecodeDelay=1 107renameToFetchDelay=1 108renameToIEWDelay=2 109renameToROBDelay=1 110renameWidth=8 111simpoint_start_insts= 112smtCommitPolicy=RoundRobin 113smtFetchPolicy=SingleThread 114smtIQPolicy=Partitioned 115smtIQThreshold=100 116smtLSQPolicy=Partitioned 117smtLSQThreshold=100 118smtNumFetchingThreads=1 119smtROBPolicy=Partitioned 120smtROBThreshold=100 121socket_id=0 122squashWidth=8 123store_set_clear_period=250000 124switched_out=false 125system=system 126tracer=system.cpu.tracer 127trapLatency=13 128wbDepth=1 129wbWidth=8 130workload=system.cpu.workload 131dcache_port=system.cpu.dcache.cpu_side 132icache_port=system.cpu.icache.cpu_side 133 134[system.cpu.branchPred] 135type=BranchPredictor 136BTBEntries=4096 137BTBTagSize=16 138RASSize=16 139choiceCtrBits=2 140choicePredictorSize=8192 141eventq_index=0 142globalCtrBits=2 143globalPredictorSize=8192 144instShiftAmt=2 145localCtrBits=2 146localHistoryTableSize=2048 147localPredictorSize=2048 148numThreads=1 149predType=tournament 150 151[system.cpu.checker] 152type=O3Checker 153children=dstage2_mmu dtb isa istage2_mmu itb tracer 154checker=Null 155clk_domain=system.cpu_clk_domain 156cpu_id=0 157do_checkpoint_insts=true 158do_quiesce=true 159do_statistics_insts=true 160dstage2_mmu=system.cpu.checker.dstage2_mmu 161dtb=system.cpu.checker.dtb 162eventq_index=0 163exitOnError=false 164function_trace=false 165function_trace_start=0 166interrupts=Null 167isa=system.cpu.checker.isa 168istage2_mmu=system.cpu.checker.istage2_mmu 169itb=system.cpu.checker.itb 170max_insts_all_threads=0 171max_insts_any_thread=0 172max_loads_all_threads=0 173max_loads_any_thread=0 174numThreads=1 175profile=0 176progress_interval=0 177simpoint_start_insts= 178socket_id=0 179switched_out=false 180system=system 181tracer=system.cpu.checker.tracer 182updateOnError=true 183warnOnlyOnLoadError=true 184workload=system.cpu.workload 185 186[system.cpu.checker.dstage2_mmu] 187type=ArmStage2MMU 188children=stage2_tlb 189eventq_index=0 190stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 191tlb=system.cpu.checker.dtb 192 193[system.cpu.checker.dstage2_mmu.stage2_tlb] 194type=ArmTLB 195children=walker 196eventq_index=0 197is_stage2=true 198size=32 199walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 200 201[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 202type=ArmTableWalker 203clk_domain=system.cpu_clk_domain 204eventq_index=0 205is_stage2=true 206num_squash_per_cycle=2 207sys=system 208port=system.cpu.toL2Bus.slave[9] 209 210[system.cpu.checker.dtb] 211type=ArmTLB 212children=walker 213eventq_index=0 214is_stage2=false 215size=64 216walker=system.cpu.checker.dtb.walker 217 218[system.cpu.checker.dtb.walker] 219type=ArmTableWalker 220clk_domain=system.cpu_clk_domain 221eventq_index=0 222is_stage2=false 223num_squash_per_cycle=2 224sys=system 225port=system.cpu.toL2Bus.slave[7] 226 227[system.cpu.checker.isa] 228type=ArmISA 229eventq_index=0 230fpsid=1090793632 231id_aa64afr0_el1=0 232id_aa64afr1_el1=0 233id_aa64dfr0_el1=1052678 234id_aa64dfr1_el1=0 235id_aa64isar0_el1=0 236id_aa64isar1_el1=0 237id_aa64mmfr0_el1=15728642 238id_aa64mmfr1_el1=0 239id_aa64pfr0_el1=17 240id_aa64pfr1_el1=0 241id_isar0=34607377 242id_isar1=34677009 243id_isar2=555950401 244id_isar3=17899825 245id_isar4=268501314 246id_isar5=0 247id_mmfr0=270536963 248id_mmfr1=0 249id_mmfr2=19070976 250id_mmfr3=34611729 251id_pfr0=49 252id_pfr1=4113 253midr=1091551472 254system=system 255 256[system.cpu.checker.istage2_mmu] 257type=ArmStage2MMU 258children=stage2_tlb 259eventq_index=0 260stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 261tlb=system.cpu.checker.itb 262 263[system.cpu.checker.istage2_mmu.stage2_tlb] 264type=ArmTLB 265children=walker 266eventq_index=0 267is_stage2=true 268size=32 269walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 270 271[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 272type=ArmTableWalker 273clk_domain=system.cpu_clk_domain 274eventq_index=0 275is_stage2=true 276num_squash_per_cycle=2 277sys=system 278port=system.cpu.toL2Bus.slave[8] 279 280[system.cpu.checker.itb] 281type=ArmTLB 282children=walker 283eventq_index=0 284is_stage2=false 285size=64 286walker=system.cpu.checker.itb.walker 287 288[system.cpu.checker.itb.walker] 289type=ArmTableWalker 290clk_domain=system.cpu_clk_domain 291eventq_index=0 292is_stage2=false 293num_squash_per_cycle=2 294sys=system 295port=system.cpu.toL2Bus.slave[6] 296 297[system.cpu.checker.tracer] 298type=ExeTracer 299eventq_index=0 300 301[system.cpu.dcache] 302type=BaseCache 303children=tags 304addr_ranges=0:18446744073709551615 305assoc=2 306clk_domain=system.cpu_clk_domain 307eventq_index=0 308forward_snoops=true 309hit_latency=2 310is_top_level=true 311max_miss_count=0 312mshrs=4 313prefetch_on_access=false 314prefetcher=Null 315response_latency=2 316sequential_access=false 317size=262144 318system=system 319tags=system.cpu.dcache.tags 320tgts_per_mshr=20 321two_queue=false 322write_buffers=8 323cpu_side=system.cpu.dcache_port 324mem_side=system.cpu.toL2Bus.slave[1] 325 326[system.cpu.dcache.tags] 327type=LRU 328assoc=2 329block_size=64 330clk_domain=system.cpu_clk_domain 331eventq_index=0 332hit_latency=2 333sequential_access=false 334size=262144 335 336[system.cpu.dstage2_mmu] 337type=ArmStage2MMU 338children=stage2_tlb 339eventq_index=0 340stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 341tlb=system.cpu.dtb 342 343[system.cpu.dstage2_mmu.stage2_tlb] 344type=ArmTLB 345children=walker 346eventq_index=0 347is_stage2=true 348size=32 349walker=system.cpu.dstage2_mmu.stage2_tlb.walker 350 351[system.cpu.dstage2_mmu.stage2_tlb.walker] 352type=ArmTableWalker 353clk_domain=system.cpu_clk_domain 354eventq_index=0 355is_stage2=true 356num_squash_per_cycle=2 357sys=system 358port=system.cpu.toL2Bus.slave[5] 359 360[system.cpu.dtb] 361type=ArmTLB 362children=walker 363eventq_index=0 364is_stage2=false 365size=64 366walker=system.cpu.dtb.walker 367 368[system.cpu.dtb.walker] 369type=ArmTableWalker 370clk_domain=system.cpu_clk_domain 371eventq_index=0 372is_stage2=false 373num_squash_per_cycle=2 374sys=system 375port=system.cpu.toL2Bus.slave[3] 376 377[system.cpu.fuPool] 378type=FUPool 379children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 380FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 381eventq_index=0 382 383[system.cpu.fuPool.FUList0] 384type=FUDesc 385children=opList 386count=6 387eventq_index=0 388opList=system.cpu.fuPool.FUList0.opList 389 390[system.cpu.fuPool.FUList0.opList] 391type=OpDesc 392eventq_index=0 393issueLat=1 394opClass=IntAlu 395opLat=1 396 397[system.cpu.fuPool.FUList1] 398type=FUDesc 399children=opList0 opList1 400count=2 401eventq_index=0 402opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 403 404[system.cpu.fuPool.FUList1.opList0] 405type=OpDesc 406eventq_index=0 407issueLat=1 408opClass=IntMult 409opLat=3 410 411[system.cpu.fuPool.FUList1.opList1] 412type=OpDesc 413eventq_index=0 414issueLat=19 415opClass=IntDiv 416opLat=20 417 418[system.cpu.fuPool.FUList2] 419type=FUDesc 420children=opList0 opList1 opList2 421count=4 422eventq_index=0 423opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 424 425[system.cpu.fuPool.FUList2.opList0] 426type=OpDesc 427eventq_index=0 428issueLat=1 429opClass=FloatAdd 430opLat=2 431 432[system.cpu.fuPool.FUList2.opList1] 433type=OpDesc 434eventq_index=0 435issueLat=1 436opClass=FloatCmp 437opLat=2 438 439[system.cpu.fuPool.FUList2.opList2] 440type=OpDesc 441eventq_index=0 442issueLat=1 443opClass=FloatCvt 444opLat=2 445 446[system.cpu.fuPool.FUList3] 447type=FUDesc 448children=opList0 opList1 opList2 449count=2 450eventq_index=0 451opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 452 453[system.cpu.fuPool.FUList3.opList0] 454type=OpDesc 455eventq_index=0 456issueLat=1 457opClass=FloatMult 458opLat=4 459 460[system.cpu.fuPool.FUList3.opList1] 461type=OpDesc 462eventq_index=0 463issueLat=12 464opClass=FloatDiv 465opLat=12 466 467[system.cpu.fuPool.FUList3.opList2] 468type=OpDesc 469eventq_index=0 470issueLat=24 471opClass=FloatSqrt 472opLat=24 473 474[system.cpu.fuPool.FUList4] 475type=FUDesc 476children=opList 477count=0 478eventq_index=0 479opList=system.cpu.fuPool.FUList4.opList 480 481[system.cpu.fuPool.FUList4.opList] 482type=OpDesc 483eventq_index=0 484issueLat=1 485opClass=MemRead 486opLat=1 487 488[system.cpu.fuPool.FUList5] 489type=FUDesc 490children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 491count=4 492eventq_index=0 493opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 494 495[system.cpu.fuPool.FUList5.opList00] 496type=OpDesc 497eventq_index=0 498issueLat=1 499opClass=SimdAdd 500opLat=1 501 502[system.cpu.fuPool.FUList5.opList01] 503type=OpDesc 504eventq_index=0 505issueLat=1 506opClass=SimdAddAcc 507opLat=1 508 509[system.cpu.fuPool.FUList5.opList02] 510type=OpDesc 511eventq_index=0 512issueLat=1 513opClass=SimdAlu 514opLat=1 515 516[system.cpu.fuPool.FUList5.opList03] 517type=OpDesc 518eventq_index=0 519issueLat=1 520opClass=SimdCmp 521opLat=1 522 523[system.cpu.fuPool.FUList5.opList04] 524type=OpDesc 525eventq_index=0 526issueLat=1 527opClass=SimdCvt 528opLat=1 529 530[system.cpu.fuPool.FUList5.opList05] 531type=OpDesc 532eventq_index=0 533issueLat=1 534opClass=SimdMisc 535opLat=1 536 537[system.cpu.fuPool.FUList5.opList06] 538type=OpDesc 539eventq_index=0 540issueLat=1 541opClass=SimdMult 542opLat=1 543 544[system.cpu.fuPool.FUList5.opList07] 545type=OpDesc 546eventq_index=0 547issueLat=1 548opClass=SimdMultAcc 549opLat=1 550 551[system.cpu.fuPool.FUList5.opList08] 552type=OpDesc 553eventq_index=0 554issueLat=1 555opClass=SimdShift 556opLat=1 557 558[system.cpu.fuPool.FUList5.opList09] 559type=OpDesc 560eventq_index=0 561issueLat=1 562opClass=SimdShiftAcc 563opLat=1 564 565[system.cpu.fuPool.FUList5.opList10] 566type=OpDesc 567eventq_index=0 568issueLat=1 569opClass=SimdSqrt 570opLat=1 571 572[system.cpu.fuPool.FUList5.opList11] 573type=OpDesc 574eventq_index=0 575issueLat=1 576opClass=SimdFloatAdd 577opLat=1 578 579[system.cpu.fuPool.FUList5.opList12] 580type=OpDesc 581eventq_index=0 582issueLat=1 583opClass=SimdFloatAlu 584opLat=1 585 586[system.cpu.fuPool.FUList5.opList13] 587type=OpDesc 588eventq_index=0 589issueLat=1 590opClass=SimdFloatCmp 591opLat=1 592 593[system.cpu.fuPool.FUList5.opList14] 594type=OpDesc 595eventq_index=0 596issueLat=1 597opClass=SimdFloatCvt 598opLat=1 599 600[system.cpu.fuPool.FUList5.opList15] 601type=OpDesc 602eventq_index=0 603issueLat=1 604opClass=SimdFloatDiv 605opLat=1 606 607[system.cpu.fuPool.FUList5.opList16] 608type=OpDesc 609eventq_index=0 610issueLat=1 611opClass=SimdFloatMisc 612opLat=1 613 614[system.cpu.fuPool.FUList5.opList17] 615type=OpDesc 616eventq_index=0 617issueLat=1 618opClass=SimdFloatMult 619opLat=1 620 621[system.cpu.fuPool.FUList5.opList18] 622type=OpDesc 623eventq_index=0 624issueLat=1 625opClass=SimdFloatMultAcc 626opLat=1 627 628[system.cpu.fuPool.FUList5.opList19] 629type=OpDesc 630eventq_index=0 631issueLat=1 632opClass=SimdFloatSqrt 633opLat=1 634 635[system.cpu.fuPool.FUList6] 636type=FUDesc 637children=opList 638count=0 639eventq_index=0 640opList=system.cpu.fuPool.FUList6.opList 641 642[system.cpu.fuPool.FUList6.opList] 643type=OpDesc 644eventq_index=0 645issueLat=1 646opClass=MemWrite 647opLat=1 648 649[system.cpu.fuPool.FUList7] 650type=FUDesc 651children=opList0 opList1 652count=4 653eventq_index=0 654opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 655 656[system.cpu.fuPool.FUList7.opList0] 657type=OpDesc 658eventq_index=0 659issueLat=1 660opClass=MemRead 661opLat=1 662 663[system.cpu.fuPool.FUList7.opList1] 664type=OpDesc 665eventq_index=0 666issueLat=1 667opClass=MemWrite 668opLat=1 669 670[system.cpu.fuPool.FUList8] 671type=FUDesc 672children=opList 673count=1 674eventq_index=0 675opList=system.cpu.fuPool.FUList8.opList 676 677[system.cpu.fuPool.FUList8.opList] 678type=OpDesc 679eventq_index=0 680issueLat=3 681opClass=IprAccess 682opLat=3 683 684[system.cpu.icache] 685type=BaseCache 686children=tags 687addr_ranges=0:18446744073709551615 688assoc=2 689clk_domain=system.cpu_clk_domain 690eventq_index=0 691forward_snoops=true 692hit_latency=2 693is_top_level=true 694max_miss_count=0 695mshrs=4 696prefetch_on_access=false 697prefetcher=Null 698response_latency=2 699sequential_access=false 700size=131072 701system=system 702tags=system.cpu.icache.tags 703tgts_per_mshr=20 704two_queue=false 705write_buffers=8 706cpu_side=system.cpu.icache_port 707mem_side=system.cpu.toL2Bus.slave[0] 708 709[system.cpu.icache.tags] 710type=LRU 711assoc=2 712block_size=64 713clk_domain=system.cpu_clk_domain 714eventq_index=0 715hit_latency=2 716sequential_access=false 717size=131072 718 719[system.cpu.interrupts] 720type=ArmInterrupts 721eventq_index=0 722 723[system.cpu.isa] 724type=ArmISA 725eventq_index=0 726fpsid=1090793632 727id_aa64afr0_el1=0 728id_aa64afr1_el1=0 729id_aa64dfr0_el1=1052678 730id_aa64dfr1_el1=0 731id_aa64isar0_el1=0 732id_aa64isar1_el1=0 733id_aa64mmfr0_el1=15728642 734id_aa64mmfr1_el1=0 735id_aa64pfr0_el1=17 736id_aa64pfr1_el1=0 737id_isar0=34607377 738id_isar1=34677009 739id_isar2=555950401 740id_isar3=17899825 741id_isar4=268501314 742id_isar5=0 743id_mmfr0=270536963 744id_mmfr1=0 745id_mmfr2=19070976 746id_mmfr3=34611729 747id_pfr0=49 748id_pfr1=4113 749midr=1091551472 750system=system 751 752[system.cpu.istage2_mmu] 753type=ArmStage2MMU 754children=stage2_tlb 755eventq_index=0 756stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 757tlb=system.cpu.itb 758 759[system.cpu.istage2_mmu.stage2_tlb] 760type=ArmTLB 761children=walker 762eventq_index=0 763is_stage2=true 764size=32 765walker=system.cpu.istage2_mmu.stage2_tlb.walker 766 767[system.cpu.istage2_mmu.stage2_tlb.walker] 768type=ArmTableWalker 769clk_domain=system.cpu_clk_domain 770eventq_index=0 771is_stage2=true 772num_squash_per_cycle=2 773sys=system 774port=system.cpu.toL2Bus.slave[4] 775 776[system.cpu.itb] 777type=ArmTLB 778children=walker 779eventq_index=0 780is_stage2=false 781size=64 782walker=system.cpu.itb.walker 783 784[system.cpu.itb.walker] 785type=ArmTableWalker 786clk_domain=system.cpu_clk_domain 787eventq_index=0 788is_stage2=false 789num_squash_per_cycle=2 790sys=system 791port=system.cpu.toL2Bus.slave[2] 792 793[system.cpu.l2cache] 794type=BaseCache 795children=tags 796addr_ranges=0:18446744073709551615 797assoc=8 798clk_domain=system.cpu_clk_domain 799eventq_index=0 800forward_snoops=true 801hit_latency=20 802is_top_level=false 803max_miss_count=0 804mshrs=20 805prefetch_on_access=false 806prefetcher=Null 807response_latency=20 808sequential_access=false 809size=2097152 810system=system 811tags=system.cpu.l2cache.tags 812tgts_per_mshr=12 813two_queue=false 814write_buffers=8 815cpu_side=system.cpu.toL2Bus.master[0] 816mem_side=system.membus.slave[1] 817 818[system.cpu.l2cache.tags] 819type=LRU 820assoc=8 821block_size=64 822clk_domain=system.cpu_clk_domain 823eventq_index=0 824hit_latency=20 825sequential_access=false 826size=2097152 827 828[system.cpu.toL2Bus] 829type=CoherentBus 830clk_domain=system.cpu_clk_domain 831eventq_index=0 832header_cycles=1 833system=system 834use_default_range=false 835width=32 836master=system.cpu.l2cache.cpu_side 837slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port 838 839[system.cpu.tracer] 840type=ExeTracer 841eventq_index=0 842 843[system.cpu.workload] 844type=LiveProcess 845cmd=hello 846cwd= 847egid=100 848env= 849errout=cerr 850euid=100 851eventq_index=0 852executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello 853gid=100 854input=cin 855max_stack_size=67108864 856output=cout 857pid=100 858ppid=99 859simpoint=0 860system=system 861uid=100 862 863[system.cpu_clk_domain] 864type=SrcClockDomain 865clock=500 866eventq_index=0 867voltage_domain=system.voltage_domain 868 869[system.membus] 870type=CoherentBus 871clk_domain=system.clk_domain 872eventq_index=0 873header_cycles=1 874system=system 875use_default_range=false 876width=8 877master=system.physmem.port 878slave=system.system_port system.cpu.l2cache.mem_side 879 880[system.physmem] 881type=DRAMCtrl 882activation_limit=4 883addr_mapping=RoRaBaChCo 884banks_per_rank=8 885burst_length=8 886channels=1 887clk_domain=system.clk_domain 888conf_table_reported=true 889device_bus_width=8 890device_rowbuffer_size=1024 891devices_per_rank=8 892eventq_index=0 893in_addr_map=true 894max_accesses_per_row=16 895mem_sched_policy=frfcfs 896min_writes_per_switch=16 897null=false 898page_policy=open_adaptive 899range=0:134217727 900ranks_per_channel=2 901read_buffer_size=32 902static_backend_latency=10000 903static_frontend_latency=10000 904tBURST=5000 905tCK=1250 906tCL=13750 907tRAS=35000 908tRCD=13750 909tREFI=7800000 910tRFC=260000 911tRP=13750 912tRRD=6000 913tRTP=7500 914tRTW=2500 915tWR=15000 916tWTR=7500 917tXAW=30000 918write_buffer_size=64 919write_high_thresh_perc=85 920write_low_thresh_perc=50 921port=system.membus.master[0] 922 923[system.voltage_domain] 924type=VoltageDomain 925eventq_index=0 926voltage=1.000000 927 928