config.ini revision 10038
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=DerivO3CPU 45children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52activity=0 53backComSize=5 54branchPred=system.cpu.branchPred 55cachePorts=200 56checker=system.cpu.checker 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dstage2_mmu=system.cpu.dstage2_mmu 72dtb=system.cpu.dtb 73eventq_index=0 74fetchBufferSize=64 75fetchToDecodeDelay=1 76fetchTrapLatency=1 77fetchWidth=8 78forwardComSize=5 79fuPool=system.cpu.fuPool 80function_trace=false 81function_trace_start=0 82iewToCommitDelay=1 83iewToDecodeDelay=1 84iewToFetchDelay=1 85iewToRenameDelay=1 86interrupts=system.cpu.interrupts 87isa=system.cpu.isa 88issueToExecuteDelay=1 89issueWidth=8 90istage2_mmu=system.cpu.istage2_mmu 91itb=system.cpu.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysCCRegs=0 99numPhysFloatRegs=256 100numPhysIntRegs=256 101numROBEntries=192 102numRobs=1 103numThreads=1 104profile=0 105progress_interval=0 106renameToDecodeDelay=1 107renameToFetchDelay=1 108renameToIEWDelay=2 109renameToROBDelay=1 110renameWidth=8 111simpoint_start_insts= 112smtCommitPolicy=RoundRobin 113smtFetchPolicy=SingleThread 114smtIQPolicy=Partitioned 115smtIQThreshold=100 116smtLSQPolicy=Partitioned 117smtLSQThreshold=100 118smtNumFetchingThreads=1 119smtROBPolicy=Partitioned 120smtROBThreshold=100 121squashWidth=8 122store_set_clear_period=250000 123switched_out=false 124system=system 125tracer=system.cpu.tracer 126trapLatency=13 127wbDepth=1 128wbWidth=8 129workload=system.cpu.workload 130dcache_port=system.cpu.dcache.cpu_side 131icache_port=system.cpu.icache.cpu_side 132 133[system.cpu.branchPred] 134type=BranchPredictor 135BTBEntries=4096 136BTBTagSize=16 137RASSize=16 138choiceCtrBits=2 139choicePredictorSize=8192 140eventq_index=0 141globalCtrBits=2 142globalPredictorSize=8192 143instShiftAmt=2 144localCtrBits=2 145localHistoryTableSize=2048 146localPredictorSize=2048 147numThreads=1 148predType=tournament 149 150[system.cpu.checker] 151type=O3Checker 152children=dstage2_mmu dtb isa istage2_mmu itb tracer 153checker=Null 154clk_domain=system.cpu_clk_domain 155cpu_id=0 156do_checkpoint_insts=true 157do_quiesce=true 158do_statistics_insts=true 159dstage2_mmu=system.cpu.checker.dstage2_mmu 160dtb=system.cpu.checker.dtb 161eventq_index=0 162exitOnError=false 163function_trace=false 164function_trace_start=0 165interrupts=Null 166isa=system.cpu.checker.isa 167istage2_mmu=system.cpu.checker.istage2_mmu 168itb=system.cpu.checker.itb 169max_insts_all_threads=0 170max_insts_any_thread=0 171max_loads_all_threads=0 172max_loads_any_thread=0 173numThreads=1 174profile=0 175progress_interval=0 176simpoint_start_insts= 177switched_out=false 178system=system 179tracer=system.cpu.checker.tracer 180updateOnError=true 181warnOnlyOnLoadError=true 182workload=system.cpu.workload 183 184[system.cpu.checker.dstage2_mmu] 185type=ArmStage2MMU 186children=stage2_tlb 187eventq_index=0 188stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 189tlb=system.cpu.checker.dtb 190 191[system.cpu.checker.dstage2_mmu.stage2_tlb] 192type=ArmTLB 193children=walker 194eventq_index=0 195is_stage2=true 196size=32 197walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 198 199[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 200type=ArmTableWalker 201clk_domain=system.cpu_clk_domain 202eventq_index=0 203is_stage2=true 204num_squash_per_cycle=2 205sys=system 206port=system.cpu.toL2Bus.slave[9] 207 208[system.cpu.checker.dtb] 209type=ArmTLB 210children=walker 211eventq_index=0 212is_stage2=false 213size=64 214walker=system.cpu.checker.dtb.walker 215 216[system.cpu.checker.dtb.walker] 217type=ArmTableWalker 218clk_domain=system.cpu_clk_domain 219eventq_index=0 220is_stage2=false 221num_squash_per_cycle=2 222sys=system 223port=system.cpu.toL2Bus.slave[7] 224 225[system.cpu.checker.isa] 226type=ArmISA 227eventq_index=0 228fpsid=1090793632 229id_aa64afr0_el1=0 230id_aa64afr1_el1=0 231id_aa64dfr0_el1=1052678 232id_aa64dfr1_el1=0 233id_aa64isar0_el1=0 234id_aa64isar1_el1=0 235id_aa64mmfr0_el1=15728642 236id_aa64mmfr1_el1=0 237id_aa64pfr0_el1=17 238id_aa64pfr1_el1=0 239id_isar0=34607377 240id_isar1=34677009 241id_isar2=555950401 242id_isar3=17899825 243id_isar4=268501314 244id_isar5=0 245id_mmfr0=270536963 246id_mmfr1=0 247id_mmfr2=19070976 248id_mmfr3=34611729 249id_pfr0=49 250id_pfr1=4113 251midr=1091551472 252system=system 253 254[system.cpu.checker.istage2_mmu] 255type=ArmStage2MMU 256children=stage2_tlb 257eventq_index=0 258stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 259tlb=system.cpu.checker.itb 260 261[system.cpu.checker.istage2_mmu.stage2_tlb] 262type=ArmTLB 263children=walker 264eventq_index=0 265is_stage2=true 266size=32 267walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 268 269[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 270type=ArmTableWalker 271clk_domain=system.cpu_clk_domain 272eventq_index=0 273is_stage2=true 274num_squash_per_cycle=2 275sys=system 276port=system.cpu.toL2Bus.slave[8] 277 278[system.cpu.checker.itb] 279type=ArmTLB 280children=walker 281eventq_index=0 282is_stage2=false 283size=64 284walker=system.cpu.checker.itb.walker 285 286[system.cpu.checker.itb.walker] 287type=ArmTableWalker 288clk_domain=system.cpu_clk_domain 289eventq_index=0 290is_stage2=false 291num_squash_per_cycle=2 292sys=system 293port=system.cpu.toL2Bus.slave[6] 294 295[system.cpu.checker.tracer] 296type=ExeTracer 297eventq_index=0 298 299[system.cpu.dcache] 300type=BaseCache 301children=tags 302addr_ranges=0:18446744073709551615 303assoc=2 304clk_domain=system.cpu_clk_domain 305eventq_index=0 306forward_snoops=true 307hit_latency=2 308is_top_level=true 309max_miss_count=0 310mshrs=4 311prefetch_on_access=false 312prefetcher=Null 313response_latency=2 314sequential_access=false 315size=262144 316system=system 317tags=system.cpu.dcache.tags 318tgts_per_mshr=20 319two_queue=false 320write_buffers=8 321cpu_side=system.cpu.dcache_port 322mem_side=system.cpu.toL2Bus.slave[1] 323 324[system.cpu.dcache.tags] 325type=LRU 326assoc=2 327block_size=64 328clk_domain=system.cpu_clk_domain 329eventq_index=0 330hit_latency=2 331sequential_access=false 332size=262144 333 334[system.cpu.dstage2_mmu] 335type=ArmStage2MMU 336children=stage2_tlb 337eventq_index=0 338stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 339tlb=system.cpu.dtb 340 341[system.cpu.dstage2_mmu.stage2_tlb] 342type=ArmTLB 343children=walker 344eventq_index=0 345is_stage2=true 346size=32 347walker=system.cpu.dstage2_mmu.stage2_tlb.walker 348 349[system.cpu.dstage2_mmu.stage2_tlb.walker] 350type=ArmTableWalker 351clk_domain=system.cpu_clk_domain 352eventq_index=0 353is_stage2=true 354num_squash_per_cycle=2 355sys=system 356port=system.cpu.toL2Bus.slave[5] 357 358[system.cpu.dtb] 359type=ArmTLB 360children=walker 361eventq_index=0 362is_stage2=false 363size=64 364walker=system.cpu.dtb.walker 365 366[system.cpu.dtb.walker] 367type=ArmTableWalker 368clk_domain=system.cpu_clk_domain 369eventq_index=0 370is_stage2=false 371num_squash_per_cycle=2 372sys=system 373port=system.cpu.toL2Bus.slave[3] 374 375[system.cpu.fuPool] 376type=FUPool 377children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 378FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 379eventq_index=0 380 381[system.cpu.fuPool.FUList0] 382type=FUDesc 383children=opList 384count=6 385eventq_index=0 386opList=system.cpu.fuPool.FUList0.opList 387 388[system.cpu.fuPool.FUList0.opList] 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=IntAlu 393opLat=1 394 395[system.cpu.fuPool.FUList1] 396type=FUDesc 397children=opList0 opList1 398count=2 399eventq_index=0 400opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 401 402[system.cpu.fuPool.FUList1.opList0] 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=IntMult 407opLat=3 408 409[system.cpu.fuPool.FUList1.opList1] 410type=OpDesc 411eventq_index=0 412issueLat=19 413opClass=IntDiv 414opLat=20 415 416[system.cpu.fuPool.FUList2] 417type=FUDesc 418children=opList0 opList1 opList2 419count=4 420eventq_index=0 421opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 422 423[system.cpu.fuPool.FUList2.opList0] 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=FloatAdd 428opLat=2 429 430[system.cpu.fuPool.FUList2.opList1] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=FloatCmp 435opLat=2 436 437[system.cpu.fuPool.FUList2.opList2] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=FloatCvt 442opLat=2 443 444[system.cpu.fuPool.FUList3] 445type=FUDesc 446children=opList0 opList1 opList2 447count=2 448eventq_index=0 449opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 450 451[system.cpu.fuPool.FUList3.opList0] 452type=OpDesc 453eventq_index=0 454issueLat=1 455opClass=FloatMult 456opLat=4 457 458[system.cpu.fuPool.FUList3.opList1] 459type=OpDesc 460eventq_index=0 461issueLat=12 462opClass=FloatDiv 463opLat=12 464 465[system.cpu.fuPool.FUList3.opList2] 466type=OpDesc 467eventq_index=0 468issueLat=24 469opClass=FloatSqrt 470opLat=24 471 472[system.cpu.fuPool.FUList4] 473type=FUDesc 474children=opList 475count=0 476eventq_index=0 477opList=system.cpu.fuPool.FUList4.opList 478 479[system.cpu.fuPool.FUList4.opList] 480type=OpDesc 481eventq_index=0 482issueLat=1 483opClass=MemRead 484opLat=1 485 486[system.cpu.fuPool.FUList5] 487type=FUDesc 488children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 489count=4 490eventq_index=0 491opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 492 493[system.cpu.fuPool.FUList5.opList00] 494type=OpDesc 495eventq_index=0 496issueLat=1 497opClass=SimdAdd 498opLat=1 499 500[system.cpu.fuPool.FUList5.opList01] 501type=OpDesc 502eventq_index=0 503issueLat=1 504opClass=SimdAddAcc 505opLat=1 506 507[system.cpu.fuPool.FUList5.opList02] 508type=OpDesc 509eventq_index=0 510issueLat=1 511opClass=SimdAlu 512opLat=1 513 514[system.cpu.fuPool.FUList5.opList03] 515type=OpDesc 516eventq_index=0 517issueLat=1 518opClass=SimdCmp 519opLat=1 520 521[system.cpu.fuPool.FUList5.opList04] 522type=OpDesc 523eventq_index=0 524issueLat=1 525opClass=SimdCvt 526opLat=1 527 528[system.cpu.fuPool.FUList5.opList05] 529type=OpDesc 530eventq_index=0 531issueLat=1 532opClass=SimdMisc 533opLat=1 534 535[system.cpu.fuPool.FUList5.opList06] 536type=OpDesc 537eventq_index=0 538issueLat=1 539opClass=SimdMult 540opLat=1 541 542[system.cpu.fuPool.FUList5.opList07] 543type=OpDesc 544eventq_index=0 545issueLat=1 546opClass=SimdMultAcc 547opLat=1 548 549[system.cpu.fuPool.FUList5.opList08] 550type=OpDesc 551eventq_index=0 552issueLat=1 553opClass=SimdShift 554opLat=1 555 556[system.cpu.fuPool.FUList5.opList09] 557type=OpDesc 558eventq_index=0 559issueLat=1 560opClass=SimdShiftAcc 561opLat=1 562 563[system.cpu.fuPool.FUList5.opList10] 564type=OpDesc 565eventq_index=0 566issueLat=1 567opClass=SimdSqrt 568opLat=1 569 570[system.cpu.fuPool.FUList5.opList11] 571type=OpDesc 572eventq_index=0 573issueLat=1 574opClass=SimdFloatAdd 575opLat=1 576 577[system.cpu.fuPool.FUList5.opList12] 578type=OpDesc 579eventq_index=0 580issueLat=1 581opClass=SimdFloatAlu 582opLat=1 583 584[system.cpu.fuPool.FUList5.opList13] 585type=OpDesc 586eventq_index=0 587issueLat=1 588opClass=SimdFloatCmp 589opLat=1 590 591[system.cpu.fuPool.FUList5.opList14] 592type=OpDesc 593eventq_index=0 594issueLat=1 595opClass=SimdFloatCvt 596opLat=1 597 598[system.cpu.fuPool.FUList5.opList15] 599type=OpDesc 600eventq_index=0 601issueLat=1 602opClass=SimdFloatDiv 603opLat=1 604 605[system.cpu.fuPool.FUList5.opList16] 606type=OpDesc 607eventq_index=0 608issueLat=1 609opClass=SimdFloatMisc 610opLat=1 611 612[system.cpu.fuPool.FUList5.opList17] 613type=OpDesc 614eventq_index=0 615issueLat=1 616opClass=SimdFloatMult 617opLat=1 618 619[system.cpu.fuPool.FUList5.opList18] 620type=OpDesc 621eventq_index=0 622issueLat=1 623opClass=SimdFloatMultAcc 624opLat=1 625 626[system.cpu.fuPool.FUList5.opList19] 627type=OpDesc 628eventq_index=0 629issueLat=1 630opClass=SimdFloatSqrt 631opLat=1 632 633[system.cpu.fuPool.FUList6] 634type=FUDesc 635children=opList 636count=0 637eventq_index=0 638opList=system.cpu.fuPool.FUList6.opList 639 640[system.cpu.fuPool.FUList6.opList] 641type=OpDesc 642eventq_index=0 643issueLat=1 644opClass=MemWrite 645opLat=1 646 647[system.cpu.fuPool.FUList7] 648type=FUDesc 649children=opList0 opList1 650count=4 651eventq_index=0 652opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 653 654[system.cpu.fuPool.FUList7.opList0] 655type=OpDesc 656eventq_index=0 657issueLat=1 658opClass=MemRead 659opLat=1 660 661[system.cpu.fuPool.FUList7.opList1] 662type=OpDesc 663eventq_index=0 664issueLat=1 665opClass=MemWrite 666opLat=1 667 668[system.cpu.fuPool.FUList8] 669type=FUDesc 670children=opList 671count=1 672eventq_index=0 673opList=system.cpu.fuPool.FUList8.opList 674 675[system.cpu.fuPool.FUList8.opList] 676type=OpDesc 677eventq_index=0 678issueLat=3 679opClass=IprAccess 680opLat=3 681 682[system.cpu.icache] 683type=BaseCache 684children=tags 685addr_ranges=0:18446744073709551615 686assoc=2 687clk_domain=system.cpu_clk_domain 688eventq_index=0 689forward_snoops=true 690hit_latency=2 691is_top_level=true 692max_miss_count=0 693mshrs=4 694prefetch_on_access=false 695prefetcher=Null 696response_latency=2 697sequential_access=false 698size=131072 699system=system 700tags=system.cpu.icache.tags 701tgts_per_mshr=20 702two_queue=false 703write_buffers=8 704cpu_side=system.cpu.icache_port 705mem_side=system.cpu.toL2Bus.slave[0] 706 707[system.cpu.icache.tags] 708type=LRU 709assoc=2 710block_size=64 711clk_domain=system.cpu_clk_domain 712eventq_index=0 713hit_latency=2 714sequential_access=false 715size=131072 716 717[system.cpu.interrupts] 718type=ArmInterrupts 719eventq_index=0 720 721[system.cpu.isa] 722type=ArmISA 723eventq_index=0 724fpsid=1090793632 725id_aa64afr0_el1=0 726id_aa64afr1_el1=0 727id_aa64dfr0_el1=1052678 728id_aa64dfr1_el1=0 729id_aa64isar0_el1=0 730id_aa64isar1_el1=0 731id_aa64mmfr0_el1=15728642 732id_aa64mmfr1_el1=0 733id_aa64pfr0_el1=17 734id_aa64pfr1_el1=0 735id_isar0=34607377 736id_isar1=34677009 737id_isar2=555950401 738id_isar3=17899825 739id_isar4=268501314 740id_isar5=0 741id_mmfr0=270536963 742id_mmfr1=0 743id_mmfr2=19070976 744id_mmfr3=34611729 745id_pfr0=49 746id_pfr1=4113 747midr=1091551472 748system=system 749 750[system.cpu.istage2_mmu] 751type=ArmStage2MMU 752children=stage2_tlb 753eventq_index=0 754stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 755tlb=system.cpu.itb 756 757[system.cpu.istage2_mmu.stage2_tlb] 758type=ArmTLB 759children=walker 760eventq_index=0 761is_stage2=true 762size=32 763walker=system.cpu.istage2_mmu.stage2_tlb.walker 764 765[system.cpu.istage2_mmu.stage2_tlb.walker] 766type=ArmTableWalker 767clk_domain=system.cpu_clk_domain 768eventq_index=0 769is_stage2=true 770num_squash_per_cycle=2 771sys=system 772port=system.cpu.toL2Bus.slave[4] 773 774[system.cpu.itb] 775type=ArmTLB 776children=walker 777eventq_index=0 778is_stage2=false 779size=64 780walker=system.cpu.itb.walker 781 782[system.cpu.itb.walker] 783type=ArmTableWalker 784clk_domain=system.cpu_clk_domain 785eventq_index=0 786is_stage2=false 787num_squash_per_cycle=2 788sys=system 789port=system.cpu.toL2Bus.slave[2] 790 791[system.cpu.l2cache] 792type=BaseCache 793children=tags 794addr_ranges=0:18446744073709551615 795assoc=8 796clk_domain=system.cpu_clk_domain 797eventq_index=0 798forward_snoops=true 799hit_latency=20 800is_top_level=false 801max_miss_count=0 802mshrs=20 803prefetch_on_access=false 804prefetcher=Null 805response_latency=20 806sequential_access=false 807size=2097152 808system=system 809tags=system.cpu.l2cache.tags 810tgts_per_mshr=12 811two_queue=false 812write_buffers=8 813cpu_side=system.cpu.toL2Bus.master[0] 814mem_side=system.membus.slave[1] 815 816[system.cpu.l2cache.tags] 817type=LRU 818assoc=8 819block_size=64 820clk_domain=system.cpu_clk_domain 821eventq_index=0 822hit_latency=20 823sequential_access=false 824size=2097152 825 826[system.cpu.toL2Bus] 827type=CoherentBus 828clk_domain=system.cpu_clk_domain 829eventq_index=0 830header_cycles=1 831system=system 832use_default_range=false 833width=32 834master=system.cpu.l2cache.cpu_side 835slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port 836 837[system.cpu.tracer] 838type=ExeTracer 839eventq_index=0 840 841[system.cpu.workload] 842type=LiveProcess 843cmd=hello 844cwd= 845egid=100 846env= 847errout=cerr 848euid=100 849eventq_index=0 850executable=/dist/test-progs/hello/bin/arm/linux/hello 851gid=100 852input=cin 853max_stack_size=67108864 854output=cout 855pid=100 856ppid=99 857simpoint=0 858system=system 859uid=100 860 861[system.cpu_clk_domain] 862type=SrcClockDomain 863clock=500 864eventq_index=0 865voltage_domain=system.voltage_domain 866 867[system.membus] 868type=CoherentBus 869clk_domain=system.clk_domain 870eventq_index=0 871header_cycles=1 872system=system 873use_default_range=false 874width=8 875master=system.physmem.port 876slave=system.system_port system.cpu.l2cache.mem_side 877 878[system.physmem] 879type=SimpleDRAM 880activation_limit=4 881addr_mapping=RaBaChCo 882banks_per_rank=8 883burst_length=8 884channels=1 885clk_domain=system.clk_domain 886conf_table_reported=true 887device_bus_width=8 888device_rowbuffer_size=1024 889devices_per_rank=8 890eventq_index=0 891in_addr_map=true 892mem_sched_policy=frfcfs 893null=false 894page_policy=open 895range=0:134217727 896ranks_per_channel=2 897read_buffer_size=32 898static_backend_latency=10000 899static_frontend_latency=10000 900tBURST=5000 901tCL=13750 902tRAS=35000 903tRCD=13750 904tREFI=7800000 905tRFC=300000 906tRP=13750 907tRRD=6250 908tWTR=7500 909tXAW=40000 910write_buffer_size=32 911write_high_thresh_perc=70 912write_low_thresh_perc=0 913port=system.membus.master[0] 914 915[system.voltage_domain] 916type=VoltageDomain 917eventq_index=0 918voltage=1.000000 919 920