config.ini revision 10036
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 39eventq_index=0 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true 48LSQDepCheckShift=4 49SQEntries=32 50SSITSize=1024 51activity=0 52backComSize=5 53branchPred=system.cpu.branchPred 54cachePorts=200 55checker=system.cpu.checker 56clk_domain=system.cpu_clk_domain 57commitToDecodeDelay=1 58commitToFetchDelay=1 59commitToIEWDelay=1 60commitToRenameDelay=1 61commitWidth=8 62cpu_id=0 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb 71eventq_index=0 72fetchBufferSize=64 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 81iewToDecodeDelay=1 82iewToFetchDelay=1 83iewToRenameDelay=1 84interrupts=system.cpu.interrupts 85isa=system.cpu.isa 86issueToExecuteDelay=1 87issueWidth=8 88itb=system.cpu.itb 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysCCRegs=0 96numPhysFloatRegs=256 97numPhysIntRegs=256 98numROBEntries=192 99numRobs=1 100numThreads=1 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108simpoint_start_insts= 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 118squashWidth=8 119store_set_clear_period=250000 120switched_out=false 121system=system 122tracer=system.cpu.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 126workload=system.cpu.workload 127dcache_port=system.cpu.dcache.cpu_side 128icache_port=system.cpu.icache.cpu_side 129 130[system.cpu.branchPred] 131type=BranchPredictor 132BTBEntries=4096 133BTBTagSize=16 134RASSize=16 135choiceCtrBits=2 136choicePredictorSize=8192 137eventq_index=0 138globalCtrBits=2 139globalPredictorSize=8192 140instShiftAmt=2 141localCtrBits=2 142localHistoryTableSize=2048 143localPredictorSize=2048 144numThreads=1 145predType=tournament 146 147[system.cpu.checker] 148type=O3Checker 149children=dtb isa itb tracer 150checker=Null 151clk_domain=system.cpu_clk_domain 152cpu_id=0 153do_checkpoint_insts=true 154do_quiesce=true 155do_statistics_insts=true 156dtb=system.cpu.checker.dtb 157eventq_index=0 158exitOnError=false 159function_trace=false 160function_trace_start=0 161interrupts=Null 162isa=system.cpu.checker.isa 163itb=system.cpu.checker.itb 164max_insts_all_threads=0 165max_insts_any_thread=0 166max_loads_all_threads=0 167max_loads_any_thread=0 168numThreads=1 169profile=0 170progress_interval=0 171simpoint_start_insts= 172switched_out=false 173system=system 174tracer=system.cpu.checker.tracer 175updateOnError=true 176warnOnlyOnLoadError=true 177workload=system.cpu.workload 178 179[system.cpu.checker.dtb] 180type=ArmTLB 181children=walker 182eventq_index=0 183size=64 184walker=system.cpu.checker.dtb.walker 185 186[system.cpu.checker.dtb.walker] 187type=ArmTableWalker 188clk_domain=system.cpu_clk_domain 189eventq_index=0 190num_squash_per_cycle=2 191sys=system 192port=system.cpu.toL2Bus.slave[5] 193 194[system.cpu.checker.isa] 195type=ArmISA 196eventq_index=0 197fpsid=1090793632 198id_isar0=34607377 199id_isar1=34677009 200id_isar2=555950401 201id_isar3=17899825 202id_isar4=268501314 203id_isar5=0 204id_mmfr0=3 205id_mmfr1=0 206id_mmfr2=19070976 207id_mmfr3=4027589137 208id_pfr0=49 209id_pfr1=1 210midr=890224640 211 212[system.cpu.checker.itb] 213type=ArmTLB 214children=walker 215eventq_index=0 216size=64 217walker=system.cpu.checker.itb.walker 218 219[system.cpu.checker.itb.walker] 220type=ArmTableWalker 221clk_domain=system.cpu_clk_domain 222eventq_index=0 223num_squash_per_cycle=2 224sys=system 225port=system.cpu.toL2Bus.slave[4] 226 227[system.cpu.checker.tracer] 228type=ExeTracer 229eventq_index=0 230 231[system.cpu.dcache] 232type=BaseCache 233children=tags 234addr_ranges=0:18446744073709551615 235assoc=2 236clk_domain=system.cpu_clk_domain 237eventq_index=0 238forward_snoops=true 239hit_latency=2 240is_top_level=true 241max_miss_count=0 242mshrs=4 243prefetch_on_access=false 244prefetcher=Null 245response_latency=2 246sequential_access=false 247size=262144 248system=system 249tags=system.cpu.dcache.tags 250tgts_per_mshr=20 251two_queue=false 252write_buffers=8 253cpu_side=system.cpu.dcache_port 254mem_side=system.cpu.toL2Bus.slave[1] 255 256[system.cpu.dcache.tags] 257type=LRU 258assoc=2 259block_size=64 260clk_domain=system.cpu_clk_domain 261eventq_index=0 262hit_latency=2 263sequential_access=false 264size=262144 265 266[system.cpu.dtb] 267type=ArmTLB 268children=walker 269eventq_index=0 270size=64 271walker=system.cpu.dtb.walker 272 273[system.cpu.dtb.walker] 274type=ArmTableWalker 275clk_domain=system.cpu_clk_domain 276eventq_index=0 277num_squash_per_cycle=2 278sys=system 279port=system.cpu.toL2Bus.slave[3] 280 281[system.cpu.fuPool] 282type=FUPool 283children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 284FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 285eventq_index=0 286 287[system.cpu.fuPool.FUList0] 288type=FUDesc 289children=opList 290count=6 291eventq_index=0 292opList=system.cpu.fuPool.FUList0.opList 293 294[system.cpu.fuPool.FUList0.opList] 295type=OpDesc 296eventq_index=0 297issueLat=1 298opClass=IntAlu 299opLat=1 300 301[system.cpu.fuPool.FUList1] 302type=FUDesc 303children=opList0 opList1 304count=2 305eventq_index=0 306opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 307 308[system.cpu.fuPool.FUList1.opList0] 309type=OpDesc 310eventq_index=0 311issueLat=1 312opClass=IntMult 313opLat=3 314 315[system.cpu.fuPool.FUList1.opList1] 316type=OpDesc 317eventq_index=0 318issueLat=19 319opClass=IntDiv 320opLat=20 321 322[system.cpu.fuPool.FUList2] 323type=FUDesc 324children=opList0 opList1 opList2 325count=4 326eventq_index=0 327opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 328 329[system.cpu.fuPool.FUList2.opList0] 330type=OpDesc 331eventq_index=0 332issueLat=1 333opClass=FloatAdd 334opLat=2 335 336[system.cpu.fuPool.FUList2.opList1] 337type=OpDesc 338eventq_index=0 339issueLat=1 340opClass=FloatCmp 341opLat=2 342 343[system.cpu.fuPool.FUList2.opList2] 344type=OpDesc 345eventq_index=0 346issueLat=1 347opClass=FloatCvt 348opLat=2 349 350[system.cpu.fuPool.FUList3] 351type=FUDesc 352children=opList0 opList1 opList2 353count=2 354eventq_index=0 355opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 356 357[system.cpu.fuPool.FUList3.opList0] 358type=OpDesc 359eventq_index=0 360issueLat=1 361opClass=FloatMult 362opLat=4 363 364[system.cpu.fuPool.FUList3.opList1] 365type=OpDesc 366eventq_index=0 367issueLat=12 368opClass=FloatDiv 369opLat=12 370 371[system.cpu.fuPool.FUList3.opList2] 372type=OpDesc 373eventq_index=0 374issueLat=24 375opClass=FloatSqrt 376opLat=24 377 378[system.cpu.fuPool.FUList4] 379type=FUDesc 380children=opList 381count=0 382eventq_index=0 383opList=system.cpu.fuPool.FUList4.opList 384 385[system.cpu.fuPool.FUList4.opList] 386type=OpDesc 387eventq_index=0 388issueLat=1 389opClass=MemRead 390opLat=1 391 392[system.cpu.fuPool.FUList5] 393type=FUDesc 394children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 395count=4 396eventq_index=0 397opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 398 399[system.cpu.fuPool.FUList5.opList00] 400type=OpDesc 401eventq_index=0 402issueLat=1 403opClass=SimdAdd 404opLat=1 405 406[system.cpu.fuPool.FUList5.opList01] 407type=OpDesc 408eventq_index=0 409issueLat=1 410opClass=SimdAddAcc 411opLat=1 412 413[system.cpu.fuPool.FUList5.opList02] 414type=OpDesc 415eventq_index=0 416issueLat=1 417opClass=SimdAlu 418opLat=1 419 420[system.cpu.fuPool.FUList5.opList03] 421type=OpDesc 422eventq_index=0 423issueLat=1 424opClass=SimdCmp 425opLat=1 426 427[system.cpu.fuPool.FUList5.opList04] 428type=OpDesc 429eventq_index=0 430issueLat=1 431opClass=SimdCvt 432opLat=1 433 434[system.cpu.fuPool.FUList5.opList05] 435type=OpDesc 436eventq_index=0 437issueLat=1 438opClass=SimdMisc 439opLat=1 440 441[system.cpu.fuPool.FUList5.opList06] 442type=OpDesc 443eventq_index=0 444issueLat=1 445opClass=SimdMult 446opLat=1 447 448[system.cpu.fuPool.FUList5.opList07] 449type=OpDesc 450eventq_index=0 451issueLat=1 452opClass=SimdMultAcc 453opLat=1 454 455[system.cpu.fuPool.FUList5.opList08] 456type=OpDesc 457eventq_index=0 458issueLat=1 459opClass=SimdShift 460opLat=1 461 462[system.cpu.fuPool.FUList5.opList09] 463type=OpDesc 464eventq_index=0 465issueLat=1 466opClass=SimdShiftAcc 467opLat=1 468 469[system.cpu.fuPool.FUList5.opList10] 470type=OpDesc 471eventq_index=0 472issueLat=1 473opClass=SimdSqrt 474opLat=1 475 476[system.cpu.fuPool.FUList5.opList11] 477type=OpDesc 478eventq_index=0 479issueLat=1 480opClass=SimdFloatAdd 481opLat=1 482 483[system.cpu.fuPool.FUList5.opList12] 484type=OpDesc 485eventq_index=0 486issueLat=1 487opClass=SimdFloatAlu 488opLat=1 489 490[system.cpu.fuPool.FUList5.opList13] 491type=OpDesc 492eventq_index=0 493issueLat=1 494opClass=SimdFloatCmp 495opLat=1 496 497[system.cpu.fuPool.FUList5.opList14] 498type=OpDesc 499eventq_index=0 500issueLat=1 501opClass=SimdFloatCvt 502opLat=1 503 504[system.cpu.fuPool.FUList5.opList15] 505type=OpDesc 506eventq_index=0 507issueLat=1 508opClass=SimdFloatDiv 509opLat=1 510 511[system.cpu.fuPool.FUList5.opList16] 512type=OpDesc 513eventq_index=0 514issueLat=1 515opClass=SimdFloatMisc 516opLat=1 517 518[system.cpu.fuPool.FUList5.opList17] 519type=OpDesc 520eventq_index=0 521issueLat=1 522opClass=SimdFloatMult 523opLat=1 524 525[system.cpu.fuPool.FUList5.opList18] 526type=OpDesc 527eventq_index=0 528issueLat=1 529opClass=SimdFloatMultAcc 530opLat=1 531 532[system.cpu.fuPool.FUList5.opList19] 533type=OpDesc 534eventq_index=0 535issueLat=1 536opClass=SimdFloatSqrt 537opLat=1 538 539[system.cpu.fuPool.FUList6] 540type=FUDesc 541children=opList 542count=0 543eventq_index=0 544opList=system.cpu.fuPool.FUList6.opList 545 546[system.cpu.fuPool.FUList6.opList] 547type=OpDesc 548eventq_index=0 549issueLat=1 550opClass=MemWrite 551opLat=1 552 553[system.cpu.fuPool.FUList7] 554type=FUDesc 555children=opList0 opList1 556count=4 557eventq_index=0 558opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 559 560[system.cpu.fuPool.FUList7.opList0] 561type=OpDesc 562eventq_index=0 563issueLat=1 564opClass=MemRead 565opLat=1 566 567[system.cpu.fuPool.FUList7.opList1] 568type=OpDesc 569eventq_index=0 570issueLat=1 571opClass=MemWrite 572opLat=1 573 574[system.cpu.fuPool.FUList8] 575type=FUDesc 576children=opList 577count=1 578eventq_index=0 579opList=system.cpu.fuPool.FUList8.opList 580 581[system.cpu.fuPool.FUList8.opList] 582type=OpDesc 583eventq_index=0 584issueLat=3 585opClass=IprAccess 586opLat=3 587 588[system.cpu.icache] 589type=BaseCache 590children=tags 591addr_ranges=0:18446744073709551615 592assoc=2 593clk_domain=system.cpu_clk_domain 594eventq_index=0 595forward_snoops=true 596hit_latency=2 597is_top_level=true 598max_miss_count=0 599mshrs=4 600prefetch_on_access=false 601prefetcher=Null 602response_latency=2 603sequential_access=false 604size=131072 605system=system 606tags=system.cpu.icache.tags 607tgts_per_mshr=20 608two_queue=false 609write_buffers=8 610cpu_side=system.cpu.icache_port 611mem_side=system.cpu.toL2Bus.slave[0] 612 613[system.cpu.icache.tags] 614type=LRU 615assoc=2 616block_size=64 617clk_domain=system.cpu_clk_domain 618eventq_index=0 619hit_latency=2 620sequential_access=false 621size=131072 622 623[system.cpu.interrupts] 624type=ArmInterrupts 625eventq_index=0 626 627[system.cpu.isa] 628type=ArmISA 629eventq_index=0 630fpsid=1090793632 631id_isar0=34607377 632id_isar1=34677009 633id_isar2=555950401 634id_isar3=17899825 635id_isar4=268501314 636id_isar5=0 637id_mmfr0=3 638id_mmfr1=0 639id_mmfr2=19070976 640id_mmfr3=4027589137 641id_pfr0=49 642id_pfr1=1 643midr=890224640 644 645[system.cpu.itb] 646type=ArmTLB 647children=walker 648eventq_index=0 649size=64 650walker=system.cpu.itb.walker 651 652[system.cpu.itb.walker] 653type=ArmTableWalker 654clk_domain=system.cpu_clk_domain 655eventq_index=0 656num_squash_per_cycle=2 657sys=system 658port=system.cpu.toL2Bus.slave[2] 659 660[system.cpu.l2cache] 661type=BaseCache 662children=tags 663addr_ranges=0:18446744073709551615 664assoc=8 665clk_domain=system.cpu_clk_domain 666eventq_index=0 667forward_snoops=true 668hit_latency=20 669is_top_level=false 670max_miss_count=0 671mshrs=20 672prefetch_on_access=false 673prefetcher=Null 674response_latency=20 675sequential_access=false 676size=2097152 677system=system 678tags=system.cpu.l2cache.tags 679tgts_per_mshr=12 680two_queue=false 681write_buffers=8 682cpu_side=system.cpu.toL2Bus.master[0] 683mem_side=system.membus.slave[1] 684 685[system.cpu.l2cache.tags] 686type=LRU 687assoc=8 688block_size=64 689clk_domain=system.cpu_clk_domain 690eventq_index=0 691hit_latency=20 692sequential_access=false 693size=2097152 694 695[system.cpu.toL2Bus] 696type=CoherentBus 697clk_domain=system.cpu_clk_domain 698eventq_index=0 699header_cycles=1 700system=system 701use_default_range=false 702width=32 703master=system.cpu.l2cache.cpu_side 704slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 705 706[system.cpu.tracer] 707type=ExeTracer 708eventq_index=0 709 710[system.cpu.workload] 711type=LiveProcess 712cmd=hello 713cwd= 714egid=100 715env= 716errout=cerr 717euid=100 718eventq_index=0 719executable=/dist/test-progs/hello/bin/arm/linux/hello 720gid=100 721input=cin 722max_stack_size=67108864 723output=cout 724pid=100 725ppid=99 726simpoint=0 727system=system 728uid=100 729 730[system.cpu_clk_domain] 731type=SrcClockDomain 732clock=500 733eventq_index=0 734voltage_domain=system.voltage_domain 735 736[system.membus] 737type=CoherentBus 738clk_domain=system.clk_domain 739eventq_index=0 740header_cycles=1 741system=system 742use_default_range=false 743width=8 744master=system.physmem.port 745slave=system.system_port system.cpu.l2cache.mem_side 746 747[system.physmem] 748type=SimpleDRAM 749activation_limit=4 750addr_mapping=RaBaChCo 751banks_per_rank=8 752burst_length=8 753channels=1 754clk_domain=system.clk_domain 755conf_table_reported=true 756device_bus_width=8 757device_rowbuffer_size=1024 758devices_per_rank=8 759eventq_index=0 760in_addr_map=true 761mem_sched_policy=frfcfs 762null=false 763page_policy=open 764range=0:134217727 765ranks_per_channel=2 766read_buffer_size=32 767static_backend_latency=10000 768static_frontend_latency=10000 769tBURST=5000 770tCL=13750 771tRAS=35000 772tRCD=13750 773tREFI=7800000 774tRFC=300000 775tRP=13750 776tRRD=6250 777tWTR=7500 778tXAW=40000 779write_buffer_size=32 780write_high_thresh_perc=70 781write_low_thresh_perc=0 782port=system.membus.master[0] 783 784[system.voltage_domain] 785type=VoltageDomain 786eventq_index=0 787voltage=1.000000 788 789