stats.txt revision 10260
110260SAndrew.Bardsley@arm.com 210260SAndrew.Bardsley@arm.com---------- Begin Simulation Statistics ---------- 310260SAndrew.Bardsley@arm.comfinal_tick 27963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 410260SAndrew.Bardsley@arm.comhost_inst_rate 75358 # Simulator instruction rate (inst/s) 510260SAndrew.Bardsley@arm.comhost_mem_usage 292860 # Number of bytes of host memory used 610260SAndrew.Bardsley@arm.comhost_op_rate 93985 # Simulator op (including micro ops) rate (op/s) 710260SAndrew.Bardsley@arm.comhost_seconds 0.06 # Real time elapsed on the host 810260SAndrew.Bardsley@arm.comhost_tick_rate 457698243 # Simulator tick rate (ticks/s) 910260SAndrew.Bardsley@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 1010260SAndrew.Bardsley@arm.comsim_insts 4604 # Number of instructions simulated 1110260SAndrew.Bardsley@arm.comsim_ops 5742 # Number of ops (including micro ops) simulated 1210260SAndrew.Bardsley@arm.comsim_seconds 0.000028 # Number of seconds simulated 1310260SAndrew.Bardsley@arm.comsim_ticks 27963000 # Number of ticks simulated 1410260SAndrew.Bardsley@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1510260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1610260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.BTBHitPct 21.219512 # BTB Hit Percentage 1710260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.BTBHits 348 # Number of BTB hits 1810260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.BTBLookups 1640 # Number of BTB lookups 1910260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 2010260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect 2110260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.condPredicted 1370 # Number of conditional branches predicted 2210260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.lookups 2005 # Number of BP lookups 2310260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.usedRAS 202 # Number of times the RAS was used to get a target. 2410260SAndrew.Bardsley@arm.comsystem.cpu.committedInsts 4604 # Number of instructions committed 2510260SAndrew.Bardsley@arm.comsystem.cpu.committedOps 5742 # Number of ops (including micro ops) committed 2610260SAndrew.Bardsley@arm.comsystem.cpu.cpi 12.147263 # CPI: cycles per instruction 2710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses) 2810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 2910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits 3010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 3110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.inst 1318 # number of ReadReq accesses(hits+misses) 3210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1318 # number of ReadReq accesses(hits+misses) 3310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60367.304348 # average ReadReq miss latency 3410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 60367.304348 # average ReadReq miss latency 3510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60667.563107 # average ReadReq mshr miss latency 3610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60667.563107 # average ReadReq mshr miss latency 3710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.inst 1203 # number of ReadReq hits 3810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_hits::total 1203 # number of ReadReq hits 3910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.inst 6942240 # number of ReadReq miss cycles 4010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 6942240 # number of ReadReq miss cycles 4110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.087253 # miss rate for ReadReq accesses 4210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.087253 # miss rate for ReadReq accesses 4310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses 4410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 4510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits 4610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 4710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6248759 # number of ReadReq MSHR miss cycles 4810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6248759 # number of ReadReq MSHR miss cycles 4910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.078149 # mshr miss rate for ReadReq accesses 5010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.078149 # mshr miss rate for ReadReq accesses 5110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses 5210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 5310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses) 5410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 5510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits 5610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 5710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) 5810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 5910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.179104 # average WriteReq miss latency 6010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 68664.179104 # average WriteReq miss latency 6110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66843.023256 # average WriteReq mshr miss latency 6210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66843.023256 # average WriteReq mshr miss latency 6310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits 6410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 6510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.inst 4600500 # number of WriteReq miss cycles 6610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 4600500 # number of WriteReq miss cycles 6710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses 6810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses 6910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses 7010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 7110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.inst 24 # number of WriteReq MSHR hits 7210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits 7310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2874250 # number of WriteReq MSHR miss cycles 7410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2874250 # number of WriteReq MSHR miss cycles 7510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses 7610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 7710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses 7810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 7910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 8210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 8310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses 8710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_accesses::total 2231 # number of demand (read+write) accesses 8810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.inst 63421.648352 # average overall miss latency 8910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 63421.648352 # average overall miss latency 9010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62486.363014 # average overall mshr miss latency 9110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 62486.363014 # average overall mshr miss latency 9210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_hits::cpu.inst 2049 # number of demand (read+write) hits 9310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_hits::total 2049 # number of demand (read+write) hits 9410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.inst 11542740 # number of demand (read+write) miss cycles 9510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_latency::total 11542740 # number of demand (read+write) miss cycles 9610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.inst 0.081578 # miss rate for demand accesses 9710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.081578 # miss rate for demand accesses 9810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses 9910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 10010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits 10110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits 10210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9123009 # number of demand (read+write) MSHR miss cycles 10310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 9123009 # number of demand (read+write) MSHR miss cycles 10410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.065442 # mshr miss rate for demand accesses 10510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.065442 # mshr miss rate for demand accesses 10610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses 10710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 10810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 10910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 11010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_accesses::cpu.inst 2231 # number of overall (read+write) accesses 11110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_accesses::total 2231 # number of overall (read+write) accesses 11210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.inst 63421.648352 # average overall miss latency 11310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 63421.648352 # average overall miss latency 11410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62486.363014 # average overall mshr miss latency 11510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 62486.363014 # average overall mshr miss latency 11610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_hits::cpu.inst 2049 # number of overall hits 11710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_hits::total 2049 # number of overall hits 11810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.inst 11542740 # number of overall miss cycles 11910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_latency::total 11542740 # number of overall miss cycles 12010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.inst 0.081578 # miss rate for overall accesses 12110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.081578 # miss rate for overall accesses 12210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses 12310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_misses::total 182 # number of overall misses 12410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits 12510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits 12610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9123009 # number of overall MSHR miss cycles 12710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 9123009 # number of overall MSHR miss cycles 12810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.065442 # mshr miss rate for overall accesses 12910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.065442 # mshr miss rate for overall accesses 13010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses 13110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses 13210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 13310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 13410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.avg_refs 14.184932 # Average number of references to valid blocks. 13510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.data_accesses 4652 # Number of data accesses 13610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.inst 86.831207 # Average occupied blocks per requestor 13710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.inst 0.021199 # Average percentage of cache occupancy 13810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021199 # Average percentage of cache occupancy 13910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 14010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 14110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 14210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 14310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.tag_accesses 4652 # Number of tag accesses 14410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.tagsinuse 86.831207 # Cycle average of tags in use 14510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.total_refs 2071 # Total number of references to valid blocks. 14610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 14710260SAndrew.Bardsley@arm.comsystem.cpu.discardedOps 1297 # Number of ops (including micro ops) which were discarded before commit 14810260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 14910260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 15010260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 15110260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 15210260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 15310260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 15410260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 15510260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 15610260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 15710260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 15810260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 15910260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 16010260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 16110260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 16210260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 16310260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 16410260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 16510260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 16610260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 16710260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 16810260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 16910260SAndrew.Bardsley@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 17010260SAndrew.Bardsley@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 17110260SAndrew.Bardsley@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 17210260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 17310260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 17410260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 17510260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 17610260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 17710260SAndrew.Bardsley@arm.comsystem.cpu.dtb.hits 0 # DTB hits 17810260SAndrew.Bardsley@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 17910260SAndrew.Bardsley@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 18010260SAndrew.Bardsley@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 18110260SAndrew.Bardsley@arm.comsystem.cpu.dtb.misses 0 # DTB misses 18210260SAndrew.Bardsley@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 18310260SAndrew.Bardsley@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 18410260SAndrew.Bardsley@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 18510260SAndrew.Bardsley@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 18610260SAndrew.Bardsley@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 18710260SAndrew.Bardsley@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 18810260SAndrew.Bardsley@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 18910260SAndrew.Bardsley@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 19010260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2307 # number of ReadReq accesses(hits+misses) 19110260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_accesses::total 2307 # number of ReadReq accesses(hits+misses) 19210260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66806.250000 # average ReadReq miss latency 19310260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 66806.250000 # average ReadReq miss latency 19410260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64396.875000 # average ReadReq mshr miss latency 19510260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64396.875000 # average ReadReq mshr miss latency 19610260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1987 # number of ReadReq hits 19710260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_hits::total 1987 # number of ReadReq hits 19810260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 21378000 # number of ReadReq miss cycles 19910260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 21378000 # number of ReadReq miss cycles 20010260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138708 # miss rate for ReadReq accesses 20110260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.138708 # miss rate for ReadReq accesses 20210260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 320 # number of ReadReq misses 20310260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_misses::total 320 # number of ReadReq misses 20410260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20607000 # number of ReadReq MSHR miss cycles 20510260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 20607000 # number of ReadReq MSHR miss cycles 20610260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138708 # mshr miss rate for ReadReq accesses 20710260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.138708 # mshr miss rate for ReadReq accesses 20810260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 320 # number of ReadReq MSHR misses 20910260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 320 # number of ReadReq MSHR misses 21010260SAndrew.Bardsley@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 21110260SAndrew.Bardsley@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 21210260SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 21310260SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 21410260SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 21510260SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 21610260SAndrew.Bardsley@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 21710260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2307 # number of demand (read+write) accesses 21810260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_accesses::total 2307 # number of demand (read+write) accesses 21910260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 66806.250000 # average overall miss latency 22010260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 66806.250000 # average overall miss latency 22110260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64396.875000 # average overall mshr miss latency 22210260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 64396.875000 # average overall mshr miss latency 22310260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1987 # number of demand (read+write) hits 22410260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_hits::total 1987 # number of demand (read+write) hits 22510260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 21378000 # number of demand (read+write) miss cycles 22610260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_latency::total 21378000 # number of demand (read+write) miss cycles 22710260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.138708 # miss rate for demand accesses 22810260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_rate::total 0.138708 # miss rate for demand accesses 22910260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_misses::cpu.inst 320 # number of demand (read+write) misses 23010260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_misses::total 320 # number of demand (read+write) misses 23110260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 20607000 # number of demand (read+write) MSHR miss cycles 23210260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 20607000 # number of demand (read+write) MSHR miss cycles 23310260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138708 # mshr miss rate for demand accesses 23410260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.138708 # mshr miss rate for demand accesses 23510260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 320 # number of demand (read+write) MSHR misses 23610260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses 23710260SAndrew.Bardsley@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 23810260SAndrew.Bardsley@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 23910260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2307 # number of overall (read+write) accesses 24010260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_accesses::total 2307 # number of overall (read+write) accesses 24110260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 66806.250000 # average overall miss latency 24210260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 66806.250000 # average overall miss latency 24310260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64396.875000 # average overall mshr miss latency 24410260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 64396.875000 # average overall mshr miss latency 24510260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1987 # number of overall hits 24610260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_hits::total 1987 # number of overall hits 24710260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 21378000 # number of overall miss cycles 24810260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_latency::total 21378000 # number of overall miss cycles 24910260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.138708 # miss rate for overall accesses 25010260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_rate::total 0.138708 # miss rate for overall accesses 25110260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_misses::cpu.inst 320 # number of overall misses 25210260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_misses::total 320 # number of overall misses 25310260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 20607000 # number of overall MSHR miss cycles 25410260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 20607000 # number of overall MSHR miss cycles 25510260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138708 # mshr miss rate for overall accesses 25610260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.138708 # mshr miss rate for overall accesses 25710260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 320 # number of overall MSHR misses 25810260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_misses::total 320 # number of overall MSHR misses 25910260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 26010260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id 26110260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.avg_refs 6.209375 # Average number of references to valid blocks. 26210260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.data_accesses 4934 # Number of data accesses 26310260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 161.718196 # Average occupied blocks per requestor 26410260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.078964 # Average percentage of cache occupancy 26510260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_percent::total 0.078964 # Average percentage of cache occupancy 26610260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id 26710260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id 26810260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.replacements 3 # number of replacements 26910260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.sampled_refs 320 # Sample count of references to valid blocks. 27010260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.tag_accesses 4934 # Number of tag accesses 27110260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.tagsinuse 161.718196 # Cycle average of tags in use 27210260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.total_refs 1987 # Total number of references to valid blocks. 27310260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 27410260SAndrew.Bardsley@arm.comsystem.cpu.idleCycles 44980 # Total number of cycles that the CPU has spent unscheduled due to idling 27510260SAndrew.Bardsley@arm.comsystem.cpu.ipc 0.082323 # IPC: instructions per cycle 27610260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 27710260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 27810260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 27910260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28010260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28110260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28210260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28310260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28410260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 28510260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 28610260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 28710260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 28810260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 28910260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29010260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 29110260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29210260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 29310260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 29410260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29510260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 29610260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 29710260SAndrew.Bardsley@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 29810260SAndrew.Bardsley@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 29910260SAndrew.Bardsley@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 30010260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 30110260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 30210260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 30310260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30410260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30510260SAndrew.Bardsley@arm.comsystem.cpu.itb.hits 0 # DTB hits 30610260SAndrew.Bardsley@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 30710260SAndrew.Bardsley@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 30810260SAndrew.Bardsley@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 30910260SAndrew.Bardsley@arm.comsystem.cpu.itb.misses 0 # DTB misses 31010260SAndrew.Bardsley@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 31110260SAndrew.Bardsley@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 31210260SAndrew.Bardsley@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 31310260SAndrew.Bardsley@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 31410260SAndrew.Bardsley@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 31510260SAndrew.Bardsley@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 31610260SAndrew.Bardsley@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 31710260SAndrew.Bardsley@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 31810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) 31910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 32010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65831.395349 # average ReadExReq miss latency 32110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 65831.395349 # average ReadExReq miss latency 32210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53308.139535 # average ReadExReq mshr miss latency 32310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53308.139535 # average ReadExReq mshr miss latency 32410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2830750 # number of ReadExReq miss cycles 32510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2830750 # number of ReadExReq miss cycles 32610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 32710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 32810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses 32910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 33010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2292250 # number of ReadExReq MSHR miss cycles 33110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2292250 # number of ReadExReq MSHR miss cycles 33210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 33310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 33410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses 33510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 33610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 423 # number of ReadReq accesses(hits+misses) 33710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 423 # number of ReadReq accesses(hits+misses) 33810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67507.124352 # average ReadReq miss latency 33910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 67507.124352 # average ReadReq miss latency 34010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55150.530504 # average ReadReq mshr miss latency 34110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55150.530504 # average ReadReq mshr miss latency 34210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 37 # number of ReadReq hits 34310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits 34410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26057750 # number of ReadReq miss cycles 34510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 26057750 # number of ReadReq miss cycles 34610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.912530 # miss rate for ReadReq accesses 34710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.912530 # miss rate for ReadReq accesses 34810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses 34910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses 35010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits 35110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 35210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20791750 # number of ReadReq MSHR miss cycles 35310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791750 # number of ReadReq MSHR miss cycles 35410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891253 # mshr miss rate for ReadReq accesses 35510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.891253 # mshr miss rate for ReadReq accesses 35610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses 35710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses 35810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 35910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 36010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 36110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 36210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 36310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 36410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 36510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 466 # number of demand (read+write) accesses 36610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_accesses::total 466 # number of demand (read+write) accesses 36710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67339.160839 # average overall miss latency 36810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 67339.160839 # average overall miss latency 36910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54961.904762 # average overall mshr miss latency 37010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 54961.904762 # average overall mshr miss latency 37110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits 37210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits 37310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 28888500 # number of demand (read+write) miss cycles 37410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_latency::total 28888500 # number of demand (read+write) miss cycles 37510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.920601 # miss rate for demand accesses 37610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.920601 # miss rate for demand accesses 37710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses 37810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses 37910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits 38010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 38110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23084000 # number of demand (read+write) MSHR miss cycles 38210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 23084000 # number of demand (read+write) MSHR miss cycles 38310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.901288 # mshr miss rate for demand accesses 38410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.901288 # mshr miss rate for demand accesses 38510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses 38610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses 38710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 38810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 38910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 466 # number of overall (read+write) accesses 39010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_accesses::total 466 # number of overall (read+write) accesses 39110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67339.160839 # average overall miss latency 39210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 67339.160839 # average overall miss latency 39310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54961.904762 # average overall mshr miss latency 39410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 54961.904762 # average overall mshr miss latency 39510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits 39610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_hits::total 37 # number of overall hits 39710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 28888500 # number of overall miss cycles 39810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_latency::total 28888500 # number of overall miss cycles 39910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.920601 # miss rate for overall accesses 40010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.920601 # miss rate for overall accesses 40110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses 40210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_misses::total 429 # number of overall misses 40310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits 40410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits 40510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23084000 # number of overall MSHR miss cycles 40610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 23084000 # number of overall MSHR miss cycles 40710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.901288 # mshr miss rate for overall accesses 40810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.901288 # mshr miss rate for overall accesses 40910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses 41010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses 41110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 41210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 41310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.avg_refs 0.098143 # Average number of references to valid blocks. 41410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.data_accesses 4148 # Number of data accesses 41510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 195.926239 # Average occupied blocks per requestor 41610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.005979 # Average percentage of cache occupancy 41710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005979 # Average percentage of cache occupancy 41810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id 41910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id 42010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 42110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks. 42210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.tag_accesses 4148 # Number of tag accesses 42310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.tagsinuse 195.926239 # Cycle average of tags in use 42410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.total_refs 37 # Total number of references to valid blocks. 42510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 42610260SAndrew.Bardsley@arm.comsystem.cpu.numCycles 55926 # number of cpu cycles simulated 42710260SAndrew.Bardsley@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 42810260SAndrew.Bardsley@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 42910260SAndrew.Bardsley@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43010260SAndrew.Bardsley@arm.comsystem.cpu.tickCycles 10946 # Number of cycles that the CPU actually ticked 43110260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.data_through_bus 29824 # Total data (bytes) 43210260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) 43310260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 43410260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.pkt_count::total 932 # Packet count per connected master and slave (bytes) 43510260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 233000 # Layer occupancy (ticks) 43610260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 43710260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 545500 # Layer occupancy (ticks) 43810260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 43910260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 234491 # Layer occupancy (ticks) 44010260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 44110260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 44210260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.throughput 1066552230 # Throughput (bytes/s) 44310260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes) 44410260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 44510260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 29824 # Cumulative packet size per connected master and slave (bytes) 44610260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 423 # Transaction distribution 44710260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 423 # Transaction distribution 44810260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 44910260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 45010260SAndrew.Bardsley@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 45110260SAndrew.Bardsley@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 45210260SAndrew.Bardsley@arm.comsystem.membus.data_through_bus 26880 # Total data (bytes) 45310260SAndrew.Bardsley@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) 45410260SAndrew.Bardsley@arm.comsystem.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) 45510260SAndrew.Bardsley@arm.comsystem.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) 45610260SAndrew.Bardsley@arm.comsystem.membus.reqLayer0.utilization 1.7 # Layer utilization (%) 45710260SAndrew.Bardsley@arm.comsystem.membus.respLayer1.occupancy 3923500 # Layer occupancy (ticks) 45810260SAndrew.Bardsley@arm.comsystem.membus.respLayer1.utilization 14.0 # Layer utilization (%) 45910260SAndrew.Bardsley@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 46010260SAndrew.Bardsley@arm.comsystem.membus.throughput 961270250 # Throughput (bytes/s) 46110260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) 46210260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) 46310260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::ReadReq 377 # Transaction distribution 46410260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::ReadResp 377 # Transaction distribution 46510260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::ReadExReq 43 # Transaction distribution 46610260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::ReadExResp 43 # Transaction distribution 46710260SAndrew.Bardsley@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 46810260SAndrew.Bardsley@arm.comsystem.physmem.avgGap 66375.00 # Average gap between requests 46910260SAndrew.Bardsley@arm.comsystem.physmem.avgMemAccLat 24369.64 # Average memory access latency per DRAM burst 47010260SAndrew.Bardsley@arm.comsystem.physmem.avgQLat 5619.64 # Average queueing delay per DRAM burst 47110260SAndrew.Bardsley@arm.comsystem.physmem.avgRdBW 961.27 # Average DRAM read bandwidth in MiByte/s 47210260SAndrew.Bardsley@arm.comsystem.physmem.avgRdBWSys 961.27 # Average system read bandwidth in MiByte/s 47310260SAndrew.Bardsley@arm.comsystem.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 47410260SAndrew.Bardsley@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 47510260SAndrew.Bardsley@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 47610260SAndrew.Bardsley@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 47710260SAndrew.Bardsley@arm.comsystem.physmem.busUtil 7.51 # Data bus utilization in percentage 47810260SAndrew.Bardsley@arm.comsystem.physmem.busUtilRead 7.51 # Data bus utilization in percentage for reads 47910260SAndrew.Bardsley@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 48010260SAndrew.Bardsley@arm.comsystem.physmem.bw_inst_read::cpu.inst 695776562 # Instruction read bandwidth from this memory (bytes/s) 48110260SAndrew.Bardsley@arm.comsystem.physmem.bw_inst_read::total 695776562 # Instruction read bandwidth from this memory (bytes/s) 48210260SAndrew.Bardsley@arm.comsystem.physmem.bw_read::cpu.inst 961270250 # Total read bandwidth from this memory (bytes/s) 48310260SAndrew.Bardsley@arm.comsystem.physmem.bw_read::total 961270250 # Total read bandwidth from this memory (bytes/s) 48410260SAndrew.Bardsley@arm.comsystem.physmem.bw_total::cpu.inst 961270250 # Total bandwidth to/from this memory (bytes/s) 48510260SAndrew.Bardsley@arm.comsystem.physmem.bw_total::total 961270250 # Total bandwidth to/from this memory (bytes/s) 48610260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation 48710260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::mean 389.907692 # Bytes accessed per row activation 48810260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::gmean 267.054058 # Bytes accessed per row activation 48910260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::stdev 328.238562 # Bytes accessed per row activation 49010260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::0-127 11 16.92% 16.92% # Bytes accessed per row activation 49110260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::128-255 17 26.15% 43.08% # Bytes accessed per row activation 49210260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::256-383 12 18.46% 61.54% # Bytes accessed per row activation 49310260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::384-511 7 10.77% 72.31% # Bytes accessed per row activation 49410260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::512-639 3 4.62% 76.92% # Bytes accessed per row activation 49510260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::640-767 2 3.08% 80.00% # Bytes accessed per row activation 49610260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::768-895 3 4.62% 84.62% # Bytes accessed per row activation 49710260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::1024-1151 10 15.38% 100.00% # Bytes accessed per row activation 49810260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation 49910260SAndrew.Bardsley@arm.comsystem.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM 50010260SAndrew.Bardsley@arm.comsystem.physmem.bytesReadSys 26880 # Total read bytes from the system interface side 50110260SAndrew.Bardsley@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 50210260SAndrew.Bardsley@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 50310260SAndrew.Bardsley@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 50410260SAndrew.Bardsley@arm.comsystem.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory 50510260SAndrew.Bardsley@arm.comsystem.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory 50610260SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory 50710260SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::total 26880 # Number of bytes read from this memory 50810260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::IDLE 12000 # Time in different power states 50910260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::REF 780000 # Time in different power states 51010260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 51110260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::ACT 22869500 # Time in different power states 51210260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 51310260SAndrew.Bardsley@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51410260SAndrew.Bardsley@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51510260SAndrew.Bardsley@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 51610260SAndrew.Bardsley@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 51710260SAndrew.Bardsley@arm.comsystem.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory 51810260SAndrew.Bardsley@arm.comsystem.physmem.num_reads::total 420 # Number of read requests responded to by this memory 51910260SAndrew.Bardsley@arm.comsystem.physmem.pageHitRate 82.62 # Row buffer hit rate, read and write combined 52010260SAndrew.Bardsley@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 52110260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::0 91 # Per bank write bursts 52210260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::1 51 # Per bank write bursts 52310260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 52410260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::3 42 # Per bank write bursts 52510260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::4 22 # Per bank write bursts 52610260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::5 41 # Per bank write bursts 52710260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::6 36 # Per bank write bursts 52810260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::7 12 # Per bank write bursts 52910260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::8 6 # Per bank write bursts 53010260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::9 6 # Per bank write bursts 53110260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::10 27 # Per bank write bursts 53210260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 53310260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::12 9 # Per bank write bursts 53410260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::13 8 # Per bank write bursts 53510260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 53610260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::15 7 # Per bank write bursts 53710260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 53810260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 53910260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 54010260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 54110260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 54210260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 54310260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 54410260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 54510260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 54610260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 54710260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 54810260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 54910260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 55010260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 55110260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 55210260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 55310260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see 55410260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::1 65 # What read queue length does an incoming req see 55510260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see 55610260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 55710260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 55810260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 55910260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 56010260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 56110260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 56210260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 56310260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 56410260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 56510260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 56610260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 56710260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 56810260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 56910260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 57010260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 57110260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 57210260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 57310260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 57410260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 57510260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 57610260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 57710260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 57810260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 57910260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 58010260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 58110260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 58210260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 58310260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 58410260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 58510260SAndrew.Bardsley@arm.comsystem.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue 58610260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 58710260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 58810260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 58910260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 59010260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 59110260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 59210260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::6 420 # Read request sizes (log2) 59310260SAndrew.Bardsley@arm.comsystem.physmem.readReqs 420 # Number of read requests accepted 59410260SAndrew.Bardsley@arm.comsystem.physmem.readRowHitRate 82.62 # Row buffer hit rate for reads 59510260SAndrew.Bardsley@arm.comsystem.physmem.readRowHits 347 # Number of row buffer hits during reads 59610260SAndrew.Bardsley@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 59710260SAndrew.Bardsley@arm.comsystem.physmem.totBusLat 2100000 # Total ticks spent in databus transfers 59810260SAndrew.Bardsley@arm.comsystem.physmem.totGap 27877500 # Total gap between requests 59910260SAndrew.Bardsley@arm.comsystem.physmem.totMemAccLat 10235250 # Total ticks spent from burst creation until serviced by the DRAM 60010260SAndrew.Bardsley@arm.comsystem.physmem.totQLat 2360250 # Total ticks spent queuing 60110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 60210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 60310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 60410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 60510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 60610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 60710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 60810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 60910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 61010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 61110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 61210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 61310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 61410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 61510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 61610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 61710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 61810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 61910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 62010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 62110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 62210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 62310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 62410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 62510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 62610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 62710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 62810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 62910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 63010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 63110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 63210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 63310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 63410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 63510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 63610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 63710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 63810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 63910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 64010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 64110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 64210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 64310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 64410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 64510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 64610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 64710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 64810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 64910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 65010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 65110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 65210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 65310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 65410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 65510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 65610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 65710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 65810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 65910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 66010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 66110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 66210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 66310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 66410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 66510260SAndrew.Bardsley@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 66610260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 66710260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 66810260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 66910260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 67010260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 67110260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 67210260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 67310260SAndrew.Bardsley@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 67410260SAndrew.Bardsley@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 67510260SAndrew.Bardsley@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 67610260SAndrew.Bardsley@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 67710260SAndrew.Bardsley@arm.com 67810260SAndrew.Bardsley@arm.com---------- End Simulation Statistics ---------- 679