stats.txt revision 9481:b0fa6b872f40
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 32544000 # Number of ticks simulated 5final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 97330 # Simulator instruction rate (inst/s) 8host_op_rate 97300 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 495402774 # Simulator tick rate (ticks/s) 10host_mem_usage 269640 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 446 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.fetch_hits 0 # ITB hits 31system.cpu.dtb.fetch_misses 0 # ITB misses 32system.cpu.dtb.fetch_acv 0 # ITB acv 33system.cpu.dtb.fetch_accesses 0 # ITB accesses 34system.cpu.dtb.read_hits 1183 # DTB read hits 35system.cpu.dtb.read_misses 7 # DTB read misses 36system.cpu.dtb.read_acv 0 # DTB read access violations 37system.cpu.dtb.read_accesses 1190 # DTB read accesses 38system.cpu.dtb.write_hits 865 # DTB write hits 39system.cpu.dtb.write_misses 3 # DTB write misses 40system.cpu.dtb.write_acv 0 # DTB write access violations 41system.cpu.dtb.write_accesses 868 # DTB write accesses 42system.cpu.dtb.data_hits 2048 # DTB hits 43system.cpu.dtb.data_misses 10 # DTB misses 44system.cpu.dtb.data_acv 0 # DTB access violations 45system.cpu.dtb.data_accesses 2058 # DTB accesses 46system.cpu.itb.fetch_hits 6401 # ITB hits 47system.cpu.itb.fetch_misses 17 # ITB misses 48system.cpu.itb.fetch_acv 0 # ITB acv 49system.cpu.itb.fetch_accesses 6418 # ITB accesses 50system.cpu.itb.read_hits 0 # DTB read hits 51system.cpu.itb.read_misses 0 # DTB read misses 52system.cpu.itb.read_acv 0 # DTB read access violations 53system.cpu.itb.read_accesses 0 # DTB read accesses 54system.cpu.itb.write_hits 0 # DTB write hits 55system.cpu.itb.write_misses 0 # DTB write misses 56system.cpu.itb.write_acv 0 # DTB write access violations 57system.cpu.itb.write_accesses 0 # DTB write accesses 58system.cpu.itb.data_hits 0 # DTB hits 59system.cpu.itb.data_misses 0 # DTB misses 60system.cpu.itb.data_acv 0 # DTB access violations 61system.cpu.itb.data_accesses 0 # DTB accesses 62system.cpu.workload.num_syscalls 17 # Number of system calls 63system.cpu.numCycles 65088 # number of cpu cycles simulated 64system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 65system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 66system.cpu.committedInsts 6390 # Number of instructions committed 67system.cpu.committedOps 6390 # Number of ops (including micro ops) committed 68system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 69system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 70system.cpu.num_func_calls 251 # number of times a function call or return occured 71system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 72system.cpu.num_int_insts 6317 # number of integer instructions 73system.cpu.num_fp_insts 10 # number of float instructions 74system.cpu.num_int_register_reads 8285 # number of times the integer registers were read 75system.cpu.num_int_register_writes 4568 # number of times the integer registers were written 76system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 77system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 78system.cpu.num_mem_refs 2058 # number of memory refs 79system.cpu.num_load_insts 1190 # Number of load instructions 80system.cpu.num_store_insts 868 # Number of store instructions 81system.cpu.num_idle_cycles 0 # Number of idle cycles 82system.cpu.num_busy_cycles 65088 # Number of busy cycles 83system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 84system.cpu.idle_fraction 0 # Percentage of idle cycles 85system.cpu.icache.replacements 0 # number of replacements 86system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use 87system.cpu.icache.total_refs 6122 # Total number of references to valid blocks. 88system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 89system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. 90system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 91system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor 92system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy 93system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy 94system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits 95system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits 96system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits 97system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits 98system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits 99system.cpu.icache.overall_hits::total 6122 # number of overall hits 100system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 101system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 102system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 103system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 104system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 105system.cpu.icache.overall_misses::total 279 # number of overall misses 106system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles 107system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles 108system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles 109system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles 110system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles 111system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles 112system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) 113system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) 114system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses 115system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses 116system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses 117system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses 118system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses 119system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses 120system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses 121system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses 122system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses 123system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses 124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency 125system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency 126system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 127system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency 128system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 129system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency 130system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 131system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 132system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 133system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 134system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 135system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 136system.cpu.icache.fast_writes 0 # number of fast writes performed 137system.cpu.icache.cache_copies 0 # number of cache copies performed 138system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 139system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 140system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 141system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 142system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 143system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 144system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles 145system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles 146system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles 147system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles 148system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles 149system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles 150system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses 151system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses 152system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses 153system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses 154system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses 155system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses 156system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency 157system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency 158system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 159system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 160system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 161system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 162system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 163system.cpu.l2cache.replacements 0 # number of replacements 164system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use 165system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 166system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 167system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 168system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 169system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor 170system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor 171system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy 172system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy 173system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy 174system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 175system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 176system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 177system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 178system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 179system.cpu.l2cache.overall_hits::total 1 # number of overall hits 180system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 181system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 182system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses 183system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 184system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 185system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 186system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 187system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 188system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 189system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 190system.cpu.l2cache.overall_misses::total 446 # number of overall misses 191system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles 192system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles 193system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles 194system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles 195system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles 196system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles 197system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles 198system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles 199system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles 200system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles 201system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles 202system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) 203system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) 204system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) 205system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 206system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 207system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 208system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 209system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 210system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 211system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 212system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 213system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses 214system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 215system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses 216system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 217system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 218system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 219system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 220system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses 221system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 222system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 223system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses 224system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 225system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 226system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 227system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 228system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 229system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 230system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 231system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 232system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 233system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 234system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 235system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 236system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 237system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 238system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 239system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 240system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 241system.cpu.l2cache.fast_writes 0 # number of fast writes performed 242system.cpu.l2cache.cache_copies 0 # number of cache copies performed 243system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 244system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 245system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 246system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 247system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 248system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 249system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 250system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 251system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 252system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 253system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 254system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles 255system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles 256system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles 257system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles 258system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles 259system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 260system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles 261system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles 262system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 263system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles 264system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles 265system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses 266system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 267system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses 268system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 269system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 270system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 271system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 272system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses 273system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 274system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 275system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses 276system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 277system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 278system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 279system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 280system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 281system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 282system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 283system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 284system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 285system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 286system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 287system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 288system.cpu.dcache.replacements 0 # number of replacements 289system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use 290system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. 291system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 292system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. 293system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 294system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor 295system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 296system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy 297system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits 298system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits 299system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 300system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 301system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits 302system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits 303system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits 304system.cpu.dcache.overall_hits::total 1880 # number of overall hits 305system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 306system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 307system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 308system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 309system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 310system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 311system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 312system.cpu.dcache.overall_misses::total 168 # number of overall misses 313system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles 314system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles 315system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles 316system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles 317system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles 318system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles 319system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles 320system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles 321system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) 322system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) 323system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 324system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 325system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses 326system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses 327system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses 328system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses 329system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses 330system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses 331system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 332system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 333system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses 334system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses 335system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses 336system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses 337system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 338system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 339system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 340system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 341system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 342system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 343system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 344system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 345system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 346system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 347system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 348system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 349system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 350system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 351system.cpu.dcache.fast_writes 0 # number of fast writes performed 352system.cpu.dcache.cache_copies 0 # number of cache copies performed 353system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 354system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 355system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 356system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 357system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 358system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 359system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 360system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 361system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles 362system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles 363system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles 364system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles 365system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles 366system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles 367system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles 368system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles 369system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses 370system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses 371system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 372system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 373system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses 374system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses 375system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses 376system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses 377system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 378system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 379system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 380system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 381system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 382system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 383system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 384system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 385system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 386 387---------- End Simulation Statistics ---------- 388