stats.txt revision 11530:6e143fd2cabf
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000036 # Number of seconds simulated 4sim_ticks 35682500 # Number of ticks simulated 5final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 516760 # Simulator instruction rate (inst/s) 8host_op_rate 516348 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2875227341 # Simulator tick rate (ticks/s) 10host_mem_usage 291440 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 6403 # Number of instructions simulated 13sim_ops 6403 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 446 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dtb.fetch_hits 0 # ITB hits 36system.cpu.dtb.fetch_misses 0 # ITB misses 37system.cpu.dtb.fetch_acv 0 # ITB acv 38system.cpu.dtb.fetch_accesses 0 # ITB accesses 39system.cpu.dtb.read_hits 1185 # DTB read hits 40system.cpu.dtb.read_misses 7 # DTB read misses 41system.cpu.dtb.read_acv 0 # DTB read access violations 42system.cpu.dtb.read_accesses 1192 # DTB read accesses 43system.cpu.dtb.write_hits 865 # DTB write hits 44system.cpu.dtb.write_misses 3 # DTB write misses 45system.cpu.dtb.write_acv 0 # DTB write access violations 46system.cpu.dtb.write_accesses 868 # DTB write accesses 47system.cpu.dtb.data_hits 2050 # DTB hits 48system.cpu.dtb.data_misses 10 # DTB misses 49system.cpu.dtb.data_acv 0 # DTB access violations 50system.cpu.dtb.data_accesses 2060 # DTB accesses 51system.cpu.itb.fetch_hits 6414 # ITB hits 52system.cpu.itb.fetch_misses 17 # ITB misses 53system.cpu.itb.fetch_acv 0 # ITB acv 54system.cpu.itb.fetch_accesses 6431 # ITB accesses 55system.cpu.itb.read_hits 0 # DTB read hits 56system.cpu.itb.read_misses 0 # DTB read misses 57system.cpu.itb.read_acv 0 # DTB read access violations 58system.cpu.itb.read_accesses 0 # DTB read accesses 59system.cpu.itb.write_hits 0 # DTB write hits 60system.cpu.itb.write_misses 0 # DTB write misses 61system.cpu.itb.write_acv 0 # DTB write access violations 62system.cpu.itb.write_accesses 0 # DTB write accesses 63system.cpu.itb.data_hits 0 # DTB hits 64system.cpu.itb.data_misses 0 # DTB misses 65system.cpu.itb.data_acv 0 # DTB access violations 66system.cpu.itb.data_accesses 0 # DTB accesses 67system.cpu.workload.num_syscalls 17 # Number of system calls 68system.cpu.pwrStateResidencyTicks::ON 35682500 # Cumulative time (in ticks) in various power states 69system.cpu.numCycles 71365 # number of cpu cycles simulated 70system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 71system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 72system.cpu.committedInsts 6403 # Number of instructions committed 73system.cpu.committedOps 6403 # Number of ops (including micro ops) committed 74system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses 75system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 76system.cpu.num_func_calls 251 # number of times a function call or return occured 77system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls 78system.cpu.num_int_insts 6329 # number of integer instructions 79system.cpu.num_fp_insts 10 # number of float instructions 80system.cpu.num_int_register_reads 8297 # number of times the integer registers were read 81system.cpu.num_int_register_writes 4575 # number of times the integer registers were written 82system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 83system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 84system.cpu.num_mem_refs 2060 # number of memory refs 85system.cpu.num_load_insts 1192 # Number of load instructions 86system.cpu.num_store_insts 868 # Number of store instructions 87system.cpu.num_idle_cycles 0 # Number of idle cycles 88system.cpu.num_busy_cycles 71365 # Number of busy cycles 89system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 90system.cpu.idle_fraction 0 # Percentage of idle cycles 91system.cpu.Branches 1056 # Number of branches fetched 92system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 93system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction 94system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction 95system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction 96system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction 97system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction 98system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction 99system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction 100system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction 101system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction 102system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction 103system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction 104system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction 105system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction 106system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction 107system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction 108system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction 109system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction 110system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction 111system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction 112system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction 113system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction 114system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction 115system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction 116system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction 117system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction 118system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction 119system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction 120system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction 121system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction 122system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction 123system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction 124system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 125system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::total 6413 # Class of executed instruction 127system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 128system.cpu.dcache.tags.replacements 0 # number of replacements 129system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use 130system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks. 131system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 132system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks. 133system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 134system.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor 135system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 136system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy 137system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 138system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 139system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id 140system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id 141system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses 142system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses 143system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 144system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits 145system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits 146system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 147system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 148system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits 149system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits 150system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits 151system.cpu.dcache.overall_hits::total 1882 # number of overall hits 152system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 153system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 154system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 155system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 156system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 157system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 158system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 159system.cpu.dcache.overall_misses::total 168 # number of overall misses 160system.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles 161system.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles 162system.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles 163system.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles 164system.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles 165system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles 166system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles 167system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles 168system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) 169system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) 170system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 171system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 172system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses 173system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses 174system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses 175system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses 176system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses 177system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses 178system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 179system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 180system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses 181system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses 182system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses 183system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses 184system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency 185system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency 186system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency 187system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency 188system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency 189system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency 190system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 191system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 192system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 193system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 194system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 195system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 196system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 197system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 198system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 199system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 200system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 201system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 202system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 203system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 204system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 205system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 206system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles 207system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles 208system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles 209system.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles 210system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles 211system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles 212system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles 213system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles 214system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses 215system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses 216system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 217system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 218system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses 219system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses 220system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses 221system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses 222system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 223system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 224system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 225system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 226system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 227system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 228system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 229system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 230system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 231system.cpu.icache.tags.replacements 0 # number of replacements 232system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use 233system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. 234system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 235system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. 236system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 237system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor 238system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy 239system.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy 240system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id 241system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 242system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id 243system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id 244system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses 245system.cpu.icache.tags.data_accesses 13107 # Number of data accesses 246system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 247system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits 248system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits 249system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits 250system.cpu.icache.demand_hits::total 6135 # number of demand (read+write) hits 251system.cpu.icache.overall_hits::cpu.inst 6135 # number of overall hits 252system.cpu.icache.overall_hits::total 6135 # number of overall hits 253system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 254system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 255system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 256system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 257system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 258system.cpu.icache.overall_misses::total 279 # number of overall misses 259system.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles 260system.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles 261system.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles 262system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles 263system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles 264system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles 265system.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses) 266system.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses) 267system.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses 268system.cpu.icache.demand_accesses::total 6414 # number of demand (read+write) accesses 269system.cpu.icache.overall_accesses::cpu.inst 6414 # number of overall (read+write) accesses 270system.cpu.icache.overall_accesses::total 6414 # number of overall (read+write) accesses 271system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043499 # miss rate for ReadReq accesses 272system.cpu.icache.ReadReq_miss_rate::total 0.043499 # miss rate for ReadReq accesses 273system.cpu.icache.demand_miss_rate::cpu.inst 0.043499 # miss rate for demand accesses 274system.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses 275system.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses 276system.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses 277system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency 278system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency 279system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency 280system.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency 281system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency 282system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency 283system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 284system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 285system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 286system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 287system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 288system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 289system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 290system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 291system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 292system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 293system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 294system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 295system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles 296system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles 297system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles 298system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles 299system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles 300system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles 301system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses 302system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses 303system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses 304system.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses 305system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses 306system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses 307system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency 308system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency 309system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 310system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency 311system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 312system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency 313system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 314system.cpu.l2cache.tags.replacements 0 # number of replacements 315system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use 316system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 317system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 318system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 319system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 320system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor 321system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor 322system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy 323system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy 324system.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy 325system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 326system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 327system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 328system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id 329system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses 330system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses 331system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 332system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 333system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 334system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 335system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 336system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 337system.cpu.l2cache.overall_hits::total 1 # number of overall hits 338system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 339system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 340system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses 341system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses 342system.cpu.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 343system.cpu.l2cache.ReadSharedReq_misses::total 95 # number of ReadSharedReq misses 344system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 345system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 346system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 347system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 348system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 349system.cpu.l2cache.overall_misses::total 446 # number of overall misses 350system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles 351system.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles 352system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles 353system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles 354system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles 355system.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles 356system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles 357system.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles 358system.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles 359system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles 360system.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles 361system.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles 362system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 363system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 364system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) 365system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses) 366system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 367system.cpu.l2cache.ReadSharedReq_accesses::total 95 # number of ReadSharedReq accesses(hits+misses) 368system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 369system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 370system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 371system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 372system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 373system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 374system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 375system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 376system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses 377system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses 378system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 379system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 380system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 381system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 382system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses 383system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 384system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 385system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses 386system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 387system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 388system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency 389system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency 390system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 391system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 392system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency 393system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 394system.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency 395system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency 396system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 397system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency 398system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 399system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 400system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 401system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 402system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 403system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 404system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 405system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 406system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses 407system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses 408system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 409system.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses 410system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 411system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 412system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 413system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 414system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 415system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 416system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles 417system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles 418system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles 419system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles 420system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles 421system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles 422system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles 423system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles 424system.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles 425system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles 426system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles 427system.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles 428system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 429system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 430system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses 431system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses 432system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 433system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 434system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 435system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 436system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses 437system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 438system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 439system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses 440system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 441system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 442system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency 443system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency 444system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 445system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 446system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 447system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 448system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency 449system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 450system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 451system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency 452system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. 453system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 454system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 455system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 458system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 459system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 460system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution 464system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 465system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) 467system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) 468system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 470system.cpu.toL2Bus.snoops 0 # Total snoops (count) 471system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram 472system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram 473system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram 474system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 475system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram 476system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram 477system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 478system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 479system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram 482system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 483system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 484system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 485system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) 486system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 487system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 488system.membus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states 489system.membus.trans_dist::ReadResp 373 # Transaction distribution 490system.membus.trans_dist::ReadExReq 73 # Transaction distribution 491system.membus.trans_dist::ReadExResp 73 # Transaction distribution 492system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 493system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 494system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 495system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 496system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 497system.membus.snoops 0 # Total snoops (count) 498system.membus.snoop_fanout::samples 446 # Request fanout histogram 499system.membus.snoop_fanout::mean 0 # Request fanout histogram 500system.membus.snoop_fanout::stdev 0 # Request fanout histogram 501system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 502system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 503system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 504system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 505system.membus.snoop_fanout::min_value 0 # Request fanout histogram 506system.membus.snoop_fanout::max_value 0 # Request fanout histogram 507system.membus.snoop_fanout::total 446 # Request fanout histogram 508system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) 509system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 510system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks) 511system.membus.respLayer1.utilization 6.2 # Layer utilization (%) 512 513---------- End Simulation Statistics ---------- 514