stats.txt revision 9285
13048SN/A 23048SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 0.000033 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 32544000 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79285Sandreas.hansson@arm.comhost_inst_rate 68117 # Simulator instruction rate (inst/s) 89285Sandreas.hansson@arm.comhost_op_rate 68101 # Simulator op (including micro ops) rate (op/s) 99285Sandreas.hansson@arm.comhost_tick_rate 346770993 # Simulator tick rate (ticks/s) 109285Sandreas.hansson@arm.comhost_mem_usage 218620 # Number of bytes of host memory used 119285Sandreas.hansson@arm.comhost_seconds 0.09 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6390 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6390 # Number of ops (including micro ops) simulated 149055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 159055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28544 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 209055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 446 # Number of read requests responded to by this memory 229285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) 239285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) 249285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) 259285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) 269285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) 279285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) 289285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 318428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 328428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 338428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 349150SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 1183 # DTB read hits 358428SN/Asystem.cpu.dtb.read_misses 7 # DTB read misses 368428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 379150SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 1190 # DTB read accesses 388428SN/Asystem.cpu.dtb.write_hits 865 # DTB write hits 398428SN/Asystem.cpu.dtb.write_misses 3 # DTB write misses 408428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 418428SN/Asystem.cpu.dtb.write_accesses 868 # DTB write accesses 429150SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits 2048 # DTB hits 438428SN/Asystem.cpu.dtb.data_misses 10 # DTB misses 448428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 459150SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses 2058 # DTB accesses 469150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits 6401 # ITB hits 478428SN/Asystem.cpu.itb.fetch_misses 17 # ITB misses 488428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 499150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses 6418 # ITB accesses 508428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 518428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 528428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 538428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 548428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 558428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 568428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 578428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 588428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 598428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 608428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 618428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 628428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 639285Sandreas.hansson@arm.comsystem.cpu.numCycles 65088 # number of cpu cycles simulated 648428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 658428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 669150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6390 # Number of instructions committed 679150SAli.Saidi@ARM.comsystem.cpu.committedOps 6390 # Number of ops (including micro ops) committed 689150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 698428SN/Asystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 708428SN/Asystem.cpu.num_func_calls 251 # number of times a function call or return occured 719150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 729150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 6317 # number of integer instructions 738428SN/Asystem.cpu.num_fp_insts 10 # number of float instructions 749150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 8285 # number of times the integer registers were read 759150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 4568 # number of times the integer registers were written 768428SN/Asystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 778428SN/Asystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 789150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 2058 # number of memory refs 799150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 1190 # Number of load instructions 808428SN/Asystem.cpu.num_store_insts 868 # Number of store instructions 818428SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 829285Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 65088 # Number of busy cycles 838428SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 848428SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 858428SN/Asystem.cpu.icache.replacements 0 # number of replacements 869285Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use 879150SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 6122 # Total number of references to valid blocks. 888428SN/Asystem.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 899150SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. 908428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 919285Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor 929285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy 939285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy 949150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits 959150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits 969150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits 979150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits 989150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits 999150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 6122 # number of overall hits 1008835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 1018835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 1028835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 1038835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 1048835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 1058835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 279 # number of overall misses 1069285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles 1079285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles 1089285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles 1099285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles 1109285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles 1119285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles 1129150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) 1139150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) 1149150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses 1159150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses 1169150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses 1179150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses 1189150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses 1199150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses 1209150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses 1219150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses 1229150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses 1239150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses 1249285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency 1259285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency 1269285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 1279285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency 1289285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 1299285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency 1308428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1318428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1328428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1338428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1348983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1358983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1368428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1378428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1388835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 1398835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 1408835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 1418835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 1428835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 1438835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 1448835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles 1458835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles 1468835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles 1478835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles 1488835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles 1498835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles 1509150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses 1519150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses 1529150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses 1539150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses 1549150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses 1559150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses 1568835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency 1579055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency 1588835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 1599055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 1608835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 1619055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 1628428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1638428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 1649285Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use 1659150SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. 1668428SN/Asystem.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 1679150SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. 1688428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1699285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor 1709285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 1719285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy 1729150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits 1739150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits 1748835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 1758835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 1769150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits 1779150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits 1789150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits 1799150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 1880 # number of overall hits 1808835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 1818835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 1828835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 1838835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 1848835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 1858835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 1868835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 1878835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 168 # number of overall misses 1889285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles 1899285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles 1909285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles 1919285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles 1929285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles 1939285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles 1949285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles 1959285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles 1969150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) 1979150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) 1988835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 1998835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 2009150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses 2019150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses 2029150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses 2039150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses 2049150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses 2059150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses 2068835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 2079055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 2089150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses 2099150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses 2109150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses 2119150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses 2129285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 2139285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 2149285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 2159285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 2169285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 2179285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 2189285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 2199285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 2208428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2218428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2228428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2238428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 2248983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2258983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2268428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 2273048SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 2288835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 2298835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 2308835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 2318835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 2328835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 2338835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 2348835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 2358835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 2368835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles 2378835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles 2388835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles 2398835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles 2408835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles 2418835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles 2428835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles 2438835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles 2449150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses 2459150SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses 2468835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 2479055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 2489150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses 2499150SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses 2509150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses 2519150SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses 2528835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 2539055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 2548835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 2559055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 2568835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 2579055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 2588835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 2599055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 2608428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2618428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 2629285Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use 2638428SN/Asystem.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 2648428SN/Asystem.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 2658428SN/Asystem.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 2668428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2679285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor 2689285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor 2699285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy 2709285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy 2719285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy 2728835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 2738835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 2748835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 2758835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 2768835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 2778835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 2788835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 2798835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 2808835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses 2818835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 2828835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 2838835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 2848835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 2858835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 2868835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 2878835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 2888835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 446 # number of overall misses 2898835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles 2908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles 2918835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles 2928835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles 2938835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles 2948835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles 2958835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles 2968835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles 2978835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles 2988835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles 2998835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles 3008835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) 3018835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) 3028835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) 3038835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 3048835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 3058835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 3068835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 3078835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 3088835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 3098835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 3108835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 3118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses 3128835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 3139055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses 3148835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 3159055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 3168835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 3178835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 3189055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses 3198835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 3208835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 3219055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses 3228835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 3238835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 3249055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 3258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 3269055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 3278835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 3288835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 3299055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 3308835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 3318835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 3329055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 3338428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3348428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3358428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 3368428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 3378983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3388983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3398428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 3403048SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 3418835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 3428835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 3438835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 3448835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 3458835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 3468835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 3478835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 3488835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 3498835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 3508835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 3518835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 3528835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles 3538835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles 3548835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles 3558835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles 3568835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles 3578835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 3588835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles 3598835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles 3608835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 3618835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles 3628835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles 3638835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses 3648835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 3659055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses 3668835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 3679055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 3688835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 3698835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 3709055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses 3718835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 3728835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 3739055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses 3748835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 3758835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 3769055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 3778835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 3789055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 3798835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3808835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3819055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 3828835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3838835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3849055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 3858428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 3863048SN/A 3873048SN/A---------- End Simulation Statistics ---------- 388