stats.txt revision 8835
13048SN/A 23048SN/A---------- Begin Simulation Statistics ---------- 37670SN/Asim_seconds 0.000033 # Number of seconds simulated 47670SN/Asim_ticks 33007000 # Number of ticks simulated 58721SN/Afinal_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 78835SAli.Saidi@ARM.comhost_inst_rate 37663 # Simulator instruction rate (inst/s) 88835SAli.Saidi@ARM.comhost_op_rate 37658 # Simulator op (including micro ops) rate (op/s) 98835SAli.Saidi@ARM.comhost_tick_rate 194071847 # Simulator tick rate (ticks/s) 108835SAli.Saidi@ARM.comhost_mem_usage 209060 # Number of bytes of host memory used 118835SAli.Saidi@ARM.comhost_seconds 0.17 # Real time elapsed on the host 128428SN/Asim_insts 6404 # Number of instructions simulated 138835SAli.Saidi@ARM.comsim_ops 6404 # Number of ops (including micro ops) simulated 148721SN/Asystem.physmem.bytes_read 28544 # Number of bytes read from this memory 158721SN/Asystem.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory 168721SN/Asystem.physmem.bytes_written 0 # Number of bytes written to this memory 178721SN/Asystem.physmem.num_reads 446 # Number of read requests responded to by this memory 188721SN/Asystem.physmem.num_writes 0 # Number of write requests responded to by this memory 198721SN/Asystem.physmem.num_other 0 # Number of other requests responded to by this memory 208721SN/Asystem.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s) 218721SN/Asystem.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s) 228721SN/Asystem.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s) 238428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 248428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 258428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 268428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 278428SN/Asystem.cpu.dtb.read_hits 1185 # DTB read hits 288428SN/Asystem.cpu.dtb.read_misses 7 # DTB read misses 298428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 308428SN/Asystem.cpu.dtb.read_accesses 1192 # DTB read accesses 318428SN/Asystem.cpu.dtb.write_hits 865 # DTB write hits 328428SN/Asystem.cpu.dtb.write_misses 3 # DTB write misses 338428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 348428SN/Asystem.cpu.dtb.write_accesses 868 # DTB write accesses 358428SN/Asystem.cpu.dtb.data_hits 2050 # DTB hits 368428SN/Asystem.cpu.dtb.data_misses 10 # DTB misses 378428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 388428SN/Asystem.cpu.dtb.data_accesses 2060 # DTB accesses 398428SN/Asystem.cpu.itb.fetch_hits 6415 # ITB hits 408428SN/Asystem.cpu.itb.fetch_misses 17 # ITB misses 418428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 428428SN/Asystem.cpu.itb.fetch_accesses 6432 # ITB accesses 438428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 448428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 458428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 468428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 478428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 488428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 498428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 508428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 518428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 528428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 538428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 548428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 558428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 568428SN/Asystem.cpu.numCycles 66014 # number of cpu cycles simulated 578428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 588428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 598835SAli.Saidi@ARM.comsystem.cpu.committedInsts 6404 # Number of instructions committed 608835SAli.Saidi@ARM.comsystem.cpu.committedOps 6404 # Number of ops (including micro ops) committed 618428SN/Asystem.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses 628428SN/Asystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 638428SN/Asystem.cpu.num_func_calls 251 # number of times a function call or return occured 648428SN/Asystem.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls 658428SN/Asystem.cpu.num_int_insts 6331 # number of integer instructions 668428SN/Asystem.cpu.num_fp_insts 10 # number of float instructions 678428SN/Asystem.cpu.num_int_register_reads 8304 # number of times the integer registers were read 688428SN/Asystem.cpu.num_int_register_writes 4581 # number of times the integer registers were written 698428SN/Asystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 708428SN/Asystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 718428SN/Asystem.cpu.num_mem_refs 2060 # number of memory refs 728428SN/Asystem.cpu.num_load_insts 1192 # Number of load instructions 738428SN/Asystem.cpu.num_store_insts 868 # Number of store instructions 748428SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 758428SN/Asystem.cpu.num_busy_cycles 66014 # Number of busy cycles 768428SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 778428SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 788428SN/Asystem.cpu.icache.replacements 0 # number of replacements 798428SN/Asystem.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use 808428SN/Asystem.cpu.icache.total_refs 6136 # Total number of references to valid blocks. 818428SN/Asystem.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 828428SN/Asystem.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. 838428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 848835SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor 858835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy 868835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy 878835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits 888835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits 898835SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits 908835SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits 918835SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits 928835SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 6136 # number of overall hits 938835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 948835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 958835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 968835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 978835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 988835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 279 # number of overall misses 998835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles 1008835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles 1018835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles 1028835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles 1038835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles 1048835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles 1058835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 6415 # number of ReadReq accesses(hits+misses) 1068835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 6415 # number of ReadReq accesses(hits+misses) 1078835SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 6415 # number of demand (read+write) accesses 1088835SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 6415 # number of demand (read+write) accesses 1098835SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses 1108835SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses 1118835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses 1128835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses 1138835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses 1148835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency 1158835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency 1168835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency 1178428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1188428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1198428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1208428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1218428SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1228428SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1238428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1248428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1258835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 1268835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 1278835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 1288835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 1298835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 1308835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 1318835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles 1328835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles 1338835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles 1348835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles 1358835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles 1368835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles 1378835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses 1388835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses 1398835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses 1408835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency 1418835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 1428835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 1438428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1448428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 1458428SN/Asystem.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use 1468428SN/Asystem.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. 1478428SN/Asystem.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 1488428SN/Asystem.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. 1498428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1508835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor 1518835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.025313 # Average percentage of cache occupancy 1528835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.025313 # Average percentage of cache occupancy 1538835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits 1548835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits 1558835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 1568835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 1578835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits 1588835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits 1598835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits 1608835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 1882 # number of overall hits 1618835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 1628835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 1638835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 1648835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 1658835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 1668835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 1678835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 1688835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 168 # number of overall misses 1698835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles 1708835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles 1718835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles 1728835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles 1738835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles 1748835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles 1758835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles 1768835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles 1778835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) 1788835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) 1798835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 1808835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 1818835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses 1828835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses 1838835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses 1848835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses 1858835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses 1868835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 1878835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses 1888835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses 1898835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 1908835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 1918835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 1928835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 1938428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1948428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1958428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1968428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1976127SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1986127SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1998428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 2003048SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 2018835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 2028835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 2038835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 2048835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 2058835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 2068835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 2078835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 2088835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 2098835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles 2108835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles 2118835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles 2128835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles 2138835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles 2148835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles 2158835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles 2168835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles 2178835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses 2188835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 2198835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses 2208835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses 2218835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 2228835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 2238835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 2248835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 2258428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2268428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 2278428SN/Asystem.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use 2288428SN/Asystem.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 2298428SN/Asystem.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 2308428SN/Asystem.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 2318428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2328835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor 2338835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 56.441756 # Average occupied blocks per requestor 2348835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.003903 # Average percentage of cache occupancy 2358835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy 2368835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.005626 # Average percentage of cache occupancy 2378835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 2388835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 2398835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 2408835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 2418835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 2428835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 2438835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 2448835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 2458835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses 2468835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 2478835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 2488835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 2498835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 2508835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 2518835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 2528835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 2538835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 446 # number of overall misses 2548835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles 2558835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles 2568835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles 2578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles 2588835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles 2598835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles 2608835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles 2618835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles 2628835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles 2638835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles 2648835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles 2658835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) 2668835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) 2678835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) 2688835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 2698835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 2708835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 2718835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 2728835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 2738835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 2748835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 2758835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 2768835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses 2778835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 2788835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 2798835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 2808835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 2818835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 2828835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 2838835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 2848835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 2858835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 2868835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2878835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 2888835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2898835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 2908428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2918428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2928428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2938428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2946127SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 2956127SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 2968428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 2973048SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 2988835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 2998835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 3008835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 3018835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 3028835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 3038835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 3048835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 3058835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 3068835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 3078835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 3088835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 3098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles 3108835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles 3118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles 3128835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles 3138835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles 3148835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 3158835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles 3168835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles 3178835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 3188835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles 3198835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles 3208835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses 3218835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 3228835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 3238835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 3248835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 3258835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 3268835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 3278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 3288835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 3298835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 3308835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3318835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3328835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3338835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3348428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 3353048SN/A 3363048SN/A---------- End Simulation Statistics ---------- 337