stats.txt revision 11390
13048SN/A 23048SN/A---------- Begin Simulation Statistics ---------- 311201Sandreas.hansson@arm.comsim_seconds 0.000036 # Number of seconds simulated 411390Ssteve.reinhardt@amd.comsim_ticks 35682500 # Number of ticks simulated 511390Ssteve.reinhardt@amd.comfinal_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711390Ssteve.reinhardt@amd.comhost_inst_rate 44587 # Simulator instruction rate (inst/s) 811390Ssteve.reinhardt@amd.comhost_op_rate 44581 # Simulator op (including micro ops) rate (op/s) 911390Ssteve.reinhardt@amd.comhost_tick_rate 248411942 # Simulator tick rate (ticks/s) 1011390Ssteve.reinhardt@amd.comhost_mem_usage 226904 # Number of bytes of host memory used 1111390Ssteve.reinhardt@amd.comhost_seconds 0.14 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 6403 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 6403 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28544 # Number of bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 209055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 229055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 239055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 446 # Number of read requests responded to by this memory 2411390Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s) 2511390Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s) 2611390Ssteve.reinhardt@amd.comsystem.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s) 2711390Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s) 2811390Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s) 2911390Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s) 3011390Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s) 3111390Ssteve.reinhardt@amd.comsystem.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s) 3210036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 338428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 348428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 358428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 368428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 3711390Ssteve.reinhardt@amd.comsystem.cpu.dtb.read_hits 1185 # DTB read hits 388428SN/Asystem.cpu.dtb.read_misses 7 # DTB read misses 398428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 4011390Ssteve.reinhardt@amd.comsystem.cpu.dtb.read_accesses 1192 # DTB read accesses 418428SN/Asystem.cpu.dtb.write_hits 865 # DTB write hits 428428SN/Asystem.cpu.dtb.write_misses 3 # DTB write misses 438428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 448428SN/Asystem.cpu.dtb.write_accesses 868 # DTB write accesses 4511390Ssteve.reinhardt@amd.comsystem.cpu.dtb.data_hits 2050 # DTB hits 468428SN/Asystem.cpu.dtb.data_misses 10 # DTB misses 478428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 4811390Ssteve.reinhardt@amd.comsystem.cpu.dtb.data_accesses 2060 # DTB accesses 4911390Ssteve.reinhardt@amd.comsystem.cpu.itb.fetch_hits 6414 # ITB hits 508428SN/Asystem.cpu.itb.fetch_misses 17 # ITB misses 518428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 5211390Ssteve.reinhardt@amd.comsystem.cpu.itb.fetch_accesses 6431 # ITB accesses 538428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 548428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 558428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 568428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 578428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 588428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 598428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 608428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 618428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 628428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 638428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 648428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 658428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 6611390Ssteve.reinhardt@amd.comsystem.cpu.numCycles 71365 # number of cpu cycles simulated 678428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 688428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 6911390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 6403 # Number of instructions committed 7011390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 6403 # Number of ops (including micro ops) committed 7111390Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses 728428SN/Asystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 738428SN/Asystem.cpu.num_func_calls 251 # number of times a function call or return occured 7411390Ssteve.reinhardt@amd.comsystem.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls 7511390Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 6329 # number of integer instructions 768428SN/Asystem.cpu.num_fp_insts 10 # number of float instructions 7711390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 8297 # number of times the integer registers were read 7811390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 4575 # number of times the integer registers were written 798428SN/Asystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 808428SN/Asystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 8111390Ssteve.reinhardt@amd.comsystem.cpu.num_mem_refs 2060 # number of memory refs 8211390Ssteve.reinhardt@amd.comsystem.cpu.num_load_insts 1192 # Number of load instructions 838428SN/Asystem.cpu.num_store_insts 868 # Number of store instructions 848428SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 8511390Ssteve.reinhardt@amd.comsystem.cpu.num_busy_cycles 71365 # Number of busy cycles 868428SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 878428SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 8811390Ssteve.reinhardt@amd.comsystem.cpu.Branches 1056 # Number of branches fetched 8910220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 9011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction 9111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction 9211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction 9311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction 9411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction 9511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction 9611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction 9711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction 9811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction 9911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction 10011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction 10111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction 10211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction 10311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction 10411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction 10511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction 10611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction 10711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction 10811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction 10911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction 11011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction 11111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction 11211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction 11311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction 11411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction 11511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction 11611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction 11711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction 11811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction 11911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction 12011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction 12110220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 12210220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 12311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::total 6413 # Class of executed instruction 1249838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 12511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use 12611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks. 1279838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 12811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks. 1299838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 13011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor 13111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 13211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy 13310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 13411201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 13511201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id 13610036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id 13711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses 13811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.data_accesses 4268 # Number of data accesses 13911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits 14011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits 1419481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 1429481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 14311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits 14411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits 14511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits 14611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::total 1882 # number of overall hits 1479481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 1489481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 1499481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 1509481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 1519481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 1529481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 1539481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 1549481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 168 # number of overall misses 15511201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles 15611201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles 15711201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles 15811201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles 15911201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles 16011201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles 16111201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles 16211201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles 16311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) 16411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) 1659481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 1669481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 16711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses 16811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses 16911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses 17011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses 17111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses 17211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses 1739481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 1749481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 17511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses 17611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses 17711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses 17811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses 17911201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency 18011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency 18111201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency 18211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency 18311201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency 18411201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency 18511201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 18611201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 1879481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1889481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1899481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1909481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1919481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1929481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1939481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 1949481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 1959481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 1969481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 1979481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 1989481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 1999481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 2009481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 2019481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 2029481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 20311201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles 20411201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles 20511201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles 20611201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles 20711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles 20811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles 20911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles 21011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles 21111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses 21211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses 2139481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 2149481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 21511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses 21611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses 21711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses 21811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses 21911201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 22011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 22111201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 22211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 22311201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 22411201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 22511201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 22611201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 2279481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 22810726Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 22911390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use 23011390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. 23110726Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 23211390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. 23310726Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 23411390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor 23511390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy 23611390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy 23710726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id 23811201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 23911201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id 24010726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id 24111390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses 24211390Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.data_accesses 13107 # Number of data accesses 24311390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits 24411390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits 24511390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits 24611390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::total 6135 # number of demand (read+write) hits 24711390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::cpu.inst 6135 # number of overall hits 24811390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::total 6135 # number of overall hits 24910726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 25010726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 25110726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 25210726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 25310726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 25410726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 279 # number of overall misses 25511201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles 25611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles 25711201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles 25811201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles 25911201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles 26011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles 26111390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses) 26211390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses) 26311390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses 26411390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::total 6414 # number of demand (read+write) accesses 26511390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::cpu.inst 6414 # number of overall (read+write) accesses 26611390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::total 6414 # number of overall (read+write) accesses 26711390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043499 # miss rate for ReadReq accesses 26811390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::total 0.043499 # miss rate for ReadReq accesses 26911390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.043499 # miss rate for demand accesses 27011390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses 27111390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses 27211390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses 27311201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency 27411201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency 27511201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency 27611201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency 27711201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency 27811201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency 27910726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 28010726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 28110726Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 28210726Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 28310726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 28410726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 28510726Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 28610726Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 28710726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 28810726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 28910726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 29010726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 29110726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 29210726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 29311201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles 29411201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles 29511201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles 29611201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles 29711201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles 29811201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles 29911390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses 30011390Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses 30111390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses 30211390Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses 30311390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses 30411390Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses 30511201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency 30611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency 30711201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 30811201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency 30911201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 31011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency 31110726Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 31210726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 31311390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use 31410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 31510726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 31610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 31710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 31811390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor 31911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor 32011390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy 32111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy 32211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy 32310726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 32411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 32511201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 32610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id 32710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses 32810726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses 32910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 33010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 33110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 33210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 33310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 33410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 33510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 33610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 33710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses 33810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses 33910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 34010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 95 # number of ReadSharedReq misses 34110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 34210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 34310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 34410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 34510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 34610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 446 # number of overall misses 34711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles 34811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles 34911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles 35011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles 35111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles 35211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles 35311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles 35411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles 35511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles 35611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles 35711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles 35811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles 35910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 36010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 36110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) 36210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses) 36310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 36410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 95 # number of ReadSharedReq accesses(hits+misses) 36510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 36610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 36710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 36810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 36910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 37010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 37110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 37210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 37310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses 37410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses 37510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 37610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 37710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 37810726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 37910726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses 38010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 38110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 38210726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses 38311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 38411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 38511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency 38611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency 38711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 38811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 38911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency 39011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 39111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency 39211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency 39311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 39411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency 39510726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39610726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39710726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 39810726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 39910726Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 40010726Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 40110726Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 40210726Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 40310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 40410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 40510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses 40610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses 40710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 40810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses 40910726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 41010726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 41110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 41210726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 41310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 41410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 41511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles 41611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles 41711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles 41811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles 41911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles 42011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles 42111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles 42211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles 42311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles 42411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles 42511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles 42611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles 42710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 42810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 42910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses 43010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses 43110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 43210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 43310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 43410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 43510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses 43610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 43710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 43810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses 43911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 44011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 44111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency 44211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency 44311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 44411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 44511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 44611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 44711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency 44811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 44911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 45011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency 45110726Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 45211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. 45311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 45411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 45511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 45611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 45711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 4589729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 4599729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 4609729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 46110892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution 46210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution 4639838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 4649838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 4659838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) 46610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) 46710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 46810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 46910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 47010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram 47111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram 47211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram 47310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 47411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram 47511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram 47610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 47710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 47811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 47910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 48010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram 4819729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 48211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 4839729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 48411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) 4859729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 48611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 48710726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 373 # Transaction distribution 48810726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 73 # Transaction distribution 48910726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 73 # Transaction distribution 49010892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 49110726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 49210726Sandreas.hansson@arm.comsystem.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 49310726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 49410726Sandreas.hansson@arm.comsystem.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 49510726Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 49610726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 446 # Request fanout histogram 49710726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 49810726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 49910726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 50010726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 50110726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 50210726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 50310726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 50410726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 50510726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 446 # Request fanout histogram 50610726Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) 50711201Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 50811201Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks) 50911390Ssteve.reinhardt@amd.comsystem.membus.respLayer1.utilization 6.2 # Layer utilization (%) 5103048SN/A 5113048SN/A---------- End Simulation Statistics ---------- 512