config.ini revision 5355
19792Sandreas.hansson@arm.com[root] 29380SAndreas.Sandberg@ARM.comtype=Root 39380SAndreas.Sandberg@ARM.comchildren=system 49380SAndreas.Sandberg@ARM.comdummy=0 59380SAndreas.Sandberg@ARM.com 69380SAndreas.Sandberg@ARM.com[system] 79380SAndreas.Sandberg@ARM.comtype=System 89380SAndreas.Sandberg@ARM.comchildren=cpu membus physmem 99380SAndreas.Sandberg@ARM.commem_mode=atomic 109380SAndreas.Sandberg@ARM.comphysmem=system.physmem 119380SAndreas.Sandberg@ARM.com 129380SAndreas.Sandberg@ARM.com[system.cpu] 139380SAndreas.Sandberg@ARM.comtype=TimingSimpleCPU 149380SAndreas.Sandberg@ARM.comchildren=dcache dtb icache itb l2cache toL2Bus tracer workload 159380SAndreas.Sandberg@ARM.comclock=500 169380SAndreas.Sandberg@ARM.comcpu_id=0 179380SAndreas.Sandberg@ARM.comdefer_registration=false 189380SAndreas.Sandberg@ARM.comdtb=system.cpu.dtb 199380SAndreas.Sandberg@ARM.comfunction_trace=false 209380SAndreas.Sandberg@ARM.comfunction_trace_start=0 219380SAndreas.Sandberg@ARM.comitb=system.cpu.itb 229380SAndreas.Sandberg@ARM.commax_insts_all_threads=0 239380SAndreas.Sandberg@ARM.commax_insts_any_thread=0 249380SAndreas.Sandberg@ARM.commax_loads_all_threads=0 259380SAndreas.Sandberg@ARM.commax_loads_any_thread=0 269380SAndreas.Sandberg@ARM.comphase=0 279380SAndreas.Sandberg@ARM.comprogress_interval=0 289380SAndreas.Sandberg@ARM.comsystem=system 299380SAndreas.Sandberg@ARM.comtracer=system.cpu.tracer 309380SAndreas.Sandberg@ARM.comworkload=system.cpu.workload 319380SAndreas.Sandberg@ARM.comdcache_port=system.cpu.dcache.cpu_side 329380SAndreas.Sandberg@ARM.comicache_port=system.cpu.icache.cpu_side 339380SAndreas.Sandberg@ARM.com 349380SAndreas.Sandberg@ARM.com[system.cpu.dcache] 359380SAndreas.Sandberg@ARM.comtype=BaseCache 369380SAndreas.Sandberg@ARM.comaddr_range=0:18446744073709551615 379792Sandreas.hansson@arm.comassoc=2 389380SAndreas.Sandberg@ARM.comblock_size=64 399380SAndreas.Sandberg@ARM.comcpu_side_filter_ranges= 409380SAndreas.Sandberg@ARM.comhash_delay=1 419380SAndreas.Sandberg@ARM.comlatency=1000 429380SAndreas.Sandberg@ARM.comlifo=false 439380SAndreas.Sandberg@ARM.commax_miss_count=0 449380SAndreas.Sandberg@ARM.commem_side_filter_ranges= 459380SAndreas.Sandberg@ARM.commshrs=10 469380SAndreas.Sandberg@ARM.comprefetch_access=false 479654SAndreas.Sandberg@ARM.comprefetch_cache_check_push=true 489654SAndreas.Sandberg@ARM.comprefetch_data_accesses_only=false 499380SAndreas.Sandberg@ARM.comprefetch_degree=1 509380SAndreas.Sandberg@ARM.comprefetch_latency=10000 519380SAndreas.Sandberg@ARM.comprefetch_miss=false 529380SAndreas.Sandberg@ARM.comprefetch_past_page=false 539380SAndreas.Sandberg@ARM.comprefetch_policy=none 549380SAndreas.Sandberg@ARM.comprefetch_serial_squash=false 559380SAndreas.Sandberg@ARM.comprefetch_use_cpu_id=true 569380SAndreas.Sandberg@ARM.comprefetcher_size=100 579380SAndreas.Sandberg@ARM.comprioritizeRequests=false 589380SAndreas.Sandberg@ARM.comrepl=Null 599380SAndreas.Sandberg@ARM.comsize=262144 609792Sandreas.hansson@arm.comsplit=false 619792Sandreas.hansson@arm.comsplit_size=0 629792Sandreas.hansson@arm.comsubblock_size=0 639380SAndreas.Sandberg@ARM.comtgts_per_mshr=5 649380SAndreas.Sandberg@ARM.comtrace_addr=0 659380SAndreas.Sandberg@ARM.comtwo_queue=false 669792Sandreas.hansson@arm.comwrite_buffers=8 679380SAndreas.Sandberg@ARM.comcpu_side=system.cpu.dcache_port 689380SAndreas.Sandberg@ARM.commem_side=system.cpu.toL2Bus.port[1] 699380SAndreas.Sandberg@ARM.com 709380SAndreas.Sandberg@ARM.com[system.cpu.dtb] 719380SAndreas.Sandberg@ARM.comtype=AlphaDTB 729792Sandreas.hansson@arm.comsize=64 739380SAndreas.Sandberg@ARM.com 749380SAndreas.Sandberg@ARM.com[system.cpu.icache] 759380SAndreas.Sandberg@ARM.comtype=BaseCache 769380SAndreas.Sandberg@ARM.comaddr_range=0:18446744073709551615 779793Sakash.bagdia@arm.comassoc=2 789380SAndreas.Sandberg@ARM.comblock_size=64 799793Sakash.bagdia@arm.comcpu_side_filter_ranges= 809793Sakash.bagdia@arm.comhash_delay=1 819380SAndreas.Sandberg@ARM.comlatency=1000 829380SAndreas.Sandberg@ARM.comlifo=false 839380SAndreas.Sandberg@ARM.commax_miss_count=0 849380SAndreas.Sandberg@ARM.commem_side_filter_ranges= 859380SAndreas.Sandberg@ARM.commshrs=10 869380SAndreas.Sandberg@ARM.comprefetch_access=false 879380SAndreas.Sandberg@ARM.comprefetch_cache_check_push=true 889380SAndreas.Sandberg@ARM.comprefetch_data_accesses_only=false 899380SAndreas.Sandberg@ARM.comprefetch_degree=1 909380SAndreas.Sandberg@ARM.comprefetch_latency=10000 919380SAndreas.Sandberg@ARM.comprefetch_miss=false 929380SAndreas.Sandberg@ARM.comprefetch_past_page=false 939380SAndreas.Sandberg@ARM.comprefetch_policy=none 949380SAndreas.Sandberg@ARM.comprefetch_serial_squash=false 959380SAndreas.Sandberg@ARM.comprefetch_use_cpu_id=true 969380SAndreas.Sandberg@ARM.comprefetcher_size=100 979380SAndreas.Sandberg@ARM.comprioritizeRequests=false 989380SAndreas.Sandberg@ARM.comrepl=Null 999380SAndreas.Sandberg@ARM.comsize=131072 1009380SAndreas.Sandberg@ARM.comsplit=false 1019380SAndreas.Sandberg@ARM.comsplit_size=0 1029380SAndreas.Sandberg@ARM.comsubblock_size=0 1039380SAndreas.Sandberg@ARM.comtgts_per_mshr=5 1049380SAndreas.Sandberg@ARM.comtrace_addr=0 1059793Sakash.bagdia@arm.comtwo_queue=false 1069793Sakash.bagdia@arm.comwrite_buffers=8 1079793Sakash.bagdia@arm.comcpu_side=system.cpu.icache_port 1089380SAndreas.Sandberg@ARM.commem_side=system.cpu.toL2Bus.port[0] 1099380SAndreas.Sandberg@ARM.com 1109380SAndreas.Sandberg@ARM.com[system.cpu.itb] 1119380SAndreas.Sandberg@ARM.comtype=AlphaITB 1129674Snilay@cs.wisc.edusize=48 1139380SAndreas.Sandberg@ARM.com 1149380SAndreas.Sandberg@ARM.com[system.cpu.l2cache] 1159380SAndreas.Sandberg@ARM.comtype=BaseCache 1169380SAndreas.Sandberg@ARM.comaddr_range=0:18446744073709551615 1179380SAndreas.Sandberg@ARM.comassoc=2 1189380SAndreas.Sandberg@ARM.comblock_size=64 1199674Snilay@cs.wisc.educpu_side_filter_ranges= 1209674Snilay@cs.wisc.eduhash_delay=1 1219674Snilay@cs.wisc.edulatency=10000 1229674Snilay@cs.wisc.edulifo=false 1239674Snilay@cs.wisc.edumax_miss_count=0 1249380SAndreas.Sandberg@ARM.commem_side_filter_ranges= 1259654SAndreas.Sandberg@ARM.commshrs=10 1269654SAndreas.Sandberg@ARM.comprefetch_access=false 1279654SAndreas.Sandberg@ARM.comprefetch_cache_check_push=true 1289654SAndreas.Sandberg@ARM.comprefetch_data_accesses_only=false 1299654SAndreas.Sandberg@ARM.comprefetch_degree=1 1309654SAndreas.Sandberg@ARM.comprefetch_latency=100000 1319654SAndreas.Sandberg@ARM.comprefetch_miss=false 1329654SAndreas.Sandberg@ARM.comprefetch_past_page=false 1339380SAndreas.Sandberg@ARM.comprefetch_policy=none 1349380SAndreas.Sandberg@ARM.comprefetch_serial_squash=false 1359380SAndreas.Sandberg@ARM.comprefetch_use_cpu_id=true 1369380SAndreas.Sandberg@ARM.comprefetcher_size=100 1379380SAndreas.Sandberg@ARM.comprioritizeRequests=false 1389380SAndreas.Sandberg@ARM.comrepl=Null 1399793Sakash.bagdia@arm.comsize=2097152 1409793Sakash.bagdia@arm.comsplit=false 1419380SAndreas.Sandberg@ARM.comsplit_size=0 1429654SAndreas.Sandberg@ARM.comsubblock_size=0 1439654SAndreas.Sandberg@ARM.comtgts_per_mshr=5 1449654SAndreas.Sandberg@ARM.comtrace_addr=0 1459654SAndreas.Sandberg@ARM.comtwo_queue=false 1469380SAndreas.Sandberg@ARM.comwrite_buffers=8 1479380SAndreas.Sandberg@ARM.comcpu_side=system.cpu.toL2Bus.port[2] 1489674Snilay@cs.wisc.edumem_side=system.membus.port[1] 1499380SAndreas.Sandberg@ARM.com 1509793Sakash.bagdia@arm.com[system.cpu.toL2Bus] 1519793Sakash.bagdia@arm.comtype=Bus 1529793Sakash.bagdia@arm.comblock_size=64 1539793Sakash.bagdia@arm.combus_id=0 1549827Sakash.bagdia@arm.comclock=1000 1559827Sakash.bagdia@arm.comheader_cycles=1 1569827Sakash.bagdia@arm.comresponder_set=false 1579827Sakash.bagdia@arm.comwidth=64 1589793Sakash.bagdia@arm.comport=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 1599793Sakash.bagdia@arm.com 1609793Sakash.bagdia@arm.com[system.cpu.tracer] 1619827Sakash.bagdia@arm.comtype=ExeTracer 1629827Sakash.bagdia@arm.com 1639827Sakash.bagdia@arm.com[system.cpu.workload] 1649793Sakash.bagdia@arm.comtype=LiveProcess 1659380SAndreas.Sandberg@ARM.comcmd=hello 1669380SAndreas.Sandberg@ARM.comcwd= 1679380SAndreas.Sandberg@ARM.comegid=100 1689380SAndreas.Sandberg@ARM.comenv= 1699380SAndreas.Sandberg@ARM.comeuid=100 1709380SAndreas.Sandberg@ARM.comexecutable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 1719380SAndreas.Sandberg@ARM.comgid=100 1729380SAndreas.Sandberg@ARM.cominput=cin 1739380SAndreas.Sandberg@ARM.commax_stack_size=67108864 1749380SAndreas.Sandberg@ARM.comoutput=cout 1759380SAndreas.Sandberg@ARM.compid=100 1769792Sandreas.hansson@arm.comppid=99 1779792Sandreas.hansson@arm.comsystem=system 1789792Sandreas.hansson@arm.comuid=100 1799792Sandreas.hansson@arm.com 1809792Sandreas.hansson@arm.com[system.membus] 1819792Sandreas.hansson@arm.comtype=Bus 1829792Sandreas.hansson@arm.comblock_size=64 1839792Sandreas.hansson@arm.combus_id=0 1849792Sandreas.hansson@arm.comclock=1000 1859792Sandreas.hansson@arm.comheader_cycles=1 1869792Sandreas.hansson@arm.comresponder_set=false 1879792Sandreas.hansson@arm.comwidth=64 1889792Sandreas.hansson@arm.comport=system.physmem.port[0] system.cpu.l2cache.mem_side 1899792Sandreas.hansson@arm.com 1909792Sandreas.hansson@arm.com[system.physmem] 1919792Sandreas.hansson@arm.comtype=PhysicalMemory 1929792Sandreas.hansson@arm.comfile= 1939792Sandreas.hansson@arm.comlatency=1 1949792Sandreas.hansson@arm.comrange=0:134217727 1959792Sandreas.hansson@arm.comzero=false 1969792Sandreas.hansson@arm.comport=system.membus.port[0] 1979792Sandreas.hansson@arm.com 1989792Sandreas.hansson@arm.com