stats.txt revision 9698
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000144 # Number of seconds simulated 4sim_ticks 143853 # Number of ticks simulated 5final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 31570 # Simulator instruction rate (inst/s) 8host_op_rate 31567 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 710572 # Simulator tick rate (ticks/s) 10host_mem_usage 153096 # Number of bytes of host memory used 11host_seconds 0.20 # Real time elapsed on the host 12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits 15system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses 16system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses 17system.cpu.dtb.fetch_hits 0 # ITB hits 18system.cpu.dtb.fetch_misses 0 # ITB misses 19system.cpu.dtb.fetch_acv 0 # ITB acv 20system.cpu.dtb.fetch_accesses 0 # ITB accesses 21system.cpu.dtb.read_hits 1183 # DTB read hits 22system.cpu.dtb.read_misses 7 # DTB read misses 23system.cpu.dtb.read_acv 0 # DTB read access violations 24system.cpu.dtb.read_accesses 1190 # DTB read accesses 25system.cpu.dtb.write_hits 865 # DTB write hits 26system.cpu.dtb.write_misses 3 # DTB write misses 27system.cpu.dtb.write_acv 0 # DTB write access violations 28system.cpu.dtb.write_accesses 868 # DTB write accesses 29system.cpu.dtb.data_hits 2048 # DTB hits 30system.cpu.dtb.data_misses 10 # DTB misses 31system.cpu.dtb.data_acv 0 # DTB access violations 32system.cpu.dtb.data_accesses 2058 # DTB accesses 33system.cpu.itb.fetch_hits 6401 # ITB hits 34system.cpu.itb.fetch_misses 17 # ITB misses 35system.cpu.itb.fetch_acv 0 # ITB acv 36system.cpu.itb.fetch_accesses 6418 # ITB accesses 37system.cpu.itb.read_hits 0 # DTB read hits 38system.cpu.itb.read_misses 0 # DTB read misses 39system.cpu.itb.read_acv 0 # DTB read access violations 40system.cpu.itb.read_accesses 0 # DTB read accesses 41system.cpu.itb.write_hits 0 # DTB write hits 42system.cpu.itb.write_misses 0 # DTB write misses 43system.cpu.itb.write_acv 0 # DTB write access violations 44system.cpu.itb.write_accesses 0 # DTB write accesses 45system.cpu.itb.data_hits 0 # DTB hits 46system.cpu.itb.data_misses 0 # DTB misses 47system.cpu.itb.data_acv 0 # DTB access violations 48system.cpu.itb.data_accesses 0 # DTB accesses 49system.cpu.workload.num_syscalls 17 # Number of system calls 50system.cpu.numCycles 143853 # number of cpu cycles simulated 51system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 52system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 53system.cpu.committedInsts 6390 # Number of instructions committed 54system.cpu.committedOps 6390 # Number of ops (including micro ops) committed 55system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 56system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 57system.cpu.num_func_calls 251 # number of times a function call or return occured 58system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 59system.cpu.num_int_insts 6317 # number of integer instructions 60system.cpu.num_fp_insts 10 # number of float instructions 61system.cpu.num_int_register_reads 8285 # number of times the integer registers were read 62system.cpu.num_int_register_writes 4568 # number of times the integer registers were written 63system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 64system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 65system.cpu.num_mem_refs 2058 # number of memory refs 66system.cpu.num_load_insts 1190 # Number of load instructions 67system.cpu.num_store_insts 868 # Number of store instructions 68system.cpu.num_idle_cycles 0 # Number of idle cycles 69system.cpu.num_busy_cycles 143853 # Number of busy cycles 70system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 71system.cpu.idle_fraction 0 # Percentage of idle cycles 72 73---------- End Simulation Statistics ---------- 74