stats.txt revision 10526
16167SN/A
26167SN/A---------- Begin Simulation Statistics ----------
310526Snilay@cs.wisc.edusim_seconds                                  0.000124                       # Number of seconds simulated
410526Snilay@cs.wisc.edusim_ticks                                      123564                       # Number of ticks simulated
510526Snilay@cs.wisc.edufinal_tick                                     123564                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68721SN/Asim_freq                                   1000000000                       # Frequency of simulated ticks
710526Snilay@cs.wisc.eduhost_inst_rate                                  34581                       # Simulator instruction rate (inst/s)
810526Snilay@cs.wisc.eduhost_op_rate                                    34578                       # Simulator op (including micro ops) rate (op/s)
910526Snilay@cs.wisc.eduhost_tick_rate                                 668563                       # Simulator tick rate (ticks/s)
1010526Snilay@cs.wisc.eduhost_mem_usage                                 436724                       # Number of bytes of host memory used
1110526Snilay@cs.wisc.eduhost_seconds                                     0.19                       # Real time elapsed on the host
129150SAli.Saidi@ARM.comsim_insts                                        6390                       # Number of instructions simulated
139150SAli.Saidi@ARM.comsim_ops                                          6390                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                             1                       # Clock period in ticks
1610526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0       110720                       # Number of bytes read from this memory
1710526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::total             110720                       # Number of bytes read from this memory
1810526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0       110464                       # Number of bytes written to this memory
1910526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::total          110464                       # Number of bytes written to this memory
2010526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0         1730                       # Number of read requests responded to by this memory
2110526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::total                1730                       # Number of read requests responded to by this memory
2210526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0         1726                       # Number of write requests responded to by this memory
2310526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::total               1726                       # Number of write requests responded to by this memory
2410526Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::ruby.dir_cntrl0    896053867                       # Total read bandwidth from this memory (bytes/s)
2510526Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::total             896053867                       # Total read bandwidth from this memory (bytes/s)
2610526Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::ruby.dir_cntrl0    893982066                       # Write bandwidth from this memory (bytes/s)
2710526Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::total            893982066                       # Write bandwidth from this memory (bytes/s)
2810526Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::ruby.dir_cntrl0   1790035933                       # Total bandwidth to/from this memory (bytes/s)
2910526Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::total           1790035933                       # Total bandwidth to/from this memory (bytes/s)
3010526Snilay@cs.wisc.edusystem.mem_ctrls.readReqs                        1730                       # Number of read requests accepted
3110526Snilay@cs.wisc.edusystem.mem_ctrls.writeReqs                       1726                       # Number of write requests accepted
3210526Snilay@cs.wisc.edusystem.mem_ctrls.readBursts                      1730                       # Number of DRAM read bursts, including those serviced by the write queue
3310526Snilay@cs.wisc.edusystem.mem_ctrls.writeBursts                     1726                       # Number of DRAM write bursts, including those merged in the write queue
3410526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadDRAM                  56704                       # Total number of bytes read from DRAM
3510526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadWrQ                   54016                       # Total number of bytes read from write queue
3610526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWritten                   57536                       # Total number of bytes written to DRAM
3710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadSys                  110720                       # Total read bytes from the system interface side
3810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWrittenSys               110464                       # Total written bytes from the system interface side
3910526Snilay@cs.wisc.edusystem.mem_ctrls.servicedByWrQ                    844                       # Number of DRAM read bursts serviced by the write queue
4010526Snilay@cs.wisc.edusystem.mem_ctrls.mergedWrBursts                   803                       # Number of DRAM write bursts merged with an existing one
4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
4210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::0                85                       # Per bank write bursts
4310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::1                44                       # Per bank write bursts
4410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2                71                       # Per bank write bursts
4510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::3                65                       # Per bank write bursts
4610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::4               112                       # Per bank write bursts
4710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::5                22                       # Per bank write bursts
4810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
4910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
5010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
5110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
5210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::10               55                       # Per bank write bursts
5310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::11               32                       # Per bank write bursts
5410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::12               20                       # Per bank write bursts
5510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::13              276                       # Per bank write bursts
5610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::14               80                       # Per bank write bursts
5710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::15               19                       # Per bank write bursts
5810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::0                84                       # Per bank write bursts
5910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::1                44                       # Per bank write bursts
6010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2                73                       # Per bank write bursts
6110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::3                62                       # Per bank write bursts
6210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::4               130                       # Per bank write bursts
6310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::5                23                       # Per bank write bursts
6410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::6                 1                       # Per bank write bursts
6510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::7                 3                       # Per bank write bursts
6610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
6710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::9                 1                       # Per bank write bursts
6810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::10               53                       # Per bank write bursts
6910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::11               32                       # Per bank write bursts
7010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::12               15                       # Per bank write bursts
7110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::13              277                       # Per bank write bursts
7210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::14               81                       # Per bank write bursts
7310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::15               20                       # Per bank write bursts
7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7610526Snilay@cs.wisc.edusystem.mem_ctrls.totGap                        123476                       # Total gap between requests
7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8310526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::6                  1730                       # Read request sizes (log2)
8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9010526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::6                 1726                       # Write request sizes (log2)
9110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::0                     886                       # What read queue length does an incoming req see
9210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::15                      7                       # What write queue length does an incoming req see
13910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::16                     12                       # What write queue length does an incoming req see
14010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::17                     52                       # What write queue length does an incoming req see
14110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::18                     57                       # What write queue length does an incoming req see
14210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::19                     59                       # What write queue length does an incoming req see
14310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::20                     57                       # What write queue length does an incoming req see
14410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::21                     57                       # What write queue length does an incoming req see
14510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::22                     56                       # What write queue length does an incoming req see
14610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::23                     56                       # What write queue length does an incoming req see
14710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::24                     55                       # What write queue length does an incoming req see
14810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::25                     55                       # What write queue length does an incoming req see
14910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::26                     55                       # What write queue length does an incoming req see
15010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::27                     55                       # What write queue length does an incoming req see
15110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::28                     55                       # What write queue length does an incoming req see
15210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::29                     55                       # What write queue length does an incoming req see
15310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::30                     55                       # What write queue length does an incoming req see
15410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::31                     55                       # What write queue length does an incoming req see
15510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::32                     55                       # What write queue length does an incoming req see
15610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
15710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
15810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
15910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
16010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
16110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
16210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
16310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
16410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
16510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
16610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
16710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
16810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
16910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
17010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::samples          258                       # Bytes accessed per row activation
18810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::mean    429.147287                       # Bytes accessed per row activation
18910526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::gmean   269.046347                       # Bytes accessed per row activation
19010526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::stdev   361.589640                       # Bytes accessed per row activation
19110526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::0-127           63     24.42%     24.42% # Bytes accessed per row activation
19210526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::128-255           51     19.77%     44.19% # Bytes accessed per row activation
19310526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::256-383           24      9.30%     53.49% # Bytes accessed per row activation
19410526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::384-511           27     10.47%     63.95% # Bytes accessed per row activation
19510526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::512-639           14      5.43%     69.38% # Bytes accessed per row activation
19610526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::640-767           11      4.26%     73.64% # Bytes accessed per row activation
19710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::768-895           12      4.65%     78.29% # Bytes accessed per row activation
19810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::896-1023           14      5.43%     83.72% # Bytes accessed per row activation
19910526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::1024-1151           42     16.28%    100.00% # Bytes accessed per row activation
20010526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::total          258                       # Bytes accessed per row activation
20110526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::samples           55                       # Reads before turning the bus around for writes
20210526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::mean      15.927273                       # Reads before turning the bus around for writes
20310526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::gmean     15.760356                       # Reads before turning the bus around for writes
20410526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::stdev      2.949291                       # Reads before turning the bus around for writes
20510526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::14-15            29     52.73%     52.73% # Reads before turning the bus around for writes
20610526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::16-17            21     38.18%     90.91% # Reads before turning the bus around for writes
20710526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::18-19             4      7.27%     98.18% # Reads before turning the bus around for writes
20810526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::36-37             1      1.82%    100.00% # Reads before turning the bus around for writes
20910526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::total            55                       # Reads before turning the bus around for writes
21010526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::samples           55                       # Writes before turning the bus around for reads
21110526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::mean      16.345455                       # Writes before turning the bus around for reads
21210526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::gmean     16.329469                       # Writes before turning the bus around for reads
21310526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::stdev      0.750757                       # Writes before turning the bus around for reads
21410526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::16               44     80.00%     80.00% # Writes before turning the bus around for reads
21510526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::17                4      7.27%     87.27% # Writes before turning the bus around for reads
21610526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::18                6     10.91%     98.18% # Writes before turning the bus around for reads
21710526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::19                1      1.82%    100.00% # Writes before turning the bus around for reads
21810526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::total            55                       # Writes before turning the bus around for reads
21910526Snilay@cs.wisc.edusystem.mem_ctrls.totQLat                        10464                       # Total ticks spent queuing
22010526Snilay@cs.wisc.edusystem.mem_ctrls.totMemAccLat                   27298                       # Total ticks spent from burst creation until serviced by the DRAM
22110526Snilay@cs.wisc.edusystem.mem_ctrls.totBusLat                       4430                       # Total ticks spent in databus transfers
22210526Snilay@cs.wisc.edusystem.mem_ctrls.avgQLat                        11.81                       # Average queueing delay per DRAM burst
22310526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
22410526Snilay@cs.wisc.edusystem.mem_ctrls.avgMemAccLat                   30.81                       # Average memory access latency per DRAM burst
22510526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBW                       458.90                       # Average DRAM read bandwidth in MiByte/s
22610526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBW                       465.64                       # Average achieved write bandwidth in MiByte/s
22710526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBWSys                    896.05                       # Average system read bandwidth in MiByte/s
22810526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBWSys                    893.98                       # Average system write bandwidth in MiByte/s
22910526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
23010526Snilay@cs.wisc.edusystem.mem_ctrls.busUtil                         7.22                       # Data bus utilization in percentage
23110526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilRead                     3.59                       # Data bus utilization in percentage for reads
23210526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilWrite                    3.64                       # Data bus utilization in percentage for writes
23310526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
23410526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrQLen                      26.06                       # Average write queue length when enqueuing
23510526Snilay@cs.wisc.edusystem.mem_ctrls.readRowHits                      665                       # Number of row buffer hits during reads
23610526Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHits                     854                       # Number of row buffer hits during writes
23710526Snilay@cs.wisc.edusystem.mem_ctrls.readRowHitRate                 75.06                       # Row buffer hit rate for reads
23810526Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHitRate                92.52                       # Row buffer hit rate for writes
23910526Snilay@cs.wisc.edusystem.mem_ctrls.avgGap                         35.73                       # Average gap between requests
24010526Snilay@cs.wisc.edusystem.mem_ctrls.pageHitRate                    83.97                       # Row buffer hit rate, read and write combined
24110526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::IDLE          11701                       # Time in different power states
24210526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::REF            3900                       # Time in different power states
24310526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
24410526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::ACT          101465                       # Time in different power states
24510526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
24610526Snilay@cs.wisc.edusystem.mem_ctrls.actEnergy::0                  771120                       # Energy for activate commands per rank (pJ)
24710526Snilay@cs.wisc.edusystem.mem_ctrls.actEnergy::1                 1081080                       # Energy for activate commands per rank (pJ)
24810526Snilay@cs.wisc.edusystem.mem_ctrls.preEnergy::0                  428400                       # Energy for precharge commands per rank (pJ)
24910526Snilay@cs.wisc.edusystem.mem_ctrls.preEnergy::1                  600600                       # Energy for precharge commands per rank (pJ)
25010526Snilay@cs.wisc.edusystem.mem_ctrls.readEnergy::0                4879680                       # Energy for read commands per rank (pJ)
25110526Snilay@cs.wisc.edusystem.mem_ctrls.readEnergy::1                5466240                       # Energy for read commands per rank (pJ)
25210526Snilay@cs.wisc.edusystem.mem_ctrls.writeEnergy::0               4281984                       # Energy for write commands per rank (pJ)
25310526Snilay@cs.wisc.edusystem.mem_ctrls.writeEnergy::1               4323456                       # Energy for write commands per rank (pJ)
25410526Snilay@cs.wisc.edusystem.mem_ctrls.refreshEnergy::0             7628400                       # Energy for refresh commands per rank (pJ)
25510526Snilay@cs.wisc.edusystem.mem_ctrls.refreshEnergy::1             7628400                       # Energy for refresh commands per rank (pJ)
25610526Snilay@cs.wisc.edusystem.mem_ctrls.actBackEnergy::0            69482088                       # Energy for active background per rank (pJ)
25710526Snilay@cs.wisc.edusystem.mem_ctrls.actBackEnergy::1            69027912                       # Energy for active background per rank (pJ)
25810526Snilay@cs.wisc.edusystem.mem_ctrls.preBackEnergy::0             9282000                       # Energy for precharge background per rank (pJ)
25910526Snilay@cs.wisc.edusystem.mem_ctrls.preBackEnergy::1             9680400                       # Energy for precharge background per rank (pJ)
26010526Snilay@cs.wisc.edusystem.mem_ctrls.totalEnergy::0              96753672                       # Total energy per rank (pJ)
26110526Snilay@cs.wisc.edusystem.mem_ctrls.totalEnergy::1              97808088                       # Total energy per rank (pJ)
26210526Snilay@cs.wisc.edusystem.mem_ctrls.averagePower::0           826.587089                       # Core power per rank (mW)
26310526Snilay@cs.wisc.edusystem.mem_ctrls.averagePower::1           835.595188                       # Core power per rank (mW)
26410036SAli.Saidi@ARM.comsystem.ruby.clk_domain.clock                        1                       # Clock period in ticks
26510013Snilay@cs.wisc.edusystem.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
26610013Snilay@cs.wisc.edusystem.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
26710013Snilay@cs.wisc.edusystem.ruby.delayHist::samples                   3456                       # delay histogram for all message
26810013Snilay@cs.wisc.edusystem.ruby.delayHist                    |        3456    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
26910013Snilay@cs.wisc.edusystem.ruby.delayHist::total                     3456                       # delay histogram for all message
27010013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::bucket_size            1                      
27110013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::max_bucket            9                      
27210013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::samples         8449                      
27310013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean              1                      
27410013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean             1                      
27510013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
27610013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::total          8449                      
27710526Snilay@cs.wisc.edusystem.ruby.latency_hist::bucket_size              64                      
27810526Snilay@cs.wisc.edusystem.ruby.latency_hist::max_bucket              639                      
27910013Snilay@cs.wisc.edusystem.ruby.latency_hist::samples                8448                      
28010526Snilay@cs.wisc.edusystem.ruby.latency_hist::mean              13.626420                      
28110526Snilay@cs.wisc.edusystem.ruby.latency_hist::gmean              5.329740                      
28210526Snilay@cs.wisc.edusystem.ruby.latency_hist::stdev             25.242996                      
28310526Snilay@cs.wisc.edusystem.ruby.latency_hist                 |        8195     97.01%     97.01% |         199      2.36%     99.36% |          43      0.51%     99.87% |           2      0.02%     99.89% |           5      0.06%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
28410013Snilay@cs.wisc.edusystem.ruby.latency_hist::total                  8448                      
28510013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::bucket_size            1                      
28610013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::max_bucket            9                      
28710013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::samples            6718                      
28810013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::mean                  3                      
28910013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::gmean          3.000000                      
29010013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        6718    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
29110013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::total              6718                      
29210526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::bucket_size           64                      
29310526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::max_bucket          639                      
29410013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::samples           1730                      
29510526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::mean         54.891329                      
29610526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::gmean        49.648144                      
29710526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::stdev        31.153546                      
29810526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist            |        1477     85.38%     85.38% |         199     11.50%     96.88% |          43      2.49%     99.36% |           2      0.12%     99.48% |           5      0.29%     99.77% |           4      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
29910013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::total             1730                      
30010013Snilay@cs.wisc.edusystem.ruby.Directory.incomplete_times           1729                      
30110036SAli.Saidi@ARM.comsystem.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
3029698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_hits         6718                       # Number of cache demand hits
3039698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_misses         1730                       # Number of cache demand misses
3049698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_accesses         8448                       # Number of cache demand accesses
30510526Snilay@cs.wisc.edusystem.cpu.clk_domain.clock                         1                       # Clock period in ticks
30610526Snilay@cs.wisc.edusystem.ruby.network.routers0.percent_links_utilized     6.992328                      
3079864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Control::2         1730                      
3089864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Data::2         1726                      
3099864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Data::4         1730                      
3109864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Control::3         1726                      
3119864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Control::2        13840                      
3129864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Data::2       124272                      
3139864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Data::4       124560                      
3149864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Control::3        13808                      
31510526Snilay@cs.wisc.edusystem.ruby.network.routers1.percent_links_utilized     6.992328                      
3169864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Control::2         1730                      
3179864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Data::2         1726                      
3189864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Data::4         1730                      
3199864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Control::3         1726                      
3209864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Control::2        13840                      
3219864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Data::2       124272                      
3229864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Data::4       124560                      
3239864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Control::3        13808                      
32410526Snilay@cs.wisc.edusystem.ruby.network.routers2.percent_links_utilized     6.992328                      
3259864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Control::2         1730                      
3269864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Data::2         1726                      
3279864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Data::4         1730                      
3289864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Control::3         1726                      
3299864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Control::2        13840                      
3309864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Data::2       124272                      
3319864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Data::4       124560                      
3329864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Control::3        13808                      
3339885Sstever@gmail.comsystem.ruby.network.msg_count.Control            5190                      
3349885Sstever@gmail.comsystem.ruby.network.msg_count.Data               5178                      
3359885Sstever@gmail.comsystem.ruby.network.msg_count.Response_Data         5190                      
3369885Sstever@gmail.comsystem.ruby.network.msg_count.Writeback_Control         5178                      
3379885Sstever@gmail.comsystem.ruby.network.msg_byte.Control            41520                      
3389885Sstever@gmail.comsystem.ruby.network.msg_byte.Data              372816                      
3399885Sstever@gmail.comsystem.ruby.network.msg_byte.Response_Data       373680                      
3409885Sstever@gmail.comsystem.ruby.network.msg_byte.Writeback_Control        41424                      
3418721SN/Asystem.cpu.dtb.fetch_hits                           0                       # ITB hits
3428721SN/Asystem.cpu.dtb.fetch_misses                         0                       # ITB misses
3438721SN/Asystem.cpu.dtb.fetch_acv                            0                       # ITB acv
3448721SN/Asystem.cpu.dtb.fetch_accesses                       0                       # ITB accesses
3459150SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits                         1183                       # DTB read hits
3468721SN/Asystem.cpu.dtb.read_misses                          7                       # DTB read misses
3478721SN/Asystem.cpu.dtb.read_acv                             0                       # DTB read access violations
3489150SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses                     1190                       # DTB read accesses
3498721SN/Asystem.cpu.dtb.write_hits                         865                       # DTB write hits
3508721SN/Asystem.cpu.dtb.write_misses                         3                       # DTB write misses
3518721SN/Asystem.cpu.dtb.write_acv                            0                       # DTB write access violations
3528721SN/Asystem.cpu.dtb.write_accesses                     868                       # DTB write accesses
3539150SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits                         2048                       # DTB hits
3546167SN/Asystem.cpu.dtb.data_misses                         10                       # DTB misses
3558721SN/Asystem.cpu.dtb.data_acv                             0                       # DTB access violations
3569150SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses                     2058                       # DTB accesses
3579150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits                        6401                       # ITB hits
3588721SN/Asystem.cpu.itb.fetch_misses                        17                       # ITB misses
3598721SN/Asystem.cpu.itb.fetch_acv                            0                       # ITB acv
3609150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses                    6418                       # ITB accesses
3618721SN/Asystem.cpu.itb.read_hits                            0                       # DTB read hits
3628721SN/Asystem.cpu.itb.read_misses                          0                       # DTB read misses
3638721SN/Asystem.cpu.itb.read_acv                             0                       # DTB read access violations
3648721SN/Asystem.cpu.itb.read_accesses                        0                       # DTB read accesses
3658721SN/Asystem.cpu.itb.write_hits                           0                       # DTB write hits
3668721SN/Asystem.cpu.itb.write_misses                         0                       # DTB write misses
3678721SN/Asystem.cpu.itb.write_acv                            0                       # DTB write access violations
3688721SN/Asystem.cpu.itb.write_accesses                       0                       # DTB write accesses
3696167SN/Asystem.cpu.itb.data_hits                            0                       # DTB hits
3706167SN/Asystem.cpu.itb.data_misses                          0                       # DTB misses
3718721SN/Asystem.cpu.itb.data_acv                             0                       # DTB access violations
3728721SN/Asystem.cpu.itb.data_accesses                        0                       # DTB accesses
3738721SN/Asystem.cpu.workload.num_syscalls                   17                       # Number of system calls
37410526Snilay@cs.wisc.edusystem.cpu.numCycles                           123564                       # number of cpu cycles simulated
3758721SN/Asystem.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
3767935SN/Asystem.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
3779150SAli.Saidi@ARM.comsystem.cpu.committedInsts                        6390                       # Number of instructions committed
3789150SAli.Saidi@ARM.comsystem.cpu.committedOps                          6390                       # Number of ops (including micro ops) committed
3799150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses                  6317                       # Number of integer alu accesses
3808721SN/Asystem.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
3818721SN/Asystem.cpu.num_func_calls                         251                       # number of times a function call or return occured
3829150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts          749                       # number of instructions that are conditional controls
3839150SAli.Saidi@ARM.comsystem.cpu.num_int_insts                         6317                       # number of integer instructions
3847935SN/Asystem.cpu.num_fp_insts                            10                       # number of float instructions
3859150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads                8285                       # number of times the integer registers were read
3869150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes               4568                       # number of times the integer registers were written
3877935SN/Asystem.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
3887935SN/Asystem.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
3899150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs                          2058                       # number of memory refs
3909150SAli.Saidi@ARM.comsystem.cpu.num_load_insts                        1190                       # Number of load instructions
3918721SN/Asystem.cpu.num_store_insts                        868                       # Number of store instructions
3927935SN/Asystem.cpu.num_idle_cycles                          0                       # Number of idle cycles
39310526Snilay@cs.wisc.edusystem.cpu.num_busy_cycles                     123564                       # Number of busy cycles
3948721SN/Asystem.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
3958721SN/Asystem.cpu.idle_fraction                            0                       # Percentage of idle cycles
39610063Snilay@cs.wisc.edusystem.cpu.Branches                              1050                       # Number of branches fetched
39710220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
39810220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu                      4320     67.50%     67.80% # Class of executed instruction
39910220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult                        1      0.02%     67.81% # Class of executed instruction
40010220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv                         0      0.00%     67.81% # Class of executed instruction
40110220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd                       2      0.03%     67.84% # Class of executed instruction
40210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp                       0      0.00%     67.84% # Class of executed instruction
40310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt                       0      0.00%     67.84% # Class of executed instruction
40410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult                      0      0.00%     67.84% # Class of executed instruction
40510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv                       0      0.00%     67.84% # Class of executed instruction
40610220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt                      0      0.00%     67.84% # Class of executed instruction
40710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd                        0      0.00%     67.84% # Class of executed instruction
40810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc                     0      0.00%     67.84% # Class of executed instruction
40910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu                        0      0.00%     67.84% # Class of executed instruction
41010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp                        0      0.00%     67.84% # Class of executed instruction
41110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt                        0      0.00%     67.84% # Class of executed instruction
41210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc                       0      0.00%     67.84% # Class of executed instruction
41310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult                       0      0.00%     67.84% # Class of executed instruction
41410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc                    0      0.00%     67.84% # Class of executed instruction
41510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift                      0      0.00%     67.84% # Class of executed instruction
41610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc                   0      0.00%     67.84% # Class of executed instruction
41710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt                       0      0.00%     67.84% # Class of executed instruction
41810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd                   0      0.00%     67.84% # Class of executed instruction
41910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu                   0      0.00%     67.84% # Class of executed instruction
42010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp                   0      0.00%     67.84% # Class of executed instruction
42110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt                   0      0.00%     67.84% # Class of executed instruction
42210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv                   0      0.00%     67.84% # Class of executed instruction
42310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc                  0      0.00%     67.84% # Class of executed instruction
42410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult                  0      0.00%     67.84% # Class of executed instruction
42510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.84% # Class of executed instruction
42610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.84% # Class of executed instruction
42710220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead                     1190     18.59%     86.44% # Class of executed instruction
42810220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite                     868     13.56%    100.00% # Class of executed instruction
42910220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
43010220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
43110220Sandreas.hansson@arm.comsystem.cpu.op_class::total                       6400                       # Class of executed instruction
43210526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.link_utilization     6.998802                      
4339864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1730                      
4349864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1726                      
4359864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4       124560                      
4369864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        13808                      
43710526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.link_utilization     6.985853                      
4389864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2         1730                      
4399864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2         1726                      
4409864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2        13840                      
4419864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2       124272                      
44210526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.link_utilization     6.985853                      
4439864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2         1730                      
4449864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2         1726                      
4459864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2        13840                      
4469864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2       124272                      
44710526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.link_utilization     6.998802                      
4489864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1730                      
4499864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1726                      
4509864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       124560                      
4519864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        13808                      
45210526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.link_utilization     6.998802                      
4539864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1730                      
4549864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1726                      
4559864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4       124560                      
4569864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        13808                      
45710526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.link_utilization     6.985853                      
4589864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2         1730                      
4599864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2         1726                      
4609864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2        13840                      
4619864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2       124272                      
46210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
46310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
46410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples          1730                       # delay histogram for vnet_1
46510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1           |        1730    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
46610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total            1730                       # delay histogram for vnet_1
46710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
46810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
46910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples          1726                       # delay histogram for vnet_2
47010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2           |        1726    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
47110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total            1726                       # delay histogram for vnet_2
47210526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::bucket_size           64                      
47310526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::max_bucket           639                      
47410013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples             1183                      
47510526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::mean           33.711750                      
47610526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::gmean          16.462445                      
47710526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::stdev          33.973523                      
47810526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist              |        1077     91.04%     91.04% |          86      7.27%     98.31% |          15      1.27%     99.58% |           2      0.17%     99.75% |           2      0.17%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
47910013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total               1183                      
48010013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size            1                      
48110013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket            9                      
48210013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples          456                      
48310013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean               3                      
48410013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean       3.000000                      
48510013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         456    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
48610013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total            456                      
48710526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::bucket_size           64                      
48810526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::max_bucket          639                      
48910013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples          727                      
49010526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::mean      52.975241                      
49110526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::gmean     47.891138                      
49210526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::stdev     30.251097                      
49310526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist         |         621     85.42%     85.42% |          86     11.83%     97.25% |          15      2.06%     99.31% |           2      0.28%     99.59% |           2      0.28%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
49410013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total           727                      
49510526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size           64                      
49610526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket           639                      
49710013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples              865                      
49810526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean           18.557225                      
49910526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean           7.162336                      
50010526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev          28.547301                      
50110526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist              |         834     96.42%     96.42% |          21      2.43%     98.84% |           9      1.04%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           1      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
50210013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total                865                      
50310013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size            1                      
50410013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket            9                      
50510013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples          592                      
50610013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean               3                      
50710013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean       3.000000                      
50810013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         592    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
50910013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total            592                      
51010526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size           64                      
51110526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket          639                      
51210013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples          273                      
51310526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean      52.293040                      
51410526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean     47.271858                      
51510526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev     30.324989                      
51610526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist         |         242     88.64%     88.64% |          21      7.69%     96.34% |           9      3.30%     99.63% |           0      0.00%     99.63% |           0      0.00%     99.63% |           1      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
51710013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total           273                      
51810526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size           64                      
51910526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket          639                      
52010013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples         6400                      
52110526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean        9.247344                      
52210526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean       4.157427                      
52310526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev      20.515003                      
52410526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist          |        6284     98.19%     98.19% |          92      1.44%     99.63% |          19      0.30%     99.92% |           0      0.00%     99.92% |           3      0.05%     99.97% |           2      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
52510013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total           6400                      
52610013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
52710013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
52810013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples         5670                      
52910013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean            3                      
53010013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
53110013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        5670    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
53210013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total         5670                      
53310526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
53410526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
53510013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples          730                      
53610526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean    57.771233                      
53710526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean    52.414605                      
53810526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev    32.138819                      
53910526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist     |         614     84.11%     84.11% |          92     12.60%     96.71% |          19      2.60%     99.32% |           0      0.00%     99.32% |           3      0.41%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
54010013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total          730                      
54110526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::bucket_size           64                      
54210526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
54310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::samples         1730                      
54410526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::mean    54.891329                      
54510526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::gmean    49.648144                      
54610526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::stdev    31.153546                      
54710526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist |        1477     85.38%     85.38% |         199     11.50%     96.88% |          43      2.49%     99.36% |           2      0.12%     99.48% |           5      0.29%     99.77% |           4      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
54810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::total         1730                      
54910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
55010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
55110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples            1                      
55210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev          nan                      
55310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
55410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::total            1                      
55510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size            1                      
55610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket            9                      
55710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::samples            1                      
55810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::stdev          nan                      
55910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
56010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::total            1                      
56110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size            1                      
56210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket            9                      
56310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::samples            1                      
56410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev          nan                      
56510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
56610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::total            1                      
56710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size            8                      
56810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket           79                      
56910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::samples            1                      
57010526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::mean           75                      
57110526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean    75.000000                      
57210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev          nan                      
57310526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
57410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::total            1                      
57510526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           64                      
57610526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          639                      
57710013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::samples          727                      
57810526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::mean    52.975241                      
57910526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    47.891138                      
58010526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    30.251097                      
58110526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist |         621     85.42%     85.42% |          86     11.83%     97.25% |          15      2.06%     99.31% |           2      0.28%     99.59% |           2      0.28%     99.86% |           1      0.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
58210013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::total          727                      
58310526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           64                      
58410526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          639                      
58510013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::samples          273                      
58610526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::mean    52.293040                      
58710526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    47.271858                      
58810526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    30.324989                      
58910526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist |         242     88.64%     88.64% |          21      7.69%     96.34% |           9      3.30%     99.63% |           0      0.00%     99.63% |           0      0.00%     99.63% |           1      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59010013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::total          273                      
59110526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           64                      
59210526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
59310013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          730                      
59410526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    57.771233                      
59510526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    52.414605                      
59610526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    32.138819                      
59710526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         614     84.11%     84.11% |          92     12.60%     96.71% |          19      2.60%     99.32% |           0      0.00%     99.32% |           3      0.41%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59810013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          730                      
59910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load              1183      0.00%      0.00%
60010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch            6400      0.00%      0.00%
60110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store              865      0.00%      0.00%
60210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data              1730      0.00%      0.00%
60310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement         1726      0.00%      0.00%
60410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack         1726      0.00%      0.00%
60510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load             727      0.00%      0.00%
60610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch           730      0.00%      0.00%
60710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store            273      0.00%      0.00%
60810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load             456      0.00%      0.00%
60910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch          5670      0.00%      0.00%
61010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store            592      0.00%      0.00%
61110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement         1726      0.00%      0.00%
61210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack         1726      0.00%      0.00%
61310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data           1457      0.00%      0.00%
61410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data            273      0.00%      0.00%
61510013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.GETX            1730      0.00%      0.00%
61610013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.PUTX            1726      0.00%      0.00%
61710013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Data         1730      0.00%      0.00%
61810013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Ack         1726      0.00%      0.00%
61910013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.GETX          1730      0.00%      0.00%
62010013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.PUTX          1726      0.00%      0.00%
62110013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.IM.Memory_Data         1730      0.00%      0.00%
62210013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.MI.Memory_Ack         1726      0.00%      0.00%
6236167SN/A
6246167SN/A---------- End Simulation Statistics   ----------
625