stats.txt revision 10063
16167SN/A 26167SN/A---------- Begin Simulation Statistics ---------- 39183Shestness@cs.wisc.edusim_seconds 0.000144 # Number of seconds simulated 49183Shestness@cs.wisc.edusim_ticks 143853 # Number of ticks simulated 59183Shestness@cs.wisc.edufinal_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000 # Frequency of simulated ticks 710063Snilay@cs.wisc.eduhost_inst_rate 33822 # Simulator instruction rate (inst/s) 810063Snilay@cs.wisc.eduhost_op_rate 33819 # Simulator op (including micro ops) rate (op/s) 910063Snilay@cs.wisc.eduhost_tick_rate 761273 # Simulator tick rate (ticks/s) 1010063Snilay@cs.wisc.eduhost_mem_usage 174328 # Number of bytes of host memory used 1110063Snilay@cs.wisc.eduhost_seconds 0.19 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6390 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6390 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1 # Clock period in ticks 1610036SAli.Saidi@ARM.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 1710013Snilay@cs.wisc.edusystem.ruby.delayHist::bucket_size 1 # delay histogram for all message 1810013Snilay@cs.wisc.edusystem.ruby.delayHist::max_bucket 9 # delay histogram for all message 1910013Snilay@cs.wisc.edusystem.ruby.delayHist::samples 3456 # delay histogram for all message 2010013Snilay@cs.wisc.edusystem.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 2110013Snilay@cs.wisc.edusystem.ruby.delayHist::total 3456 # delay histogram for all message 2210013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::bucket_size 1 2310013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::max_bucket 9 2410013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::samples 8449 2510013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean 1 2610013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean 1 2710013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 2810013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::total 8449 2910013Snilay@cs.wisc.edusystem.ruby.latency_hist::bucket_size 16 3010013Snilay@cs.wisc.edusystem.ruby.latency_hist::max_bucket 159 3110013Snilay@cs.wisc.edusystem.ruby.latency_hist::samples 8448 3210013Snilay@cs.wisc.edusystem.ruby.latency_hist::mean 16.028054 3310013Snilay@cs.wisc.edusystem.ruby.latency_hist::gmean 5.654112 3410013Snilay@cs.wisc.edusystem.ruby.latency_hist::stdev 25.911348 3510013Snilay@cs.wisc.edusystem.ruby.latency_hist | 6718 79.52% 79.52% | 0 0.00% 79.52% | 0 0.00% 79.52% | 336 3.98% 83.50% | 1251 14.81% 98.31% | 136 1.61% 99.92% | 5 0.06% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3610013Snilay@cs.wisc.edusystem.ruby.latency_hist::total 8448 3710013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::bucket_size 1 3810013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::max_bucket 9 3910013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::samples 6718 4010013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::mean 3 4110013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::gmean 3.000000 4210013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 4310013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::total 6718 4410013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::bucket_size 16 4510013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::max_bucket 159 4610013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::samples 1730 4710013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::mean 66.619075 4810013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::gmean 66.251950 4910013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::stdev 7.725779 5010013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 336 19.42% 19.42% | 1251 72.31% 91.73% | 136 7.86% 99.60% | 5 0.29% 99.88% | 2 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 5110013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::total 1730 5210013Snilay@cs.wisc.edusystem.ruby.Directory.incomplete_times 1729 5310036SAli.Saidi@ARM.comsystem.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 549698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits 559698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses 569698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses 579864Snilay@cs.wisc.edusystem.ruby.network.routers0.percent_links_utilized 6.006131 589864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Control::2 1730 599864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Data::2 1726 609864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Data::4 1730 619864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Control::3 1726 629864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Control::2 13840 639864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Data::2 124272 649864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Data::4 124560 659864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 669748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memReq 3456 # Total number of memory requests 679748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memRead 1730 # Number of memory reads 689748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memWrite 1726 # Number of memory writes 699748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memRefresh 999 # Number of memory refreshes 709748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memWaitCycles 3037 # Delay stalled at the head of the bank queue 719748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankQ 11 # Delay behind the head of the bank queue 729748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.totalStalls 3048 # Total number of stall cycles 739748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.881944 # Expected number of stall cycles per request 749748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankBusy 1500 # memory stalls due to busy bank 759748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBusBusy 1375 # memory stalls due to busy bus 769748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 55 # memory stalls due to read write turnaround 779748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memArbWait 107 # memory stalls due to arbitration 789748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankCount | 162 4.69% 4.69% | 36 1.04% 5.73% | 92 2.66% 8.39% | 110 3.18% 11.57% | 106 3.07% 14.64% | 362 10.47% 25.12% | 98 2.84% 27.95% | 36 1.04% 28.99% | 32 0.93% 29.92% | 34 0.98% 30.90% | 83 2.40% 33.30% | 92 2.66% 35.97% | 110 3.18% 39.15% | 104 3.01% 42.16% | 84 2.43% 44.59% | 86 2.49% 47.08% | 83 2.40% 49.48% | 53 1.53% 51.01% | 50 1.45% 52.46% | 58 1.68% 54.14% | 64 1.85% 55.99% | 124 3.59% 59.58% | 212 6.13% 65.71% | 72 2.08% 67.80% | 66 1.91% 69.70% | 50 1.45% 71.15% | 122 3.53% 74.68% | 190 5.50% 80.18% | 220 6.37% 86.55% | 325 9.40% 95.95% | 42 1.22% 97.16% | 98 2.84% 100.00% # Number of accesses per bank 799748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankCount::total 3456 # Number of accesses per bank 809864Snilay@cs.wisc.edusystem.ruby.network.routers1.percent_links_utilized 6.006131 819864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Control::2 1730 829864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Data::2 1726 839864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Data::4 1730 849864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Control::3 1726 859864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Control::2 13840 869864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Data::2 124272 879864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Data::4 124560 889864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 899864Snilay@cs.wisc.edusystem.ruby.network.routers2.percent_links_utilized 6.006131 909864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Control::2 1730 919864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Data::2 1726 929864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Data::4 1730 939864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Control::3 1726 949864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Control::2 13840 959864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Data::2 124272 969864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Data::4 124560 979864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 989885Sstever@gmail.comsystem.ruby.network.msg_count.Control 5190 999885Sstever@gmail.comsystem.ruby.network.msg_count.Data 5178 1009885Sstever@gmail.comsystem.ruby.network.msg_count.Response_Data 5190 1019885Sstever@gmail.comsystem.ruby.network.msg_count.Writeback_Control 5178 1029885Sstever@gmail.comsystem.ruby.network.msg_byte.Control 41520 1039885Sstever@gmail.comsystem.ruby.network.msg_byte.Data 372816 1049885Sstever@gmail.comsystem.ruby.network.msg_byte.Response_Data 373680 1059885Sstever@gmail.comsystem.ruby.network.msg_byte.Writeback_Control 41424 10610036SAli.Saidi@ARM.comsystem.cpu.clk_domain.clock 1 # Clock period in ticks 1078721SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 1088721SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 1098721SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 1108721SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 1119150SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 1183 # DTB read hits 1128721SN/Asystem.cpu.dtb.read_misses 7 # DTB read misses 1138721SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 1149150SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 1190 # DTB read accesses 1158721SN/Asystem.cpu.dtb.write_hits 865 # DTB write hits 1168721SN/Asystem.cpu.dtb.write_misses 3 # DTB write misses 1178721SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 1188721SN/Asystem.cpu.dtb.write_accesses 868 # DTB write accesses 1199150SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits 2048 # DTB hits 1206167SN/Asystem.cpu.dtb.data_misses 10 # DTB misses 1218721SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 1229150SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses 2058 # DTB accesses 1239150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits 6401 # ITB hits 1248721SN/Asystem.cpu.itb.fetch_misses 17 # ITB misses 1258721SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 1269150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses 6418 # ITB accesses 1278721SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 1288721SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 1298721SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 1308721SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 1318721SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 1328721SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 1338721SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 1348721SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 1356167SN/Asystem.cpu.itb.data_hits 0 # DTB hits 1366167SN/Asystem.cpu.itb.data_misses 0 # DTB misses 1378721SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 1388721SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 1398721SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 1409183Shestness@cs.wisc.edusystem.cpu.numCycles 143853 # number of cpu cycles simulated 1418721SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1427935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1439150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6390 # Number of instructions committed 1449150SAli.Saidi@ARM.comsystem.cpu.committedOps 6390 # Number of ops (including micro ops) committed 1459150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 1468721SN/Asystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 1478721SN/Asystem.cpu.num_func_calls 251 # number of times a function call or return occured 1489150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 1499150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 6317 # number of integer instructions 1507935SN/Asystem.cpu.num_fp_insts 10 # number of float instructions 1519150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 8285 # number of times the integer registers were read 1529150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 4568 # number of times the integer registers were written 1537935SN/Asystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 1547935SN/Asystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 1559150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 2058 # number of memory refs 1569150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 1190 # Number of load instructions 1578721SN/Asystem.cpu.num_store_insts 868 # Number of store instructions 1587935SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 1599183Shestness@cs.wisc.edusystem.cpu.num_busy_cycles 143853 # Number of busy cycles 1608721SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 1618721SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 16210063Snilay@cs.wisc.edusystem.cpu.Branches 1050 # Number of branches fetched 1639864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.link_utilization 6.011692 1649864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 1659864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 1669864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560 1679864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808 1689864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.link_utilization 6.000570 1699864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2 1730 1709864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2 1726 1719864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840 1729864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272 1739864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.link_utilization 6.000570 1749864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2 1730 1759864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2 1726 1769864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840 1779864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272 1789864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.link_utilization 6.011692 1799864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730 1809864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726 1819864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560 1829864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808 1839864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.link_utilization 6.011692 1849864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730 1859864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726 1869864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560 1879864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808 1889864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.link_utilization 6.000570 1899864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2 1730 1909864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2 1726 1919864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840 1929864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272 19310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 19410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 19510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1 19610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1 | 1730 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 19710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1 19810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 19910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 20010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2 20110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2 | 1726 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 20210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2 20310013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::bucket_size 16 20410013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::max_bucket 159 20510013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples 1183 20610013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::mean 41.560440 20710013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::gmean 19.958512 20810013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::stdev 30.922662 20910013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist | 456 38.55% 38.55% | 0 0.00% 38.55% | 0 0.00% 38.55% | 118 9.97% 48.52% | 572 48.35% 96.87% | 36 3.04% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 21010013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total 1183 21110013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size 1 21210013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket 9 21310013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples 456 21410013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean 3 21510013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean 3.000000 21610013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 21710013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total 456 21810013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::bucket_size 16 21910013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::max_bucket 159 22010013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples 727 22110013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::mean 65.746905 22210013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::gmean 65.515952 22310013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::stdev 6.090166 22410013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 118 16.23% 16.23% | 572 78.68% 94.91% | 36 4.95% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 22510013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total 727 22610013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size 16 22710013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket 159 22810013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples 865 22910013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean 23.805780 23010013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean 8.045280 23110013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev 31.148787 23210013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist | 592 68.44% 68.44% | 0 0.00% 68.44% | 0 0.00% 68.44% | 29 3.35% 71.79% | 202 23.35% 95.14% | 42 4.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 23310013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total 865 23410013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size 1 23510013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket 9 23610013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples 592 23710013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean 3 23810013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean 3.000000 23910013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 24010013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total 592 24110013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size 16 24210013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket 159 24310013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples 273 24410013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean 68.923077 24510013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean 68.323325 24610013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev 9.836417 24710013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 29 10.62% 10.62% | 202 73.99% 84.62% | 42 15.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 24810013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total 273 24910013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size 16 25010013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket 159 25110013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples 6400 25210013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean 10.257344 25310013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean 4.269833 25410013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev 20.411875 25510013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist | 5670 88.59% 88.59% | 0 0.00% 88.59% | 0 0.00% 88.59% | 189 2.95% 91.55% | 477 7.45% 99.00% | 58 0.91% 99.91% | 4 0.06% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 25610013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total 6400 25710013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size 1 25810013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket 9 25910013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples 5670 26010013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean 3 26110013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean 3.000000 26210013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 26310013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total 5670 26410013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size 16 26510013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket 159 26610013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples 730 26710013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean 66.626027 26810013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean 66.226254 26910013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev 8.110427 27010013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 189 25.89% 25.89% | 477 65.34% 91.23% | 58 7.95% 99.18% | 4 0.55% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 27110013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total 730 27210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::bucket_size 16 27310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::max_bucket 159 27410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::samples 1730 27510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::mean 66.619075 27610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::gmean 66.251950 27710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::stdev 7.725779 27810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 336 19.42% 19.42% | 1251 72.31% 91.73% | 136 7.86% 99.60% | 5 0.29% 99.88% | 2 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 27910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::total 1730 28010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 28110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 28210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 28310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 28410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 28510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 28610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 28710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 28810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 28910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 29010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 29110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 29210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 29310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 29410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 29510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 29610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 29710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 29810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 29910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 30010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 30110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61 30210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000 30310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 30410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 30610013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16 30710013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159 30810013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727 30910013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.746905 31010013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.515952 31110013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 6.090166 31210013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 118 16.23% 16.23% | 572 78.68% 94.91% | 36 4.95% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 31310013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::total 727 31410013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16 31510013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159 31610013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273 31710013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::mean 68.923077 31810013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 68.323325 31910013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 9.836417 32010013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 29 10.62% 10.62% | 202 73.99% 84.62% | 42 15.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 32110013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::total 273 32210013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16 32310013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159 32410013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730 32510013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.626027 32610013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 66.226254 32710013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 8.110427 32810013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 189 25.89% 25.89% | 477 65.34% 91.23% | 58 7.95% 99.18% | 4 0.55% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 32910013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 33010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% 33110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% 33210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store 865 0.00% 0.00% 33310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data 1730 0.00% 0.00% 33410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00% 33510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00% 33610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00% 33710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00% 33810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00% 33910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00% 34010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00% 34110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00% 34210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% 34310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% 34410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% 34510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% 34610013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.GETX 1730 0.00% 0.00% 34710013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% 34810013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% 34910013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% 35010013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% 35110013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% 35210013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% 35310013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% 3546167SN/A 3556167SN/A---------- End Simulation Statistics ---------- 356