stats.txt revision 9490:e6a09d97bdc9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16030500 # Number of ticks simulated 5final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 76258 # Simulator instruction rate (inst/s) 8host_op_rate 76239 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 191753794 # Simulator tick rate (ticks/s) 10host_mem_usage 225728 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 16system.physmem.bytes_read::total 31104 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 486 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 486 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 31104 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 47 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 50 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 31 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 44 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 20 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 45 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 15817000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 486 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 101system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 2909986 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests 169system.physmem.totBusLat 2430000 # Total cycles spent in databus access 170system.physmem.totBankLat 8305000 # Total cycles spent in bank access 171system.physmem.avgQLat 5987.63 # Average queueing delay per request 172system.physmem.avgBankLat 17088.48 # Average bank access latency per request 173system.physmem.avgBusLat 5000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 28076.10 # Average memory access latency 175system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 15.16 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.85 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 396 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap 32545.27 # Average gap between requests 188system.cpu.branchPred.lookups 2896 # Number of BP lookups 189system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted 190system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect 191system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups 192system.cpu.branchPred.BTBHits 746 # Number of BTB hits 193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 194system.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage 195system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. 196system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 197system.cpu.dtb.fetch_hits 0 # ITB hits 198system.cpu.dtb.fetch_misses 0 # ITB misses 199system.cpu.dtb.fetch_acv 0 # ITB acv 200system.cpu.dtb.fetch_accesses 0 # ITB accesses 201system.cpu.dtb.read_hits 2071 # DTB read hits 202system.cpu.dtb.read_misses 50 # DTB read misses 203system.cpu.dtb.read_acv 0 # DTB read access violations 204system.cpu.dtb.read_accesses 2121 # DTB read accesses 205system.cpu.dtb.write_hits 1069 # DTB write hits 206system.cpu.dtb.write_misses 30 # DTB write misses 207system.cpu.dtb.write_acv 0 # DTB write access violations 208system.cpu.dtb.write_accesses 1099 # DTB write accesses 209system.cpu.dtb.data_hits 3140 # DTB hits 210system.cpu.dtb.data_misses 80 # DTB misses 211system.cpu.dtb.data_acv 0 # DTB access violations 212system.cpu.dtb.data_accesses 3220 # DTB accesses 213system.cpu.itb.fetch_hits 2349 # ITB hits 214system.cpu.itb.fetch_misses 38 # ITB misses 215system.cpu.itb.fetch_acv 0 # ITB acv 216system.cpu.itb.fetch_accesses 2387 # ITB accesses 217system.cpu.itb.read_hits 0 # DTB read hits 218system.cpu.itb.read_misses 0 # DTB read misses 219system.cpu.itb.read_acv 0 # DTB read access violations 220system.cpu.itb.read_accesses 0 # DTB read accesses 221system.cpu.itb.write_hits 0 # DTB write hits 222system.cpu.itb.write_misses 0 # DTB write misses 223system.cpu.itb.write_acv 0 # DTB write access violations 224system.cpu.itb.write_accesses 0 # DTB write accesses 225system.cpu.itb.data_hits 0 # DTB hits 226system.cpu.itb.data_misses 0 # DTB misses 227system.cpu.itb.data_acv 0 # DTB access violations 228system.cpu.itb.data_accesses 0 # DTB accesses 229system.cpu.workload.num_syscalls 17 # Number of system calls 230system.cpu.numCycles 32062 # number of cpu cycles simulated 231system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 232system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 233system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss 234system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed 235system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered 236system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken 237system.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked 238system.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing 239system.cpu.fetch.BlockedCycles 1142 # Number of cycles fetch has spent blocked 240system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 241system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps 242system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched 243system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed 244system.cpu.fetch.rateDist::samples 14509 # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::mean 1.139086 # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::stdev 2.536110 # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::0 11558 79.66% 79.66% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::7 185 1.28% 91.30% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle 262system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle 263system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle 264system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked 265system.cpu.decode.RunCycles 2753 # Number of cycles decode is running 266system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking 267system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing 268system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch 269system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction 270system.cpu.decode.DecodedInsts 15363 # Number of instructions handled by decode 271system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode 272system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing 273system.cpu.rename.IdleCycles 9517 # Number of cycles rename is idle 274system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking 275system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst 276system.cpu.rename.RunCycles 2631 # Number of cycles rename is running 277system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking 278system.cpu.rename.RenamedInsts 14679 # Number of instructions processed by rename 279system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 280system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full 281system.cpu.rename.RenamedOperands 11023 # Number of destination operands rename has renamed 282system.cpu.rename.RenameLookups 18314 # Number of register rename lookups that rename has made 283system.cpu.rename.int_rename_lookups 18297 # Number of integer rename lookups 284system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 285system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 286system.cpu.rename.UndoneMaps 6453 # Number of HB maps that are undone due to squashing 287system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 288system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 289system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer 290system.cpu.memDep0.insertedLoads 2761 # Number of loads inserted to the mem dependence unit. 291system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. 292system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 293system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 294system.cpu.iq.iqInstsAdded 13018 # Number of instructions added to the IQ (excludes non-spec) 295system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 296system.cpu.iq.iqInstsIssued 10806 # Number of instructions issued 297system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued 298system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling 299system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph 300system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 301system.cpu.iq.issued_per_cycle::samples 14509 # Number of insts issued each cycle 302system.cpu.iq.issued_per_cycle::mean 0.744779 # Number of insts issued each cycle 303system.cpu.iq.issued_per_cycle::stdev 1.389331 # Number of insts issued each cycle 304system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 305system.cpu.iq.issued_per_cycle::0 10032 69.14% 69.14% # Number of insts issued each cycle 306system.cpu.iq.issued_per_cycle::1 1598 11.01% 80.16% # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.13% # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::3 759 5.23% 93.36% # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::4 472 3.25% 96.62% # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::total 14509 # Number of insts issued each cycle 318system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 319system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available 320system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available 321system.cpu.iq.fu_full::IntDiv 0 0.00% 13.56% # attempts to use FU when none available 322system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.56% # attempts to use FU when none available 323system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available 324system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.56% # attempts to use FU when none available 325system.cpu.iq.fu_full::FloatMult 0 0.00% 13.56% # attempts to use FU when none available 326system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.56% # attempts to use FU when none available 327system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.56% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.56% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.56% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.56% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.56% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.56% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.56% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdMult 0 0.00% 13.56% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.56% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdShift 0 0.00% 13.56% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.56% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.56% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.56% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.56% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.56% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.56% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.56% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.56% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.56% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.56% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.56% # attempts to use FU when none available 348system.cpu.iq.fu_full::MemRead 63 53.39% 66.95% # attempts to use FU when none available 349system.cpu.iq.fu_full::MemWrite 39 33.05% 100.00% # attempts to use FU when none available 350system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 351system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 352system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 353system.cpu.iq.FU_type_0::IntAlu 7299 67.55% 67.56% # Type of FU issued 354system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.57% # Type of FU issued 355system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.57% # Type of FU issued 356system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.59% # Type of FU issued 357system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued 358system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued 359system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued 360system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued 361system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.59% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued 382system.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued 383system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued 384system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 385system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 386system.cpu.iq.FU_type_0::total 10806 # Type of FU issued 387system.cpu.iq.rate 0.337034 # Inst issue rate 388system.cpu.iq.fu_busy_cnt 118 # FU busy when requested 389system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) 390system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads 391system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes 392system.cpu.iq.int_inst_queue_wakeup_accesses 9700 # Number of integer instruction queue wakeup accesses 393system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 394system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 395system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 396system.cpu.iq.int_alu_accesses 10911 # Number of integer alu accesses 397system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 398system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores 399system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 400system.cpu.iew.lsq.thread0.squashedLoads 1578 # Number of loads squashed 401system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 402system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations 403system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed 404system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 405system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 406system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 407system.cpu.iew.lsq.thread0.cacheBlocked 87 # Number of times an access to memory failed due to the cache being blocked 408system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 409system.cpu.iew.iewSquashCycles 1212 # Number of cycles IEW is squashing 410system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking 411system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking 412system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ 413system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch 414system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions 415system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions 416system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 417system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 418system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 419system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations 420system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly 421system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly 422system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute 423system.cpu.iew.iewExecutedInsts 10154 # Number of executed instructions 424system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed 425system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute 426system.cpu.iew.exec_swp 0 # number of swp insts executed 427system.cpu.iew.exec_nop 86 # number of nop insts executed 428system.cpu.iew.exec_refs 3233 # number of memory reference insts executed 429system.cpu.iew.exec_branches 1613 # Number of branches executed 430system.cpu.iew.exec_stores 1101 # Number of stores executed 431system.cpu.iew.exec_rate 0.316699 # Inst execution rate 432system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit 433system.cpu.iew.wb_count 9710 # cumulative count of insts written-back 434system.cpu.iew.wb_producers 5134 # num instructions producing a value 435system.cpu.iew.wb_consumers 6919 # num instructions consuming a value 436system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 437system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle 438system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back 439system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 440system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit 441system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 442system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted 443system.cpu.commit.committed_per_cycle::samples 13297 # Number of insts commited each cycle 444system.cpu.commit.committed_per_cycle::mean 0.480484 # Number of insts commited each cycle 445system.cpu.commit.committed_per_cycle::stdev 1.303494 # Number of insts commited each cycle 446system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 447system.cpu.commit.committed_per_cycle::0 10548 79.33% 79.33% # Number of insts commited each cycle 448system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::2 514 3.87% 94.07% # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::6 101 0.76% 98.61% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::total 13297 # Number of insts commited each cycle 460system.cpu.commit.committedInsts 6389 # Number of instructions committed 461system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 462system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 463system.cpu.commit.refs 2048 # Number of memory references committed 464system.cpu.commit.loads 1183 # Number of loads committed 465system.cpu.commit.membars 0 # Number of memory barriers committed 466system.cpu.commit.branches 1050 # Number of branches committed 467system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 468system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 469system.cpu.commit.function_calls 127 # Number of function calls committed. 470system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached 471system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 472system.cpu.rob.rob_reads 25928 # The number of ROB reads 473system.cpu.rob.rob_writes 27481 # The number of ROB writes 474system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself 475system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling 476system.cpu.committedInsts 6372 # Number of Instructions Simulated 477system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 478system.cpu.committedInsts_total 6372 # Number of Instructions Simulated 479system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction 480system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads 481system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle 482system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads 483system.cpu.int_regfile_reads 12888 # number of integer regfile reads 484system.cpu.int_regfile_writes 7343 # number of integer regfile writes 485system.cpu.fp_regfile_reads 8 # number of floating regfile reads 486system.cpu.fp_regfile_writes 2 # number of floating regfile writes 487system.cpu.misc_regfile_reads 1 # number of misc regfile reads 488system.cpu.misc_regfile_writes 1 # number of misc regfile writes 489system.cpu.icache.replacements 0 # number of replacements 490system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use 491system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. 492system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. 493system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. 494system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 495system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor 496system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy 497system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy 498system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits 499system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits 500system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits 501system.cpu.icache.demand_hits::total 1869 # number of demand (read+write) hits 502system.cpu.icache.overall_hits::cpu.inst 1869 # number of overall hits 503system.cpu.icache.overall_hits::total 1869 # number of overall hits 504system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses 505system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses 506system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses 507system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses 508system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses 509system.cpu.icache.overall_misses::total 480 # number of overall misses 510system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles 511system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles 512system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles 513system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles 514system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles 515system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles 516system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) 517system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) 518system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses 519system.cpu.icache.demand_accesses::total 2349 # number of demand (read+write) accesses 520system.cpu.icache.overall_accesses::cpu.inst 2349 # number of overall (read+write) accesses 521system.cpu.icache.overall_accesses::total 2349 # number of overall (read+write) accesses 522system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204342 # miss rate for ReadReq accesses 523system.cpu.icache.ReadReq_miss_rate::total 0.204342 # miss rate for ReadReq accesses 524system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 # miss rate for demand accesses 525system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses 526system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses 527system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses 528system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency 529system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency 530system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency 531system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency 532system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency 533system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency 534system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 540system.cpu.icache.fast_writes 0 # number of fast writes performed 541system.cpu.icache.cache_copies 0 # number of cache copies performed 542system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits 543system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits 544system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits 545system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits 546system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits 547system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits 548system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 549system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 550system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 551system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 552system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 553system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses 554system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16102000 # number of ReadReq MSHR miss cycles 555system.cpu.icache.ReadReq_mshr_miss_latency::total 16102000 # number of ReadReq MSHR miss cycles 556system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16102000 # number of demand (read+write) MSHR miss cycles 557system.cpu.icache.demand_mshr_miss_latency::total 16102000 # number of demand (read+write) MSHR miss cycles 558system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16102000 # number of overall MSHR miss cycles 559system.cpu.icache.overall_mshr_miss_latency::total 16102000 # number of overall MSHR miss cycles 560system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses 561system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses 562system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses 563system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses 564system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses 565system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses 566system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51444.089457 # average ReadReq mshr miss latency 567system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51444.089457 # average ReadReq mshr miss latency 568system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency 569system.cpu.icache.demand_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency 570system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency 571system.cpu.icache.overall_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency 572system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 573system.cpu.l2cache.replacements 0 # number of replacements 574system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use 575system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 576system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. 577system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. 578system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 579system.cpu.l2cache.occ_blocks::cpu.inst 159.327355 # Average occupied blocks per requestor 580system.cpu.l2cache.occ_blocks::cpu.data 60.316098 # Average occupied blocks per requestor 581system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy 582system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy 583system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy 584system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 585system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 586system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 587system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 588system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 589system.cpu.l2cache.overall_hits::total 1 # number of overall hits 590system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses 591system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 592system.cpu.l2cache.ReadReq_misses::total 413 # number of ReadReq misses 593system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 594system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 595system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 596system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 597system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses 598system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 599system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 600system.cpu.l2cache.overall_misses::total 486 # number of overall misses 601system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15777000 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadReq_miss_latency::total 21857500 # number of ReadReq miss cycles 604system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles 605system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles 606system.cpu.l2cache.demand_miss_latency::cpu.inst 15777000 # number of demand (read+write) miss cycles 607system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles 608system.cpu.l2cache.demand_miss_latency::total 25545000 # number of demand (read+write) miss cycles 609system.cpu.l2cache.overall_miss_latency::cpu.inst 15777000 # number of overall miss cycles 610system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles 611system.cpu.l2cache.overall_miss_latency::total 25545000 # number of overall miss cycles 612system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) 613system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 614system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) 615system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 616system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 617system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses 618system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 619system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses 620system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses 621system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 622system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses 623system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses 624system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 625system.cpu.l2cache.ReadReq_miss_rate::total 0.997585 # miss rate for ReadReq accesses 626system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 627system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 628system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 629system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 630system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses 631system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 632system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 633system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses 634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50567.307692 # average ReadReq miss latency 635system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency 636system.cpu.l2cache.ReadReq_avg_miss_latency::total 52923.728814 # average ReadReq miss latency 637system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency 638system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency 639system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency 640system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency 641system.cpu.l2cache.demand_avg_miss_latency::total 52561.728395 # average overall miss latency 642system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency 643system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency 644system.cpu.l2cache.overall_avg_miss_latency::total 52561.728395 # average overall miss latency 645system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 646system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 647system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 648system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 649system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 650system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 651system.cpu.l2cache.fast_writes 0 # number of fast writes performed 652system.cpu.l2cache.cache_copies 0 # number of cache copies performed 653system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses 654system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 655system.cpu.l2cache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses 656system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 658system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 659system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses 661system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 662system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 663system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses 664system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11907990 # number of ReadReq MSHR miss cycles 665system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848832 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16756822 # number of ReadReq MSHR miss cycles 667system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795812 # number of ReadExReq MSHR miss cycles 668system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795812 # number of ReadExReq MSHR miss cycles 669system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11907990 # number of demand (read+write) MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644644 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::total 19552634 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11907990 # number of overall MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644644 # number of overall MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::total 19552634 # number of overall MSHR miss cycles 675system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses 676system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 677system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses 678system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 679system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 680system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 681system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 682system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses 683system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 684system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 685system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency 689system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency 697system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 698system.cpu.dcache.replacements 0 # number of replacements 699system.cpu.dcache.tagsinuse 107.713176 # Cycle average of tags in use 700system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. 701system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 702system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. 703system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 704system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor 705system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy 706system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy 707system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits 708system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits 709system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 710system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 711system.cpu.dcache.demand_hits::cpu.data 2262 # number of demand (read+write) hits 712system.cpu.dcache.demand_hits::total 2262 # number of demand (read+write) hits 713system.cpu.dcache.overall_hits::cpu.data 2262 # number of overall hits 714system.cpu.dcache.overall_hits::total 2262 # number of overall hits 715system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses 716system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses 717system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 718system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 719system.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses 720system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses 721system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses 722system.cpu.dcache.overall_misses::total 528 # number of overall misses 723system.cpu.dcache.ReadReq_miss_latency::cpu.data 9127000 # number of ReadReq miss cycles 724system.cpu.dcache.ReadReq_miss_latency::total 9127000 # number of ReadReq miss cycles 725system.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles 726system.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles 727system.cpu.dcache.demand_miss_latency::cpu.data 25020487 # number of demand (read+write) miss cycles 728system.cpu.dcache.demand_miss_latency::total 25020487 # number of demand (read+write) miss cycles 729system.cpu.dcache.overall_miss_latency::cpu.data 25020487 # number of overall miss cycles 730system.cpu.dcache.overall_miss_latency::total 25020487 # number of overall miss cycles 731system.cpu.dcache.ReadReq_accesses::cpu.data 1925 # number of ReadReq accesses(hits+misses) 732system.cpu.dcache.ReadReq_accesses::total 1925 # number of ReadReq accesses(hits+misses) 733system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 734system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 735system.cpu.dcache.demand_accesses::cpu.data 2790 # number of demand (read+write) accesses 736system.cpu.dcache.demand_accesses::total 2790 # number of demand (read+write) accesses 737system.cpu.dcache.overall_accesses::cpu.data 2790 # number of overall (read+write) accesses 738system.cpu.dcache.overall_accesses::total 2790 # number of overall (read+write) accesses 739system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087792 # miss rate for ReadReq accesses 740system.cpu.dcache.ReadReq_miss_rate::total 0.087792 # miss rate for ReadReq accesses 741system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 742system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 743system.cpu.dcache.demand_miss_rate::cpu.data 0.189247 # miss rate for demand accesses 744system.cpu.dcache.demand_miss_rate::total 0.189247 # miss rate for demand accesses 745system.cpu.dcache.overall_miss_rate::cpu.data 0.189247 # miss rate for overall accesses 746system.cpu.dcache.overall_miss_rate::total 0.189247 # miss rate for overall accesses 747system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54005.917160 # average ReadReq miss latency 748system.cpu.dcache.ReadReq_avg_miss_latency::total 54005.917160 # average ReadReq miss latency 749system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44271.551532 # average WriteReq miss latency 750system.cpu.dcache.WriteReq_avg_miss_latency::total 44271.551532 # average WriteReq miss latency 751system.cpu.dcache.demand_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency 752system.cpu.dcache.demand_avg_miss_latency::total 47387.285985 # average overall miss latency 753system.cpu.dcache.overall_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency 754system.cpu.dcache.overall_avg_miss_latency::total 47387.285985 # average overall miss latency 755system.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked 756system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 757system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked 758system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 759system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.478261 # average number of cycles each access was blocked 760system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu.dcache.fast_writes 0 # number of fast writes performed 762system.cpu.dcache.cache_copies 0 # number of cache copies performed 763system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits 764system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 765system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 766system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits 767system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits 768system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits 769system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits 770system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits 771system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 772system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 773system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 774system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 775system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 776system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 777system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 778system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 779system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6189000 # number of ReadReq MSHR miss cycles 780system.cpu.dcache.ReadReq_mshr_miss_latency::total 6189000 # number of ReadReq MSHR miss cycles 781system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3763500 # number of WriteReq MSHR miss cycles 782system.cpu.dcache.WriteReq_mshr_miss_latency::total 3763500 # number of WriteReq MSHR miss cycles 783system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9952500 # number of demand (read+write) MSHR miss cycles 784system.cpu.dcache.demand_mshr_miss_latency::total 9952500 # number of demand (read+write) MSHR miss cycles 785system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9952500 # number of overall MSHR miss cycles 786system.cpu.dcache.overall_mshr_miss_latency::total 9952500 # number of overall MSHR miss cycles 787system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052468 # mshr miss rate for ReadReq accesses 788system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052468 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for demand accesses 792system.cpu.dcache.demand_mshr_miss_rate::total 0.062366 # mshr miss rate for demand accesses 793system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for overall accesses 794system.cpu.dcache.overall_mshr_miss_rate::total 0.062366 # mshr miss rate for overall accesses 795system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61277.227723 # average ReadReq mshr miss latency 796system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61277.227723 # average ReadReq mshr miss latency 797system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51554.794521 # average WriteReq mshr miss latency 798system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51554.794521 # average WriteReq mshr miss latency 799system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency 800system.cpu.dcache.demand_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency 801system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency 802system.cpu.dcache.overall_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency 803system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 804 805---------- End Simulation Statistics ---------- 806