stats.txt revision 9312
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 11568000 # Number of ticks simulated 5final_tick 11568000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 27765 # Simulator instruction rate (inst/s) 8host_op_rate 27764 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 50400871 # Simulator tick rate (ticks/s) 10host_mem_usage 217072 # Number of bytes of host memory used 11host_seconds 0.23 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 16system.physmem.bytes_read::total 31104 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 486 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1731673582 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 957123098 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2688796680 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1731673582 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1731673582 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1731673582 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 957123098 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2688796680 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 486 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 31104 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 19 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 11441000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 486 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 101system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 3089486 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 12593486 # Sum of mem lat for all requests 169system.physmem.totBusLat 1944000 # Total cycles spent in databus access 170system.physmem.totBankLat 7560000 # Total cycles spent in bank access 171system.physmem.avgQLat 6356.97 # Average queueing delay per request 172system.physmem.avgBankLat 15555.56 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 25912.52 # Average memory access latency 175system.physmem.avgRdBW 2688.80 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 2688.80 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 16.80 # Data bus utilization in percentage 181system.physmem.avgRdQLen 1.09 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 416 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 85.60 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap 23541.15 # Average gap between requests 188system.cpu.dtb.fetch_hits 0 # ITB hits 189system.cpu.dtb.fetch_misses 0 # ITB misses 190system.cpu.dtb.fetch_acv 0 # ITB acv 191system.cpu.dtb.fetch_accesses 0 # ITB accesses 192system.cpu.dtb.read_hits 1960 # DTB read hits 193system.cpu.dtb.read_misses 58 # DTB read misses 194system.cpu.dtb.read_acv 0 # DTB read access violations 195system.cpu.dtb.read_accesses 2018 # DTB read accesses 196system.cpu.dtb.write_hits 1076 # DTB write hits 197system.cpu.dtb.write_misses 32 # DTB write misses 198system.cpu.dtb.write_acv 0 # DTB write access violations 199system.cpu.dtb.write_accesses 1108 # DTB write accesses 200system.cpu.dtb.data_hits 3036 # DTB hits 201system.cpu.dtb.data_misses 90 # DTB misses 202system.cpu.dtb.data_acv 0 # DTB access violations 203system.cpu.dtb.data_accesses 3126 # DTB accesses 204system.cpu.itb.fetch_hits 2261 # ITB hits 205system.cpu.itb.fetch_misses 38 # ITB misses 206system.cpu.itb.fetch_acv 0 # ITB acv 207system.cpu.itb.fetch_accesses 2299 # ITB accesses 208system.cpu.itb.read_hits 0 # DTB read hits 209system.cpu.itb.read_misses 0 # DTB read misses 210system.cpu.itb.read_acv 0 # DTB read access violations 211system.cpu.itb.read_accesses 0 # DTB read accesses 212system.cpu.itb.write_hits 0 # DTB write hits 213system.cpu.itb.write_misses 0 # DTB write misses 214system.cpu.itb.write_acv 0 # DTB write access violations 215system.cpu.itb.write_accesses 0 # DTB write accesses 216system.cpu.itb.data_hits 0 # DTB hits 217system.cpu.itb.data_misses 0 # DTB misses 218system.cpu.itb.data_acv 0 # DTB access violations 219system.cpu.itb.data_accesses 0 # DTB accesses 220system.cpu.workload.num_syscalls 17 # Number of system calls 221system.cpu.numCycles 23137 # number of cpu cycles simulated 222system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 223system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 224system.cpu.BPredUnit.lookups 2774 # Number of BP lookups 225system.cpu.BPredUnit.condPredicted 1638 # Number of conditional branches predicted 226system.cpu.BPredUnit.condIncorrect 514 # Number of conditional branches incorrect 227system.cpu.BPredUnit.BTBLookups 2124 # Number of BTB lookups 228system.cpu.BPredUnit.BTBHits 769 # Number of BTB hits 229system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 230system.cpu.BPredUnit.usedRAS 405 # Number of times the RAS was used to get a target. 231system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. 232system.cpu.fetch.icacheStallCycles 7948 # Number of cycles fetch is stalled on an Icache miss 233system.cpu.fetch.Insts 15915 # Number of instructions fetch has processed 234system.cpu.fetch.Branches 2774 # Number of branches that fetch encountered 235system.cpu.fetch.predictedBranches 1174 # Number of branches that fetch has predicted taken 236system.cpu.fetch.Cycles 2854 # Number of cycles fetch has run and was not squashing or blocked 237system.cpu.fetch.SquashCycles 1765 # Number of cycles fetch has spent squashing 238system.cpu.fetch.BlockedCycles 730 # Number of cycles fetch has spent blocked 239system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 240system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps 241system.cpu.fetch.CacheLines 2261 # Number of cache lines fetched 242system.cpu.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed 243system.cpu.fetch.rateDist::samples 13513 # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::mean 1.177755 # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::stdev 2.562670 # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::0 10659 78.88% 78.88% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::1 293 2.17% 81.05% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::2 218 1.61% 82.66% # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::3 238 1.76% 84.42% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::4 276 2.04% 86.46% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::5 191 1.41% 87.88% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::6 258 1.91% 89.79% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::7 175 1.30% 91.08% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::8 1205 8.92% 100.00% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::total 13513 # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.branchRate 0.119895 # Number of branch fetches per cycle 261system.cpu.fetch.rate 0.687859 # Number of inst fetches per cycle 262system.cpu.decode.IdleCycles 8886 # Number of cycles decode is idle 263system.cpu.decode.BlockedCycles 751 # Number of cycles decode is blocked 264system.cpu.decode.RunCycles 2667 # Number of cycles decode is running 265system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking 266system.cpu.decode.SquashCycles 1129 # Number of cycles decode is squashing 267system.cpu.decode.BranchResolved 236 # Number of times decode resolved a branch 268system.cpu.decode.BranchMispred 88 # Number of times decode detected a branch misprediction 269system.cpu.decode.DecodedInsts 14776 # Number of instructions handled by decode 270system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode 271system.cpu.rename.SquashCycles 1129 # Number of cycles rename is squashing 272system.cpu.rename.IdleCycles 9097 # Number of cycles rename is idle 273system.cpu.rename.BlockCycles 177 # Number of cycles rename is blocking 274system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst 275system.cpu.rename.RunCycles 2538 # Number of cycles rename is running 276system.cpu.rename.UnblockCycles 227 # Number of cycles rename is unblocking 277system.cpu.rename.RenamedInsts 14039 # Number of instructions processed by rename 278system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 279system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full 280system.cpu.rename.RenamedOperands 10509 # Number of destination operands rename has renamed 281system.cpu.rename.RenameLookups 17564 # Number of register rename lookups that rename has made 282system.cpu.rename.int_rename_lookups 17547 # Number of integer rename lookups 283system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 284system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 285system.cpu.rename.UndoneMaps 5939 # Number of HB maps that are undone due to squashing 286system.cpu.rename.serializingInsts 34 # count of serializing insts renamed 287system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed 288system.cpu.rename.skidInsts 671 # count of insts added to the skid buffer 289system.cpu.memDep0.insertedLoads 2611 # Number of loads inserted to the mem dependence unit. 290system.cpu.memDep0.insertedStores 1355 # Number of stores inserted to the mem dependence unit. 291system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 292system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 293system.cpu.iq.iqInstsAdded 12555 # Number of instructions added to the IQ (excludes non-spec) 294system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ 295system.cpu.iq.iqInstsIssued 10392 # Number of instructions issued 296system.cpu.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued 297system.cpu.iq.iqSquashedInstsExamined 5880 # Number of squashed instructions iterated over during squash; mainly for profiling 298system.cpu.iq.iqSquashedOperandsExamined 3411 # Number of squashed operands that are examined and possibly removed from graph 299system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed 300system.cpu.iq.issued_per_cycle::samples 13513 # Number of insts issued each cycle 301system.cpu.iq.issued_per_cycle::mean 0.769037 # Number of insts issued each cycle 302system.cpu.iq.issued_per_cycle::stdev 1.410550 # Number of insts issued each cycle 303system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 304system.cpu.iq.issued_per_cycle::0 9295 68.79% 68.79% # Number of insts issued each cycle 305system.cpu.iq.issued_per_cycle::1 1391 10.29% 79.08% # Number of insts issued each cycle 306system.cpu.iq.issued_per_cycle::2 1141 8.44% 87.52% # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::3 752 5.57% 93.09% # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::4 466 3.45% 96.54% # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::5 269 1.99% 98.53% # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::6 153 1.13% 99.66% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::7 32 0.24% 99.90% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::total 13513 # Number of insts issued each cycle 317system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 318system.cpu.iq.fu_full::IntAlu 11 9.57% 9.57% # attempts to use FU when none available 319system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available 320system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available 321system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available 322system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available 323system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available 324system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available 325system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available 326system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available 347system.cpu.iq.fu_full::MemRead 65 56.52% 66.09% # attempts to use FU when none available 348system.cpu.iq.fu_full::MemWrite 39 33.91% 100.00% # attempts to use FU when none available 349system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 350system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 351system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 352system.cpu.iq.FU_type_0::IntAlu 7044 67.78% 67.80% # Type of FU issued 353system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.81% # Type of FU issued 354system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued 355system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.83% # Type of FU issued 356system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.83% # Type of FU issued 357system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.83% # Type of FU issued 358system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.83% # Type of FU issued 359system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.83% # Type of FU issued 360system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.83% # Type of FU issued 361system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.83% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.83% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.83% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.83% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.83% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.83% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.83% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.83% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.83% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.83% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.83% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.83% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.83% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.83% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.83% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.83% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.83% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.83% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.83% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.83% # Type of FU issued 381system.cpu.iq.FU_type_0::MemRead 2192 21.09% 88.92% # Type of FU issued 382system.cpu.iq.FU_type_0::MemWrite 1151 11.08% 100.00% # Type of FU issued 383system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 384system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 385system.cpu.iq.FU_type_0::total 10392 # Type of FU issued 386system.cpu.iq.rate 0.449151 # Inst issue rate 387system.cpu.iq.fu_busy_cnt 115 # FU busy when requested 388system.cpu.iq.fu_busy_rate 0.011066 # FU busy rate (busy events/executed inst) 389system.cpu.iq.int_inst_queue_reads 34450 # Number of integer instruction queue reads 390system.cpu.iq.int_inst_queue_writes 18472 # Number of integer instruction queue writes 391system.cpu.iq.int_inst_queue_wakeup_accesses 9469 # Number of integer instruction queue wakeup accesses 392system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 393system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 394system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 395system.cpu.iq.int_alu_accesses 10494 # Number of integer alu accesses 396system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 397system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores 398system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 399system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed 400system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 401system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations 402system.cpu.iew.lsq.thread0.squashedStores 490 # Number of stores squashed 403system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 404system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 405system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 406system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 407system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 408system.cpu.iew.iewSquashCycles 1129 # Number of cycles IEW is squashing 409system.cpu.iew.iewBlockCycles 30 # Number of cycles IEW is blocking 410system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking 411system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ 412system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch 413system.cpu.iew.iewDispLoadInsts 2611 # Number of dispatched load instructions 414system.cpu.iew.iewDispStoreInsts 1355 # Number of dispatched store instructions 415system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions 416system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 417system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 418system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations 419system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly 420system.cpu.iew.predictedNotTakenIncorrect 377 # Number of branches that were predicted not taken incorrectly 421system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute 422system.cpu.iew.iewExecutedInsts 9865 # Number of executed instructions 423system.cpu.iew.iewExecLoadInsts 2029 # Number of load instructions executed 424system.cpu.iew.iewExecSquashedInsts 527 # Number of squashed instructions skipped in execute 425system.cpu.iew.exec_swp 0 # number of swp insts executed 426system.cpu.iew.exec_nop 86 # number of nop insts executed 427system.cpu.iew.exec_refs 3139 # number of memory reference insts executed 428system.cpu.iew.exec_branches 1600 # Number of branches executed 429system.cpu.iew.exec_stores 1110 # Number of stores executed 430system.cpu.iew.exec_rate 0.426373 # Inst execution rate 431system.cpu.iew.wb_sent 9638 # cumulative count of insts sent to commit 432system.cpu.iew.wb_count 9479 # cumulative count of insts written-back 433system.cpu.iew.wb_producers 5022 # num instructions producing a value 434system.cpu.iew.wb_consumers 6814 # num instructions consuming a value 435system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 436system.cpu.iew.wb_rate 0.409690 # insts written-back per cycle 437system.cpu.iew.wb_fanout 0.737012 # average fanout of values written-back 438system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 439system.cpu.commit.commitSquashedInsts 6282 # The number of squashed insts skipped by commit 440system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 441system.cpu.commit.branchMispredicts 432 # The number of times a branch was mispredicted 442system.cpu.commit.committed_per_cycle::samples 12384 # Number of insts commited each cycle 443system.cpu.commit.committed_per_cycle::mean 0.515908 # Number of insts commited each cycle 444system.cpu.commit.committed_per_cycle::stdev 1.366435 # Number of insts commited each cycle 445system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 446system.cpu.commit.committed_per_cycle::0 9732 78.59% 78.59% # Number of insts commited each cycle 447system.cpu.commit.committed_per_cycle::1 1344 10.85% 89.44% # Number of insts commited each cycle 448system.cpu.commit.committed_per_cycle::2 509 4.11% 93.55% # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::3 223 1.80% 95.35% # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::4 188 1.52% 96.87% # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::5 75 0.61% 97.47% # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::6 105 0.85% 98.32% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::7 63 0.51% 98.83% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::8 145 1.17% 100.00% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::total 12384 # Number of insts commited each cycle 459system.cpu.commit.committedInsts 6389 # Number of instructions committed 460system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 461system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 462system.cpu.commit.refs 2048 # Number of memory references committed 463system.cpu.commit.loads 1183 # Number of loads committed 464system.cpu.commit.membars 0 # Number of memory barriers committed 465system.cpu.commit.branches 1050 # Number of branches committed 466system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 467system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 468system.cpu.commit.function_calls 127 # Number of function calls committed. 469system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached 470system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 471system.cpu.rob.rob_reads 24559 # The number of ROB reads 472system.cpu.rob.rob_writes 26483 # The number of ROB writes 473system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself 474system.cpu.idleCycles 9624 # Total number of cycles that the CPU has spent unscheduled due to idling 475system.cpu.committedInsts 6372 # Number of Instructions Simulated 476system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 477system.cpu.committedInsts_total 6372 # Number of Instructions Simulated 478system.cpu.cpi 3.631042 # CPI: Cycles Per Instruction 479system.cpu.cpi_total 3.631042 # CPI: Total CPI of All Threads 480system.cpu.ipc 0.275403 # IPC: Instructions Per Cycle 481system.cpu.ipc_total 0.275403 # IPC: Total IPC of All Threads 482system.cpu.int_regfile_reads 12554 # number of integer regfile reads 483system.cpu.int_regfile_writes 7112 # number of integer regfile writes 484system.cpu.fp_regfile_reads 8 # number of floating regfile reads 485system.cpu.fp_regfile_writes 2 # number of floating regfile writes 486system.cpu.misc_regfile_reads 1 # number of misc regfile reads 487system.cpu.misc_regfile_writes 1 # number of misc regfile writes 488system.cpu.icache.replacements 0 # number of replacements 489system.cpu.icache.tagsinuse 160.502909 # Cycle average of tags in use 490system.cpu.icache.total_refs 1827 # Total number of references to valid blocks. 491system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. 492system.cpu.icache.avg_refs 5.818471 # Average number of references to valid blocks. 493system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 494system.cpu.icache.occ_blocks::cpu.inst 160.502909 # Average occupied blocks per requestor 495system.cpu.icache.occ_percent::cpu.inst 0.078371 # Average percentage of cache occupancy 496system.cpu.icache.occ_percent::total 0.078371 # Average percentage of cache occupancy 497system.cpu.icache.ReadReq_hits::cpu.inst 1827 # number of ReadReq hits 498system.cpu.icache.ReadReq_hits::total 1827 # number of ReadReq hits 499system.cpu.icache.demand_hits::cpu.inst 1827 # number of demand (read+write) hits 500system.cpu.icache.demand_hits::total 1827 # number of demand (read+write) hits 501system.cpu.icache.overall_hits::cpu.inst 1827 # number of overall hits 502system.cpu.icache.overall_hits::total 1827 # number of overall hits 503system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses 504system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses 505system.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses 506system.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses 507system.cpu.icache.overall_misses::cpu.inst 434 # number of overall misses 508system.cpu.icache.overall_misses::total 434 # number of overall misses 509system.cpu.icache.ReadReq_miss_latency::cpu.inst 13420000 # number of ReadReq miss cycles 510system.cpu.icache.ReadReq_miss_latency::total 13420000 # number of ReadReq miss cycles 511system.cpu.icache.demand_miss_latency::cpu.inst 13420000 # number of demand (read+write) miss cycles 512system.cpu.icache.demand_miss_latency::total 13420000 # number of demand (read+write) miss cycles 513system.cpu.icache.overall_miss_latency::cpu.inst 13420000 # number of overall miss cycles 514system.cpu.icache.overall_miss_latency::total 13420000 # number of overall miss cycles 515system.cpu.icache.ReadReq_accesses::cpu.inst 2261 # number of ReadReq accesses(hits+misses) 516system.cpu.icache.ReadReq_accesses::total 2261 # number of ReadReq accesses(hits+misses) 517system.cpu.icache.demand_accesses::cpu.inst 2261 # number of demand (read+write) accesses 518system.cpu.icache.demand_accesses::total 2261 # number of demand (read+write) accesses 519system.cpu.icache.overall_accesses::cpu.inst 2261 # number of overall (read+write) accesses 520system.cpu.icache.overall_accesses::total 2261 # number of overall (read+write) accesses 521system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191950 # miss rate for ReadReq accesses 522system.cpu.icache.ReadReq_miss_rate::total 0.191950 # miss rate for ReadReq accesses 523system.cpu.icache.demand_miss_rate::cpu.inst 0.191950 # miss rate for demand accesses 524system.cpu.icache.demand_miss_rate::total 0.191950 # miss rate for demand accesses 525system.cpu.icache.overall_miss_rate::cpu.inst 0.191950 # miss rate for overall accesses 526system.cpu.icache.overall_miss_rate::total 0.191950 # miss rate for overall accesses 527system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30921.658986 # average ReadReq miss latency 528system.cpu.icache.ReadReq_avg_miss_latency::total 30921.658986 # average ReadReq miss latency 529system.cpu.icache.demand_avg_miss_latency::cpu.inst 30921.658986 # average overall miss latency 530system.cpu.icache.demand_avg_miss_latency::total 30921.658986 # average overall miss latency 531system.cpu.icache.overall_avg_miss_latency::cpu.inst 30921.658986 # average overall miss latency 532system.cpu.icache.overall_avg_miss_latency::total 30921.658986 # average overall miss latency 533system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 534system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 535system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 536system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 537system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 538system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 539system.cpu.icache.fast_writes 0 # number of fast writes performed 540system.cpu.icache.cache_copies 0 # number of cache copies performed 541system.cpu.icache.ReadReq_mshr_hits::cpu.inst 120 # number of ReadReq MSHR hits 542system.cpu.icache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits 543system.cpu.icache.demand_mshr_hits::cpu.inst 120 # number of demand (read+write) MSHR hits 544system.cpu.icache.demand_mshr_hits::total 120 # number of demand (read+write) MSHR hits 545system.cpu.icache.overall_mshr_hits::cpu.inst 120 # number of overall MSHR hits 546system.cpu.icache.overall_mshr_hits::total 120 # number of overall MSHR hits 547system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 548system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses 549system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 550system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses 551system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 552system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses 553system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10333000 # number of ReadReq MSHR miss cycles 554system.cpu.icache.ReadReq_mshr_miss_latency::total 10333000 # number of ReadReq MSHR miss cycles 555system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10333000 # number of demand (read+write) MSHR miss cycles 556system.cpu.icache.demand_mshr_miss_latency::total 10333000 # number of demand (read+write) MSHR miss cycles 557system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10333000 # number of overall MSHR miss cycles 558system.cpu.icache.overall_mshr_miss_latency::total 10333000 # number of overall MSHR miss cycles 559system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for ReadReq accesses 560system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138877 # mshr miss rate for ReadReq accesses 561system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for demand accesses 562system.cpu.icache.demand_mshr_miss_rate::total 0.138877 # mshr miss rate for demand accesses 563system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for overall accesses 564system.cpu.icache.overall_mshr_miss_rate::total 0.138877 # mshr miss rate for overall accesses 565system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32907.643312 # average ReadReq mshr miss latency 566system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32907.643312 # average ReadReq mshr miss latency 567system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency 568system.cpu.icache.demand_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency 569system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency 570system.cpu.icache.overall_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency 571system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 572system.cpu.dcache.replacements 0 # number of replacements 573system.cpu.dcache.tagsinuse 107.685258 # Cycle average of tags in use 574system.cpu.dcache.total_refs 2236 # Total number of references to valid blocks. 575system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. 576system.cpu.dcache.avg_refs 12.924855 # Average number of references to valid blocks. 577system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 578system.cpu.dcache.occ_blocks::cpu.data 107.685258 # Average occupied blocks per requestor 579system.cpu.dcache.occ_percent::cpu.data 0.026290 # Average percentage of cache occupancy 580system.cpu.dcache.occ_percent::total 0.026290 # Average percentage of cache occupancy 581system.cpu.dcache.ReadReq_hits::cpu.data 1732 # number of ReadReq hits 582system.cpu.dcache.ReadReq_hits::total 1732 # number of ReadReq hits 583system.cpu.dcache.WriteReq_hits::cpu.data 504 # number of WriteReq hits 584system.cpu.dcache.WriteReq_hits::total 504 # number of WriteReq hits 585system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits 586system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits 587system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits 588system.cpu.dcache.overall_hits::total 2236 # number of overall hits 589system.cpu.dcache.ReadReq_misses::cpu.data 158 # number of ReadReq misses 590system.cpu.dcache.ReadReq_misses::total 158 # number of ReadReq misses 591system.cpu.dcache.WriteReq_misses::cpu.data 361 # number of WriteReq misses 592system.cpu.dcache.WriteReq_misses::total 361 # number of WriteReq misses 593system.cpu.dcache.demand_misses::cpu.data 519 # number of demand (read+write) misses 594system.cpu.dcache.demand_misses::total 519 # number of demand (read+write) misses 595system.cpu.dcache.overall_misses::cpu.data 519 # number of overall misses 596system.cpu.dcache.overall_misses::total 519 # number of overall misses 597system.cpu.dcache.ReadReq_miss_latency::cpu.data 6015000 # number of ReadReq miss cycles 598system.cpu.dcache.ReadReq_miss_latency::total 6015000 # number of ReadReq miss cycles 599system.cpu.dcache.WriteReq_miss_latency::cpu.data 9645000 # number of WriteReq miss cycles 600system.cpu.dcache.WriteReq_miss_latency::total 9645000 # number of WriteReq miss cycles 601system.cpu.dcache.demand_miss_latency::cpu.data 15660000 # number of demand (read+write) miss cycles 602system.cpu.dcache.demand_miss_latency::total 15660000 # number of demand (read+write) miss cycles 603system.cpu.dcache.overall_miss_latency::cpu.data 15660000 # number of overall miss cycles 604system.cpu.dcache.overall_miss_latency::total 15660000 # number of overall miss cycles 605system.cpu.dcache.ReadReq_accesses::cpu.data 1890 # number of ReadReq accesses(hits+misses) 606system.cpu.dcache.ReadReq_accesses::total 1890 # number of ReadReq accesses(hits+misses) 607system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 608system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 609system.cpu.dcache.demand_accesses::cpu.data 2755 # number of demand (read+write) accesses 610system.cpu.dcache.demand_accesses::total 2755 # number of demand (read+write) accesses 611system.cpu.dcache.overall_accesses::cpu.data 2755 # number of overall (read+write) accesses 612system.cpu.dcache.overall_accesses::total 2755 # number of overall (read+write) accesses 613system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083598 # miss rate for ReadReq accesses 614system.cpu.dcache.ReadReq_miss_rate::total 0.083598 # miss rate for ReadReq accesses 615system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417341 # miss rate for WriteReq accesses 616system.cpu.dcache.WriteReq_miss_rate::total 0.417341 # miss rate for WriteReq accesses 617system.cpu.dcache.demand_miss_rate::cpu.data 0.188385 # miss rate for demand accesses 618system.cpu.dcache.demand_miss_rate::total 0.188385 # miss rate for demand accesses 619system.cpu.dcache.overall_miss_rate::cpu.data 0.188385 # miss rate for overall accesses 620system.cpu.dcache.overall_miss_rate::total 0.188385 # miss rate for overall accesses 621system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38069.620253 # average ReadReq miss latency 622system.cpu.dcache.ReadReq_avg_miss_latency::total 38069.620253 # average ReadReq miss latency 623system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26717.451524 # average WriteReq miss latency 624system.cpu.dcache.WriteReq_avg_miss_latency::total 26717.451524 # average WriteReq miss latency 625system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency 626system.cpu.dcache.demand_avg_miss_latency::total 30173.410405 # average overall miss latency 627system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency 628system.cpu.dcache.overall_avg_miss_latency::total 30173.410405 # average overall miss latency 629system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 630system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 631system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 632system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 633system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 634system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 635system.cpu.dcache.fast_writes 0 # number of fast writes performed 636system.cpu.dcache.cache_copies 0 # number of cache copies performed 637system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 638system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 639system.cpu.dcache.WriteReq_mshr_hits::cpu.data 289 # number of WriteReq MSHR hits 640system.cpu.dcache.WriteReq_mshr_hits::total 289 # number of WriteReq MSHR hits 641system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits 642system.cpu.dcache.demand_mshr_hits::total 346 # number of demand (read+write) MSHR hits 643system.cpu.dcache.overall_mshr_hits::cpu.data 346 # number of overall MSHR hits 644system.cpu.dcache.overall_mshr_hits::total 346 # number of overall MSHR hits 645system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 646system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 647system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 649system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 650system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 651system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 652system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses 653system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4270000 # number of ReadReq MSHR miss cycles 654system.cpu.dcache.ReadReq_mshr_miss_latency::total 4270000 # number of ReadReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285000 # number of WriteReq MSHR miss cycles 656system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285000 # number of WriteReq MSHR miss cycles 657system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6555000 # number of demand (read+write) MSHR miss cycles 658system.cpu.dcache.demand_mshr_miss_latency::total 6555000 # number of demand (read+write) MSHR miss cycles 659system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6555000 # number of overall MSHR miss cycles 660system.cpu.dcache.overall_mshr_miss_latency::total 6555000 # number of overall MSHR miss cycles 661system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053439 # mshr miss rate for ReadReq accesses 662system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053439 # mshr miss rate for ReadReq accesses 663system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 664system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 665system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062795 # mshr miss rate for demand accesses 666system.cpu.dcache.demand_mshr_miss_rate::total 0.062795 # mshr miss rate for demand accesses 667system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062795 # mshr miss rate for overall accesses 668system.cpu.dcache.overall_mshr_miss_rate::total 0.062795 # mshr miss rate for overall accesses 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42277.227723 # average ReadReq mshr miss latency 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42277.227723 # average ReadReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31736.111111 # average WriteReq mshr miss latency 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31736.111111 # average WriteReq mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37890.173410 # average overall mshr miss latency 674system.cpu.dcache.demand_avg_mshr_miss_latency::total 37890.173410 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37890.173410 # average overall mshr miss latency 676system.cpu.dcache.overall_avg_mshr_miss_latency::total 37890.173410 # average overall mshr miss latency 677system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 678system.cpu.l2cache.replacements 0 # number of replacements 679system.cpu.l2cache.tagsinuse 220.821936 # Cycle average of tags in use 680system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 681system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. 682system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. 683system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 684system.cpu.l2cache.occ_blocks::cpu.inst 160.499801 # Average occupied blocks per requestor 685system.cpu.l2cache.occ_blocks::cpu.data 60.322135 # Average occupied blocks per requestor 686system.cpu.l2cache.occ_percent::cpu.inst 0.004898 # Average percentage of cache occupancy 687system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy 688system.cpu.l2cache.occ_percent::total 0.006739 # Average percentage of cache occupancy 689system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 690system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 691system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 692system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 693system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 694system.cpu.l2cache.overall_hits::total 1 # number of overall hits 695system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses 696system.cpu.l2cache.ReadReq_misses::cpu.data 100 # number of ReadReq misses 697system.cpu.l2cache.ReadReq_misses::total 413 # number of ReadReq misses 698system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 699system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 700system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses 701system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 702system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses 703system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses 704system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 705system.cpu.l2cache.overall_misses::total 486 # number of overall misses 706system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10016000 # number of ReadReq miss cycles 707system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4131000 # number of ReadReq miss cycles 708system.cpu.l2cache.ReadReq_miss_latency::total 14147000 # number of ReadReq miss cycles 709system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2238500 # number of ReadExReq miss cycles 710system.cpu.l2cache.ReadExReq_miss_latency::total 2238500 # number of ReadExReq miss cycles 711system.cpu.l2cache.demand_miss_latency::cpu.inst 10016000 # number of demand (read+write) miss cycles 712system.cpu.l2cache.demand_miss_latency::cpu.data 6369500 # number of demand (read+write) miss cycles 713system.cpu.l2cache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles 714system.cpu.l2cache.overall_miss_latency::cpu.inst 10016000 # number of overall miss cycles 715system.cpu.l2cache.overall_miss_latency::cpu.data 6369500 # number of overall miss cycles 716system.cpu.l2cache.overall_miss_latency::total 16385500 # number of overall miss cycles 717system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) 718system.cpu.l2cache.ReadReq_accesses::cpu.data 100 # number of ReadReq accesses(hits+misses) 719system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) 720system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 721system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 722system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses 723system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses 724system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses 725system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses 726system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses 727system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses 728system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses 729system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 730system.cpu.l2cache.ReadReq_miss_rate::total 0.997585 # miss rate for ReadReq accesses 731system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 732system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 733system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses 734system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 735system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses 736system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses 737system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 738system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses 739system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32000 # average ReadReq miss latency 740system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41310 # average ReadReq miss latency 741system.cpu.l2cache.ReadReq_avg_miss_latency::total 34254.237288 # average ReadReq miss latency 742system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 30664.383562 # average ReadExReq miss latency 743system.cpu.l2cache.ReadExReq_avg_miss_latency::total 30664.383562 # average ReadExReq miss latency 744system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32000 # average overall miss latency 745system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36817.919075 # average overall miss latency 746system.cpu.l2cache.demand_avg_miss_latency::total 33715.020576 # average overall miss latency 747system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32000 # average overall miss latency 748system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36817.919075 # average overall miss latency 749system.cpu.l2cache.overall_avg_miss_latency::total 33715.020576 # average overall miss latency 750system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu.l2cache.fast_writes 0 # number of fast writes performed 757system.cpu.l2cache.cache_copies 0 # number of cache copies performed 758system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 759system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 100 # number of ReadReq MSHR misses 760system.cpu.l2cache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses 761system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 762system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 763system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 764system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 765system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses 766system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 767system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 768system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses 769system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8904460 # number of ReadReq MSHR miss cycles 770system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3801580 # number of ReadReq MSHR miss cycles 771system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12706040 # number of ReadReq MSHR miss cycles 772system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2007032 # number of ReadExReq MSHR miss cycles 773system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2007032 # number of ReadExReq MSHR miss cycles 774system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8904460 # number of demand (read+write) MSHR miss cycles 775system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5808612 # number of demand (read+write) MSHR miss cycles 776system.cpu.l2cache.demand_mshr_miss_latency::total 14713072 # number of demand (read+write) MSHR miss cycles 777system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8904460 # number of overall MSHR miss cycles 778system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5808612 # number of overall MSHR miss cycles 779system.cpu.l2cache.overall_mshr_miss_latency::total 14713072 # number of overall MSHR miss cycles 780system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses 781system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 782system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses 783system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 784system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 785system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses 786system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 787system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses 788system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses 789system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 790system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses 791system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28448.753994 # average ReadReq mshr miss latency 792system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38015.800000 # average ReadReq mshr miss latency 793system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30765.230024 # average ReadReq mshr miss latency 794system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27493.589041 # average ReadExReq mshr miss latency 795system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27493.589041 # average ReadExReq mshr miss latency 796system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency 797system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency 798system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency 799system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency 800system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency 801system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency 802system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 803 804---------- End Simulation Statistics ---------- 805