stats.txt revision 8517
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12003500 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 47992 # Simulator instruction rate (inst/s) 7host_tick_rate 90187460 # Simulator tick rate (ticks/s) 8host_mem_usage 243780 # Number of bytes of host memory used 9host_seconds 0.13 # Real time elapsed on the host 10sim_insts 6386 # Number of instructions simulated 11system.cpu.dtb.fetch_hits 0 # ITB hits 12system.cpu.dtb.fetch_misses 0 # ITB misses 13system.cpu.dtb.fetch_acv 0 # ITB acv 14system.cpu.dtb.fetch_accesses 0 # ITB accesses 15system.cpu.dtb.read_hits 1860 # DTB read hits 16system.cpu.dtb.read_misses 45 # DTB read misses 17system.cpu.dtb.read_acv 0 # DTB read access violations 18system.cpu.dtb.read_accesses 1905 # DTB read accesses 19system.cpu.dtb.write_hits 1043 # DTB write hits 20system.cpu.dtb.write_misses 28 # DTB write misses 21system.cpu.dtb.write_acv 0 # DTB write access violations 22system.cpu.dtb.write_accesses 1071 # DTB write accesses 23system.cpu.dtb.data_hits 2903 # DTB hits 24system.cpu.dtb.data_misses 73 # DTB misses 25system.cpu.dtb.data_acv 0 # DTB access violations 26system.cpu.dtb.data_accesses 2976 # DTB accesses 27system.cpu.itb.fetch_hits 2041 # ITB hits 28system.cpu.itb.fetch_misses 29 # ITB misses 29system.cpu.itb.fetch_acv 0 # ITB acv 30system.cpu.itb.fetch_accesses 2070 # ITB accesses 31system.cpu.itb.read_hits 0 # DTB read hits 32system.cpu.itb.read_misses 0 # DTB read misses 33system.cpu.itb.read_acv 0 # DTB read access violations 34system.cpu.itb.read_accesses 0 # DTB read accesses 35system.cpu.itb.write_hits 0 # DTB write hits 36system.cpu.itb.write_misses 0 # DTB write misses 37system.cpu.itb.write_acv 0 # DTB write access violations 38system.cpu.itb.write_accesses 0 # DTB write accesses 39system.cpu.itb.data_hits 0 # DTB hits 40system.cpu.itb.data_misses 0 # DTB misses 41system.cpu.itb.data_acv 0 # DTB access violations 42system.cpu.itb.data_accesses 0 # DTB accesses 43system.cpu.workload.num_syscalls 17 # Number of system calls 44system.cpu.numCycles 24008 # number of cpu cycles simulated 45system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 46system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 47system.cpu.BPredUnit.lookups 2505 # Number of BP lookups 48system.cpu.BPredUnit.condPredicted 1456 # Number of conditional branches predicted 49system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect 50system.cpu.BPredUnit.BTBLookups 1935 # Number of BTB lookups 51system.cpu.BPredUnit.BTBHits 719 # Number of BTB hits 52system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 53system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. 54system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. 55system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss 56system.cpu.fetch.Insts 14447 # Number of instructions fetch has processed 57system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered 58system.cpu.fetch.predictedBranches 1092 # Number of branches that fetch has predicted taken 59system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked 60system.cpu.fetch.SquashCycles 1555 # Number of cycles fetch has spent squashing 61system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked 62system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 63system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps 64system.cpu.fetch.CacheLines 2041 # Number of cache lines fetched 65system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed 66system.cpu.fetch.rateDist::samples 12591 # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::mean 1.147407 # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::stdev 2.529389 # Number of instructions fetched each cycle (Total) 69system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.rateDist::0 9972 79.20% 79.20% # Number of instructions fetched each cycle (Total) 71system.cpu.fetch.rateDist::1 273 2.17% 81.37% # Number of instructions fetched each cycle (Total) 72system.cpu.fetch.rateDist::2 226 1.79% 83.16% # Number of instructions fetched each cycle (Total) 73system.cpu.fetch.rateDist::3 222 1.76% 84.93% # Number of instructions fetched each cycle (Total) 74system.cpu.fetch.rateDist::4 235 1.87% 86.79% # Number of instructions fetched each cycle (Total) 75system.cpu.fetch.rateDist::5 177 1.41% 88.20% # Number of instructions fetched each cycle (Total) 76system.cpu.fetch.rateDist::6 258 2.05% 90.25% # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.rateDist::7 141 1.12% 91.37% # Number of instructions fetched each cycle (Total) 78system.cpu.fetch.rateDist::8 1087 8.63% 100.00% # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.rateDist::total 12591 # Number of instructions fetched each cycle (Total) 83system.cpu.fetch.branchRate 0.104340 # Number of branch fetches per cycle 84system.cpu.fetch.rate 0.601758 # Number of inst fetches per cycle 85system.cpu.decode.IdleCycles 7971 # Number of cycles decode is idle 86system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked 87system.cpu.decode.RunCycles 2448 # Number of cycles decode is running 88system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 89system.cpu.decode.SquashCycles 977 # Number of cycles decode is squashing 90system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch 91system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction 92system.cpu.decode.DecodedInsts 13375 # Number of instructions handled by decode 93system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode 94system.cpu.rename.SquashCycles 977 # Number of cycles rename is squashing 95system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle 96system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking 97system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst 98system.cpu.rename.RunCycles 2318 # Number of cycles rename is running 99system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking 100system.cpu.rename.RenamedInsts 12830 # Number of instructions processed by rename 101system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full 102system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full 103system.cpu.rename.RenamedOperands 9571 # Number of destination operands rename has renamed 104system.cpu.rename.RenameLookups 16046 # Number of register rename lookups that rename has made 105system.cpu.rename.int_rename_lookups 16029 # Number of integer rename lookups 106system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 107system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed 108system.cpu.rename.UndoneMaps 4988 # Number of HB maps that are undone due to squashing 109system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 110system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 111system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer 112system.cpu.memDep0.insertedLoads 2392 # Number of loads inserted to the mem dependence unit. 113system.cpu.memDep0.insertedStores 1263 # Number of stores inserted to the mem dependence unit. 114system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 115system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 116system.cpu.iq.iqInstsAdded 11550 # Number of instructions added to the IQ (excludes non-spec) 117system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ 118system.cpu.iq.iqInstsIssued 9758 # Number of instructions issued 119system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued 120system.cpu.iq.iqSquashedInstsExamined 4875 # Number of squashed instructions iterated over during squash; mainly for profiling 121system.cpu.iq.iqSquashedOperandsExamined 2832 # Number of squashed operands that are examined and possibly removed from graph 122system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed 123system.cpu.iq.issued_per_cycle::samples 12591 # Number of insts issued each cycle 124system.cpu.iq.issued_per_cycle::mean 0.774998 # Number of insts issued each cycle 125system.cpu.iq.issued_per_cycle::stdev 1.396796 # Number of insts issued each cycle 126system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 127system.cpu.iq.issued_per_cycle::0 8508 67.57% 67.57% # Number of insts issued each cycle 128system.cpu.iq.issued_per_cycle::1 1466 11.64% 79.22% # Number of insts issued each cycle 129system.cpu.iq.issued_per_cycle::2 1070 8.50% 87.71% # Number of insts issued each cycle 130system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle 131system.cpu.iq.issued_per_cycle::4 438 3.48% 96.63% # Number of insts issued each cycle 132system.cpu.iq.issued_per_cycle::5 253 2.01% 98.64% # Number of insts issued each cycle 133system.cpu.iq.issued_per_cycle::6 129 1.02% 99.67% # Number of insts issued each cycle 134system.cpu.iq.issued_per_cycle::7 30 0.24% 99.90% # Number of insts issued each cycle 135system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle 136system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 137system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 138system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 139system.cpu.iq.issued_per_cycle::total 12591 # Number of insts issued each cycle 140system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 141system.cpu.iq.fu_full::IntAlu 13 12.38% 12.38% # attempts to use FU when none available 142system.cpu.iq.fu_full::IntMult 0 0.00% 12.38% # attempts to use FU when none available 143system.cpu.iq.fu_full::IntDiv 0 0.00% 12.38% # attempts to use FU when none available 144system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.38% # attempts to use FU when none available 145system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.38% # attempts to use FU when none available 146system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.38% # attempts to use FU when none available 147system.cpu.iq.fu_full::FloatMult 0 0.00% 12.38% # attempts to use FU when none available 148system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.38% # attempts to use FU when none available 149system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.38% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.38% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.38% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.38% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.38% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.38% # attempts to use FU when none available 155system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.38% # attempts to use FU when none available 156system.cpu.iq.fu_full::SimdMult 0 0.00% 12.38% # attempts to use FU when none available 157system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.38% # attempts to use FU when none available 158system.cpu.iq.fu_full::SimdShift 0 0.00% 12.38% # attempts to use FU when none available 159system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.38% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.38% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.38% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.38% # attempts to use FU when none available 163system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.38% # attempts to use FU when none available 164system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.38% # attempts to use FU when none available 165system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.38% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.38% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.38% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.38% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.38% # attempts to use FU when none available 170system.cpu.iq.fu_full::MemRead 54 51.43% 63.81% # attempts to use FU when none available 171system.cpu.iq.fu_full::MemWrite 38 36.19% 100.00% # attempts to use FU when none available 172system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 173system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 174system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 175system.cpu.iq.FU_type_0::IntAlu 6577 67.40% 67.42% # Type of FU issued 176system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.43% # Type of FU issued 177system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.43% # Type of FU issued 178system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.45% # Type of FU issued 179system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.45% # Type of FU issued 180system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.45% # Type of FU issued 181system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.45% # Type of FU issued 182system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.45% # Type of FU issued 183system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.45% # Type of FU issued 184system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.45% # Type of FU issued 185system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.45% # Type of FU issued 186system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.45% # Type of FU issued 187system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.45% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.45% # Type of FU issued 189system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.45% # Type of FU issued 190system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.45% # Type of FU issued 191system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.45% # Type of FU issued 192system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.45% # Type of FU issued 193system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.45% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.45% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.45% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.45% # Type of FU issued 197system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.45% # Type of FU issued 198system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.45% # Type of FU issued 199system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.45% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.45% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.45% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.45% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.45% # Type of FU issued 204system.cpu.iq.FU_type_0::MemRead 2074 21.25% 88.71% # Type of FU issued 205system.cpu.iq.FU_type_0::MemWrite 1102 11.29% 100.00% # Type of FU issued 206system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 207system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 208system.cpu.iq.FU_type_0::total 9758 # Type of FU issued 209system.cpu.iq.rate 0.406448 # Inst issue rate 210system.cpu.iq.fu_busy_cnt 105 # FU busy when requested 211system.cpu.iq.fu_busy_rate 0.010760 # FU busy rate (busy events/executed inst) 212system.cpu.iq.int_inst_queue_reads 32236 # Number of integer instruction queue reads 213system.cpu.iq.int_inst_queue_writes 16459 # Number of integer instruction queue writes 214system.cpu.iq.int_inst_queue_wakeup_accesses 8983 # Number of integer instruction queue wakeup accesses 215system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 216system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 217system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 218system.cpu.iq.int_alu_accesses 9850 # Number of integer alu accesses 219system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 220system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 221system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 222system.cpu.iew.lsq.thread0.squashedLoads 1207 # Number of loads squashed 223system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 224system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 225system.cpu.iew.lsq.thread0.squashedStores 398 # Number of stores squashed 226system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 227system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 228system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 229system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 230system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 231system.cpu.iew.iewSquashCycles 977 # Number of cycles IEW is squashing 232system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking 233system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking 234system.cpu.iew.iewDispatchedInsts 11657 # Number of instructions dispatched to IQ 235system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch 236system.cpu.iew.iewDispLoadInsts 2392 # Number of dispatched load instructions 237system.cpu.iew.iewDispStoreInsts 1263 # Number of dispatched store instructions 238system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 239system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall 240system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 241system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 242system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly 243system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly 244system.cpu.iew.branchMispredicts 446 # Number of branch mispredicts detected at execute 245system.cpu.iew.iewExecutedInsts 9316 # Number of executed instructions 246system.cpu.iew.iewExecLoadInsts 1915 # Number of load instructions executed 247system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute 248system.cpu.iew.exec_swp 0 # number of swp insts executed 249system.cpu.iew.exec_nop 80 # number of nop insts executed 250system.cpu.iew.exec_refs 2988 # number of memory reference insts executed 251system.cpu.iew.exec_branches 1504 # Number of branches executed 252system.cpu.iew.exec_stores 1073 # Number of stores executed 253system.cpu.iew.exec_rate 0.388037 # Inst execution rate 254system.cpu.iew.wb_sent 9122 # cumulative count of insts sent to commit 255system.cpu.iew.wb_count 8993 # cumulative count of insts written-back 256system.cpu.iew.wb_producers 4720 # num instructions producing a value 257system.cpu.iew.wb_consumers 6405 # num instructions consuming a value 258system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 259system.cpu.iew.wb_rate 0.374583 # insts written-back per cycle 260system.cpu.iew.wb_fanout 0.736924 # average fanout of values written-back 261system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 262system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions 263system.cpu.commit.commitSquashedInsts 5251 # The number of squashed insts skipped by commit 264system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 265system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted 266system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle 267system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle 268system.cpu.commit.committed_per_cycle::stdev 1.413328 # Number of insts commited each cycle 269system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 270system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle 271system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle 272system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle 273system.cpu.commit.committed_per_cycle::3 241 2.08% 95.15% # Number of insts commited each cycle 274system.cpu.commit.committed_per_cycle::4 158 1.36% 96.51% # Number of insts commited each cycle 275system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle 276system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle 277system.cpu.commit.committed_per_cycle::7 45 0.39% 98.60% # Number of insts commited each cycle 278system.cpu.commit.committed_per_cycle::8 163 1.40% 100.00% # Number of insts commited each cycle 279system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 280system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 281system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 282system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle 283system.cpu.commit.count 6403 # Number of instructions committed 284system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 285system.cpu.commit.refs 2050 # Number of memory references committed 286system.cpu.commit.loads 1185 # Number of loads committed 287system.cpu.commit.membars 0 # Number of memory barriers committed 288system.cpu.commit.branches 1051 # Number of branches committed 289system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 290system.cpu.commit.int_insts 6321 # Number of committed integer instructions. 291system.cpu.commit.function_calls 127 # Number of function calls committed. 292system.cpu.commit.bw_lim_events 163 # number cycles where commit BW limit reached 293system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 294system.cpu.rob.rob_reads 22754 # The number of ROB reads 295system.cpu.rob.rob_writes 24296 # The number of ROB writes 296system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself 297system.cpu.idleCycles 11417 # Total number of cycles that the CPU has spent unscheduled due to idling 298system.cpu.committedInsts 6386 # Number of Instructions Simulated 299system.cpu.committedInsts_total 6386 # Number of Instructions Simulated 300system.cpu.cpi 3.759474 # CPI: Cycles Per Instruction 301system.cpu.cpi_total 3.759474 # CPI: Total CPI of All Threads 302system.cpu.ipc 0.265995 # IPC: Instructions Per Cycle 303system.cpu.ipc_total 0.265995 # IPC: Total IPC of All Threads 304system.cpu.int_regfile_reads 11838 # number of integer regfile reads 305system.cpu.int_regfile_writes 6732 # number of integer regfile writes 306system.cpu.fp_regfile_reads 8 # number of floating regfile reads 307system.cpu.fp_regfile_writes 2 # number of floating regfile writes 308system.cpu.misc_regfile_reads 1 # number of misc regfile reads 309system.cpu.misc_regfile_writes 1 # number of misc regfile writes 310system.cpu.icache.replacements 0 # number of replacements 311system.cpu.icache.tagsinuse 159.648657 # Cycle average of tags in use 312system.cpu.icache.total_refs 1609 # Total number of references to valid blocks. 313system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. 314system.cpu.icache.avg_refs 5.173633 # Average number of references to valid blocks. 315system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 316system.cpu.icache.occ_blocks::0 159.648657 # Average occupied blocks per context 317system.cpu.icache.occ_percent::0 0.077953 # Average percentage of cache occupancy 318system.cpu.icache.ReadReq_hits 1609 # number of ReadReq hits 319system.cpu.icache.demand_hits 1609 # number of demand (read+write) hits 320system.cpu.icache.overall_hits 1609 # number of overall hits 321system.cpu.icache.ReadReq_misses 432 # number of ReadReq misses 322system.cpu.icache.demand_misses 432 # number of demand (read+write) misses 323system.cpu.icache.overall_misses 432 # number of overall misses 324system.cpu.icache.ReadReq_miss_latency 15393500 # number of ReadReq miss cycles 325system.cpu.icache.demand_miss_latency 15393500 # number of demand (read+write) miss cycles 326system.cpu.icache.overall_miss_latency 15393500 # number of overall miss cycles 327system.cpu.icache.ReadReq_accesses 2041 # number of ReadReq accesses(hits+misses) 328system.cpu.icache.demand_accesses 2041 # number of demand (read+write) accesses 329system.cpu.icache.overall_accesses 2041 # number of overall (read+write) accesses 330system.cpu.icache.ReadReq_miss_rate 0.211661 # miss rate for ReadReq accesses 331system.cpu.icache.demand_miss_rate 0.211661 # miss rate for demand accesses 332system.cpu.icache.overall_miss_rate 0.211661 # miss rate for overall accesses 333system.cpu.icache.ReadReq_avg_miss_latency 35633.101852 # average ReadReq miss latency 334system.cpu.icache.demand_avg_miss_latency 35633.101852 # average overall miss latency 335system.cpu.icache.overall_avg_miss_latency 35633.101852 # average overall miss latency 336system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 337system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 338system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 339system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 340system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 341system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 342system.cpu.icache.fast_writes 0 # number of fast writes performed 343system.cpu.icache.cache_copies 0 # number of cache copies performed 344system.cpu.icache.writebacks 0 # number of writebacks 345system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits 346system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits 347system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits 348system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses 349system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses 350system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses 351system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 352system.cpu.icache.ReadReq_mshr_miss_latency 10986500 # number of ReadReq MSHR miss cycles 353system.cpu.icache.demand_mshr_miss_latency 10986500 # number of demand (read+write) MSHR miss cycles 354system.cpu.icache.overall_mshr_miss_latency 10986500 # number of overall MSHR miss cycles 355system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 356system.cpu.icache.ReadReq_mshr_miss_rate 0.152376 # mshr miss rate for ReadReq accesses 357system.cpu.icache.demand_mshr_miss_rate 0.152376 # mshr miss rate for demand accesses 358system.cpu.icache.overall_mshr_miss_rate 0.152376 # mshr miss rate for overall accesses 359system.cpu.icache.ReadReq_avg_mshr_miss_latency 35326.366559 # average ReadReq mshr miss latency 360system.cpu.icache.demand_avg_mshr_miss_latency 35326.366559 # average overall mshr miss latency 361system.cpu.icache.overall_avg_mshr_miss_latency 35326.366559 # average overall mshr miss latency 362system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 363system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 364system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 365system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 366system.cpu.dcache.replacements 0 # number of replacements 367system.cpu.dcache.tagsinuse 109.288630 # Cycle average of tags in use 368system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. 369system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 370system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. 371system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 372system.cpu.dcache.occ_blocks::0 109.288630 # Average occupied blocks per context 373system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy 374system.cpu.dcache.ReadReq_hits 1645 # number of ReadReq hits 375system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits 376system.cpu.dcache.demand_hits 2154 # number of demand (read+write) hits 377system.cpu.dcache.overall_hits 2154 # number of overall hits 378system.cpu.dcache.ReadReq_misses 154 # number of ReadReq misses 379system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses 380system.cpu.dcache.demand_misses 510 # number of demand (read+write) misses 381system.cpu.dcache.overall_misses 510 # number of overall misses 382system.cpu.dcache.ReadReq_miss_latency 5497000 # number of ReadReq miss cycles 383system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles 384system.cpu.dcache.demand_miss_latency 17964500 # number of demand (read+write) miss cycles 385system.cpu.dcache.overall_miss_latency 17964500 # number of overall miss cycles 386system.cpu.dcache.ReadReq_accesses 1799 # number of ReadReq accesses(hits+misses) 387system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) 388system.cpu.dcache.demand_accesses 2664 # number of demand (read+write) accesses 389system.cpu.dcache.overall_accesses 2664 # number of overall (read+write) accesses 390system.cpu.dcache.ReadReq_miss_rate 0.085603 # miss rate for ReadReq accesses 391system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses 392system.cpu.dcache.demand_miss_rate 0.191441 # miss rate for demand accesses 393system.cpu.dcache.overall_miss_rate 0.191441 # miss rate for overall accesses 394system.cpu.dcache.ReadReq_avg_miss_latency 35694.805195 # average ReadReq miss latency 395system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency 396system.cpu.dcache.demand_avg_miss_latency 35224.509804 # average overall miss latency 397system.cpu.dcache.overall_avg_miss_latency 35224.509804 # average overall miss latency 398system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 399system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 400system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 401system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 402system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 403system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 404system.cpu.dcache.fast_writes 0 # number of fast writes performed 405system.cpu.dcache.cache_copies 0 # number of cache copies performed 406system.cpu.dcache.writebacks 0 # number of writebacks 407system.cpu.dcache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits 408system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits 409system.cpu.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits 410system.cpu.dcache.overall_mshr_hits 336 # number of overall MSHR hits 411system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses 412system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses 413system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses 414system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses 415system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 416system.cpu.dcache.ReadReq_mshr_miss_latency 3654000 # number of ReadReq MSHR miss cycles 417system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles 418system.cpu.dcache.demand_mshr_miss_latency 6265500 # number of demand (read+write) MSHR miss cycles 419system.cpu.dcache.overall_mshr_miss_latency 6265500 # number of overall MSHR miss cycles 420system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 421system.cpu.dcache.ReadReq_mshr_miss_rate 0.056142 # mshr miss rate for ReadReq accesses 422system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses 423system.cpu.dcache.demand_mshr_miss_rate 0.065315 # mshr miss rate for demand accesses 424system.cpu.dcache.overall_mshr_miss_rate 0.065315 # mshr miss rate for overall accesses 425system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822 # average ReadReq mshr miss latency 426system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency 427system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency 428system.cpu.dcache.overall_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency 429system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 430system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 431system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 432system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 433system.cpu.l2cache.replacements 0 # number of replacements 434system.cpu.l2cache.tagsinuse 221.178797 # Cycle average of tags in use 435system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 436system.cpu.l2cache.sampled_refs 411 # Sample count of references to valid blocks. 437system.cpu.l2cache.avg_refs 0.002433 # Average number of references to valid blocks. 438system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 439system.cpu.l2cache.occ_blocks::0 221.178797 # Average occupied blocks per context 440system.cpu.l2cache.occ_percent::0 0.006750 # Average percentage of cache occupancy 441system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits 442system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits 443system.cpu.l2cache.overall_hits 1 # number of overall hits 444system.cpu.l2cache.ReadReq_misses 411 # number of ReadReq misses 445system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses 446system.cpu.l2cache.demand_misses 484 # number of demand (read+write) misses 447system.cpu.l2cache.overall_misses 484 # number of overall misses 448system.cpu.l2cache.ReadReq_miss_latency 14129000 # number of ReadReq miss cycles 449system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles 450system.cpu.l2cache.demand_miss_latency 16642500 # number of demand (read+write) miss cycles 451system.cpu.l2cache.overall_miss_latency 16642500 # number of overall miss cycles 452system.cpu.l2cache.ReadReq_accesses 412 # number of ReadReq accesses(hits+misses) 453system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) 454system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses 455system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses 456system.cpu.l2cache.ReadReq_miss_rate 0.997573 # miss rate for ReadReq accesses 457system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 458system.cpu.l2cache.demand_miss_rate 0.997938 # miss rate for demand accesses 459system.cpu.l2cache.overall_miss_rate 0.997938 # miss rate for overall accesses 460system.cpu.l2cache.ReadReq_avg_miss_latency 34377.128954 # average ReadReq miss latency 461system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency 462system.cpu.l2cache.demand_avg_miss_latency 34385.330579 # average overall miss latency 463system.cpu.l2cache.overall_avg_miss_latency 34385.330579 # average overall miss latency 464system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 465system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 466system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 467system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 468system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 469system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 470system.cpu.l2cache.fast_writes 0 # number of fast writes performed 471system.cpu.l2cache.cache_copies 0 # number of cache copies performed 472system.cpu.l2cache.writebacks 0 # number of writebacks 473system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 474system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 475system.cpu.l2cache.ReadReq_mshr_misses 411 # number of ReadReq MSHR misses 476system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses 477system.cpu.l2cache.demand_mshr_misses 484 # number of demand (read+write) MSHR misses 478system.cpu.l2cache.overall_mshr_misses 484 # number of overall MSHR misses 479system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 480system.cpu.l2cache.ReadReq_mshr_miss_latency 12819000 # number of ReadReq MSHR miss cycles 481system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles 482system.cpu.l2cache.demand_mshr_miss_latency 15105000 # number of demand (read+write) MSHR miss cycles 483system.cpu.l2cache.overall_mshr_miss_latency 15105000 # number of overall MSHR miss cycles 484system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 485system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997573 # mshr miss rate for ReadReq accesses 486system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 487system.cpu.l2cache.demand_mshr_miss_rate 0.997938 # mshr miss rate for demand accesses 488system.cpu.l2cache.overall_mshr_miss_rate 0.997938 # mshr miss rate for overall accesses 489system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.781022 # average ReadReq mshr miss latency 490system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency 491system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency 492system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency 493system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 494system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 495system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 496system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 497 498---------- End Simulation Statistics ---------- 499