stats.txt revision 8241
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 150919 # Simulator instruction rate (inst/s) 4host_mem_usage 203704 # Number of bytes of host memory used 5host_seconds 0.04 # Real time elapsed on the host 6host_tick_rate 290889761 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 6386 # Number of instructions simulated 9sim_seconds 0.000012 # Number of seconds simulated 10sim_ticks 12357500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 2180 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. 19system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted 20system.cpu.commit.branches 1051 # Number of branches committed 21system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached 22system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 23system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions 24system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 25system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit 26system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle 27system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle 28system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle 29system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 30system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle 31system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle 32system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle 33system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle 34system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle 35system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle 36system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle 37system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle 38system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle 39system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 40system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 41system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 42system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle 43system.cpu.commit.count 6403 # Number of instructions committed 44system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 45system.cpu.commit.function_calls 127 # Number of function calls committed. 46system.cpu.commit.int_insts 6321 # Number of committed integer instructions. 47system.cpu.commit.loads 1185 # Number of loads committed 48system.cpu.commit.membars 0 # Number of memory barriers committed 49system.cpu.commit.refs 2050 # Number of memory references committed 50system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 51system.cpu.committedInsts 6386 # Number of Instructions Simulated 52system.cpu.committedInsts_total 6386 # Number of Instructions Simulated 53system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction 54system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads 55system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses) 56system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency 57system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency 58system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits 59system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles 60system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses 61system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses 62system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits 63system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles 64system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses 65system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses 66system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) 67system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency 68system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency 69system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits 70system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles 71system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses 72system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses 73system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits 74system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles 75system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses 76system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses 77system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 78system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 79system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks. 80system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 81system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 82system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 83system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 84system.cpu.dcache.cache_copies 0 # number of cache copies performed 85system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses 86system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency 87system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency 88system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits 89system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles 90system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses 91system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses 92system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits 93system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles 94system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses 95system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses 96system.cpu.dcache.fast_writes 0 # number of fast writes performed 97system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 98system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 99system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context 100system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy 101system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses 102system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency 103system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency 104system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 105system.cpu.dcache.overall_hits 2064 # number of overall hits 106system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles 107system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses 108system.cpu.dcache.overall_misses 506 # number of overall misses 109system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits 110system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles 111system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses 112system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses 113system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 114system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 115system.cpu.dcache.replacements 0 # number of replacements 116system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 117system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 118system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use 119system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks. 120system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 121system.cpu.dcache.writebacks 0 # number of writebacks 122system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked 123system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction 124system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch 125system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode 126system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle 127system.cpu.decode.RunCycles 2228 # Number of cycles decode is running 128system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing 129system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode 130system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking 131system.cpu.dtb.data_accesses 2822 # DTB accesses 132system.cpu.dtb.data_acv 0 # DTB access violations 133system.cpu.dtb.data_hits 2761 # DTB hits 134system.cpu.dtb.data_misses 61 # DTB misses 135system.cpu.dtb.fetch_accesses 0 # ITB accesses 136system.cpu.dtb.fetch_acv 0 # ITB acv 137system.cpu.dtb.fetch_hits 0 # ITB hits 138system.cpu.dtb.fetch_misses 0 # ITB misses 139system.cpu.dtb.read_accesses 1786 # DTB read accesses 140system.cpu.dtb.read_acv 0 # DTB read access violations 141system.cpu.dtb.read_hits 1750 # DTB read hits 142system.cpu.dtb.read_misses 36 # DTB read misses 143system.cpu.dtb.write_accesses 1036 # DTB write accesses 144system.cpu.dtb.write_acv 0 # DTB write access violations 145system.cpu.dtb.write_hits 1011 # DTB write hits 146system.cpu.dtb.write_misses 25 # DTB write misses 147system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered 148system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched 149system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked 150system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed 151system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed 152system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 153system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing 154system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle 155system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss 156system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken 157system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle 158system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) 159system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total) 160system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total) 161system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 162system.cpu.fetch.rateDist::0 10590 82.00% 82.00% # Number of instructions fetched each cycle (Total) 163system.cpu.fetch.rateDist::1 233 1.80% 83.80% # Number of instructions fetched each cycle (Total) 164system.cpu.fetch.rateDist::2 211 1.63% 85.44% # Number of instructions fetched each cycle (Total) 165system.cpu.fetch.rateDist::3 179 1.39% 86.82% # Number of instructions fetched each cycle (Total) 166system.cpu.fetch.rateDist::4 229 1.77% 88.59% # Number of instructions fetched each cycle (Total) 167system.cpu.fetch.rateDist::5 156 1.21% 89.80% # Number of instructions fetched each cycle (Total) 168system.cpu.fetch.rateDist::6 218 1.69% 91.49% # Number of instructions fetched each cycle (Total) 169system.cpu.fetch.rateDist::7 125 0.97% 92.46% # Number of instructions fetched each cycle (Total) 170system.cpu.fetch.rateDist::8 974 7.54% 100.00% # Number of instructions fetched each cycle (Total) 171system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 172system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 173system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 174system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) 175system.cpu.fp_regfile_reads 8 # number of floating regfile reads 176system.cpu.fp_regfile_writes 2 # number of floating regfile writes 177system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) 178system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency 179system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency 180system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits 181system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles 182system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses 183system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses 184system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits 185system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles 186system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses 187system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses 188system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 189system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 190system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks. 191system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 192system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 193system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 194system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 195system.cpu.icache.cache_copies 0 # number of cache copies performed 196system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses 197system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency 198system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency 199system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits 200system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles 201system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses 202system.cpu.icache.demand_misses 410 # number of demand (read+write) misses 203system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits 204system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles 205system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses 206system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses 207system.cpu.icache.fast_writes 0 # number of fast writes performed 208system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 209system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 210system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context 211system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy 212system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses 213system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency 214system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency 215system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 216system.cpu.icache.overall_hits 1301 # number of overall hits 217system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles 218system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses 219system.cpu.icache.overall_misses 410 # number of overall misses 220system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits 221system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles 222system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses 223system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses 224system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 225system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 226system.cpu.icache.replacements 0 # number of replacements 227system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. 228system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 229system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use 230system.cpu.icache.total_refs 1301 # Total number of references to valid blocks. 231system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 232system.cpu.icache.writebacks 0 # number of writebacks 233system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling 234system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute 235system.cpu.iew.exec_branches 1424 # Number of branches executed 236system.cpu.iew.exec_nop 82 # number of nop insts executed 237system.cpu.iew.exec_rate 0.357542 # Inst execution rate 238system.cpu.iew.exec_refs 2832 # number of memory reference insts executed 239system.cpu.iew.exec_stores 1038 # Number of stores executed 240system.cpu.iew.exec_swp 0 # number of swp insts executed 241system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking 242system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions 243system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions 244system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch 245system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions 246system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ 247system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed 248system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute 249system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions 250system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 251system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 252system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 253system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing 254system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking 255system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 256system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 257system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores 258system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed 259system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 260system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 261system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations 262system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled 263system.cpu.iew.lsq.thread.0.squashedLoads 959 # Number of loads squashed 264system.cpu.iew.lsq.thread.0.squashedStores 330 # Number of stores squashed 265system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations 266system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly 267system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly 268system.cpu.iew.wb_consumers 5952 # num instructions consuming a value 269system.cpu.iew.wb_count 8559 # cumulative count of insts written-back 270system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back 271system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 272system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 273system.cpu.iew.wb_producers 4429 # num instructions producing a value 274system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle 275system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit 276system.cpu.int_regfile_reads 11291 # number of integer regfile reads 277system.cpu.int_regfile_writes 6385 # number of integer regfile writes 278system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle 279system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads 280system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 281system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued 282system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued 283system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued 284system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued 285system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued 286system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued 287system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued 288system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued 289system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued 290system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued 291system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued 292system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued 293system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued 294system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued 295system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued 296system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued 297system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued 298system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued 299system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued 300system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued 301system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued 302system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued 303system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued 304system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued 305system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued 306system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued 307system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued 308system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued 309system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued 310system.cpu.iq.FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued 311system.cpu.iq.FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued 312system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 313system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 314system.cpu.iq.FU_type_0::total 9108 # Type of FU issued 315system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 316system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 317system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 318system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 319system.cpu.iq.fu_busy_cnt 88 # FU busy when requested 320system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) 321system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 322system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available 323system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available 324system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available 325system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available 326system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available 327system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available 328system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available 329system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available 351system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available 352system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available 353system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 354system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 355system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses 356system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads 357system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses 358system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes 359system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec) 360system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued 361system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ 362system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling 363system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued 364system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed 365system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph 366system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle 383system.cpu.iq.rate 0.368506 # Inst issue rate 384system.cpu.itb.data_accesses 0 # DTB accesses 385system.cpu.itb.data_acv 0 # DTB access violations 386system.cpu.itb.data_hits 0 # DTB hits 387system.cpu.itb.data_misses 0 # DTB misses 388system.cpu.itb.fetch_accesses 1744 # ITB accesses 389system.cpu.itb.fetch_acv 0 # ITB acv 390system.cpu.itb.fetch_hits 1711 # ITB hits 391system.cpu.itb.fetch_misses 33 # ITB misses 392system.cpu.itb.read_accesses 0 # DTB read accesses 393system.cpu.itb.read_acv 0 # DTB read access violations 394system.cpu.itb.read_hits 0 # DTB read hits 395system.cpu.itb.read_misses 0 # DTB read misses 396system.cpu.itb.write_accesses 0 # DTB write accesses 397system.cpu.itb.write_acv 0 # DTB write access violations 398system.cpu.itb.write_hits 0 # DTB write hits 399system.cpu.itb.write_misses 0 # DTB write misses 400system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) 401system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency 402system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency 403system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles 404system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 405system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses 406system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles 407system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 408system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses 409system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) 410system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency 411system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency 412system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits 413system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles 414system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses 415system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses 416system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles 417system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses 418system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses 419system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 420system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 421system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks. 422system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu.l2cache.cache_copies 0 # number of cache copies performed 427system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses 428system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency 429system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency 430system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits 431system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles 432system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses 433system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses 434system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 435system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles 436system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses 437system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses 438system.cpu.l2cache.fast_writes 0 # number of fast writes performed 439system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 440system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 441system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context 442system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy 443system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses 444system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency 445system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency 446system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 447system.cpu.l2cache.overall_hits 1 # number of overall hits 448system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles 449system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses 450system.cpu.l2cache.overall_misses 480 # number of overall misses 451system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 452system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles 453system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses 454system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses 455system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 456system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 457system.cpu.l2cache.replacements 0 # number of replacements 458system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. 459system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 460system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use 461system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 462system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 463system.cpu.l2cache.writebacks 0 # number of writebacks 464system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. 465system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 466system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. 467system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit. 468system.cpu.misc_regfile_reads 1 # number of misc regfile reads 469system.cpu.misc_regfile_writes 1 # number of misc regfile writes 470system.cpu.numCycles 24716 # number of cpu cycles simulated 471system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 472system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 473system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking 474system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed 475system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full 476system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle 477system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full 478system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made 479system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename 480system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed 481system.cpu.rename.RunCycles 2118 # Number of cycles rename is running 482system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing 483system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking 484system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing 485system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 486system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups 487system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst 488system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 489system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer 490system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 491system.cpu.rob.rob_reads 22264 # The number of ROB reads 492system.cpu.rob.rob_writes 22135 # The number of ROB writes 493system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself 494system.cpu.workload.num_syscalls 17 # Number of system calls 495 496---------- End Simulation Statistics ---------- 497