stats.txt revision 3096
1 2---------- Begin Simulation Statistics ---------- 3global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 4global.BPredUnit.BTBHits 542 # Number of BTB hits 5global.BPredUnit.BTBLookups 1938 # Number of BTB lookups 6global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. 7global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect 8global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted 9global.BPredUnit.lookups 2256 # Number of BP lookups 10global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. 11host_inst_rate 34296 # Simulator instruction rate (inst/s) 12host_mem_usage 160076 # Number of bytes of host memory used 13host_seconds 0.16 # Real time elapsed on the host 14host_tick_rate 41824 # Simulator tick rate (ticks/s) 15memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. 16memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. 17memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. 18memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. 19sim_freq 1000000000000 # Frequency of simulated ticks 20sim_insts 5623 # Number of instructions simulated 21sim_seconds 0.000000 # Number of seconds simulated 22sim_ticks 6870 # Number of ticks simulated 23system.cpu.commit.COM:branches 862 # Number of branches committed 24system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached 25system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 26system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle.samples 6116 28system.cpu.commit.COM:committed_per_cycle.min_value 0 29 0 3908 6389.80% 30 1 1064 1739.70% 31 2 389 636.04% 32 3 210 343.36% 33 4 153 250.16% 34 5 93 152.06% 35 6 76 124.26% 36 7 149 243.62% 37 8 74 120.99% 38system.cpu.commit.COM:committed_per_cycle.max_value 8 39system.cpu.commit.COM:committed_per_cycle.end_dist 40 41system.cpu.commit.COM:count 5640 # Number of instructions committed 42system.cpu.commit.COM:loads 979 # Number of loads committed 43system.cpu.commit.COM:membars 0 # Number of memory barriers committed 44system.cpu.commit.COM:refs 1791 # Number of memory references committed 45system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 46system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted 47system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions 48system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 49system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit 50system.cpu.committedInsts 5623 # Number of Instructions Simulated 51system.cpu.committedInsts_total 5623 # Number of Instructions Simulated 52system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction 53system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads 54system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) 55system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency 56system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency 57system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits 58system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles 59system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses 60system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses 61system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits 62system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles 63system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses 64system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses 65system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) 66system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency 67system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency 68system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits 69system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles 70system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses 71system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses 72system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits 73system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles 74system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses 75system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses 76system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 77system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked 78system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. 79system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 80system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked 81system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 82system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked 83system.cpu.dcache.cache_copies 0 # number of cache copies performed 84system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses 85system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency 86system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency 87system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits 88system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles 89system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses 90system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses 91system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits 92system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles 93system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses 94system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses 95system.cpu.dcache.fast_writes 0 # number of fast writes performed 96system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 97system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 98system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses 99system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency 100system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency 101system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 102system.cpu.dcache.overall_hits 2048 # number of overall hits 103system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles 104system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses 105system.cpu.dcache.overall_misses 311 # number of overall misses 106system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits 107system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles 108system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses 109system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses 110system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 111system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 112system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 113system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 114system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 115system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 116system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 117system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 118system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 119system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 120system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 121system.cpu.dcache.replacements 0 # number of replacements 122system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. 123system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 124system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use 125system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. 126system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 127system.cpu.dcache.writebacks 0 # number of writebacks 128system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked 129system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction 130system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch 131system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode 132system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle 133system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running 134system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing 135system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode 136system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking 137system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered 138system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched 139system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked 140system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed 141system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed 142system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing 143system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle 144system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss 145system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken 146system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle 147system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) 148system.cpu.fetch.rateDist.samples 6871 149system.cpu.fetch.rateDist.min_value 0 150 0 4549 6620.58% 151 1 174 253.24% 152 2 186 270.70% 153 3 157 228.50% 154 4 211 307.09% 155 5 153 222.68% 156 6 171 248.87% 157 7 105 152.82% 158 8 1165 1695.53% 159system.cpu.fetch.rateDist.max_value 8 160system.cpu.fetch.rateDist.end_dist 161 162system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) 163system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency 164system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency 165system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits 166system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles 167system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses 168system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses 169system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits 170system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles 171system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses 172system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses 173system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 174system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 175system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. 176system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked 177system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked 178system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 179system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 180system.cpu.icache.cache_copies 0 # number of cache copies performed 181system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses 182system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency 183system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency 184system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits 185system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles 186system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses 187system.cpu.icache.demand_misses 327 # number of demand (read+write) misses 188system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits 189system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles 190system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses 191system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses 192system.cpu.icache.fast_writes 0 # number of fast writes performed 193system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 194system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 195system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses 196system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency 197system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency 198system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 199system.cpu.icache.overall_hits 1255 # number of overall hits 200system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles 201system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses 202system.cpu.icache.overall_misses 327 # number of overall misses 203system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits 204system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles 205system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses 206system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses 207system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 208system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 209system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 210system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 211system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 212system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 213system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 214system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 215system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 216system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 217system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 218system.cpu.icache.replacements 0 # number of replacements 219system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. 220system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 221system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use 222system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. 223system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 224system.cpu.icache.writebacks 0 # number of writebacks 225system.cpu.iew.EXEC:branches 1206 # Number of branches executed 226system.cpu.iew.EXEC:insts 7969 # Number of executed instructions 227system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed 228system.cpu.iew.EXEC:nop 37 # number of nop insts executed 229system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate 230system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed 231system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute 232system.cpu.iew.EXEC:stores 989 # Number of stores executed 233system.cpu.iew.EXEC:swp 0 # number of swp insts executed 234system.cpu.iew.WB:consumers 5438 # num instructions consuming a value 235system.cpu.iew.WB:count 7722 # cumulative count of insts written-back 236system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back 237system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 238system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 239system.cpu.iew.WB:producers 4049 # num instructions producing a value 240system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle 241system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit 242system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute 243system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking 244system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions 245system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions 246system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch 247system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions 248system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ 249system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 250system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 251system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 252system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing 253system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking 254system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding 255system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked 256system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores 257system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 258system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 259system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 260system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled 261system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed 262system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed 263system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations 264system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly 265system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly 266system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle 267system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads 268system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue 269system.cpu.iq.IQ:residence:(null).samples 0 270system.cpu.iq.IQ:residence:(null).min_value 0 271 0 0 272 2 0 273 4 0 274 6 0 275 8 0 276 10 0 277 12 0 278 14 0 279 16 0 280 18 0 281 20 0 282 22 0 283 24 0 284 26 0 285 28 0 286 30 0 287 32 0 288 34 0 289 36 0 290 38 0 291 40 0 292 42 0 293 44 0 294 46 0 295 48 0 296 50 0 297 52 0 298 54 0 299 56 0 300 58 0 301 60 0 302 62 0 303 64 0 304 66 0 305 68 0 306 70 0 307 72 0 308 74 0 309 76 0 310 78 0 311 80 0 312 82 0 313 84 0 314 86 0 315 88 0 316 90 0 317 92 0 318 94 0 319 96 0 320 98 0 321system.cpu.iq.IQ:residence:(null).max_value 0 322system.cpu.iq.IQ:residence:(null).end_dist 323 324system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue 325system.cpu.iq.IQ:residence:IntAlu.samples 0 326system.cpu.iq.IQ:residence:IntAlu.min_value 0 327 0 0 328 2 0 329 4 0 330 6 0 331 8 0 332 10 0 333 12 0 334 14 0 335 16 0 336 18 0 337 20 0 338 22 0 339 24 0 340 26 0 341 28 0 342 30 0 343 32 0 344 34 0 345 36 0 346 38 0 347 40 0 348 42 0 349 44 0 350 46 0 351 48 0 352 50 0 353 52 0 354 54 0 355 56 0 356 58 0 357 60 0 358 62 0 359 64 0 360 66 0 361 68 0 362 70 0 363 72 0 364 74 0 365 76 0 366 78 0 367 80 0 368 82 0 369 84 0 370 86 0 371 88 0 372 90 0 373 92 0 374 94 0 375 96 0 376 98 0 377system.cpu.iq.IQ:residence:IntAlu.max_value 0 378system.cpu.iq.IQ:residence:IntAlu.end_dist 379 380system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue 381system.cpu.iq.IQ:residence:IntMult.samples 0 382system.cpu.iq.IQ:residence:IntMult.min_value 0 383 0 0 384 2 0 385 4 0 386 6 0 387 8 0 388 10 0 389 12 0 390 14 0 391 16 0 392 18 0 393 20 0 394 22 0 395 24 0 396 26 0 397 28 0 398 30 0 399 32 0 400 34 0 401 36 0 402 38 0 403 40 0 404 42 0 405 44 0 406 46 0 407 48 0 408 50 0 409 52 0 410 54 0 411 56 0 412 58 0 413 60 0 414 62 0 415 64 0 416 66 0 417 68 0 418 70 0 419 72 0 420 74 0 421 76 0 422 78 0 423 80 0 424 82 0 425 84 0 426 86 0 427 88 0 428 90 0 429 92 0 430 94 0 431 96 0 432 98 0 433system.cpu.iq.IQ:residence:IntMult.max_value 0 434system.cpu.iq.IQ:residence:IntMult.end_dist 435 436system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue 437system.cpu.iq.IQ:residence:IntDiv.samples 0 438system.cpu.iq.IQ:residence:IntDiv.min_value 0 439 0 0 440 2 0 441 4 0 442 6 0 443 8 0 444 10 0 445 12 0 446 14 0 447 16 0 448 18 0 449 20 0 450 22 0 451 24 0 452 26 0 453 28 0 454 30 0 455 32 0 456 34 0 457 36 0 458 38 0 459 40 0 460 42 0 461 44 0 462 46 0 463 48 0 464 50 0 465 52 0 466 54 0 467 56 0 468 58 0 469 60 0 470 62 0 471 64 0 472 66 0 473 68 0 474 70 0 475 72 0 476 74 0 477 76 0 478 78 0 479 80 0 480 82 0 481 84 0 482 86 0 483 88 0 484 90 0 485 92 0 486 94 0 487 96 0 488 98 0 489system.cpu.iq.IQ:residence:IntDiv.max_value 0 490system.cpu.iq.IQ:residence:IntDiv.end_dist 491 492system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue 493system.cpu.iq.IQ:residence:FloatAdd.samples 0 494system.cpu.iq.IQ:residence:FloatAdd.min_value 0 495 0 0 496 2 0 497 4 0 498 6 0 499 8 0 500 10 0 501 12 0 502 14 0 503 16 0 504 18 0 505 20 0 506 22 0 507 24 0 508 26 0 509 28 0 510 30 0 511 32 0 512 34 0 513 36 0 514 38 0 515 40 0 516 42 0 517 44 0 518 46 0 519 48 0 520 50 0 521 52 0 522 54 0 523 56 0 524 58 0 525 60 0 526 62 0 527 64 0 528 66 0 529 68 0 530 70 0 531 72 0 532 74 0 533 76 0 534 78 0 535 80 0 536 82 0 537 84 0 538 86 0 539 88 0 540 90 0 541 92 0 542 94 0 543 96 0 544 98 0 545system.cpu.iq.IQ:residence:FloatAdd.max_value 0 546system.cpu.iq.IQ:residence:FloatAdd.end_dist 547 548system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue 549system.cpu.iq.IQ:residence:FloatCmp.samples 0 550system.cpu.iq.IQ:residence:FloatCmp.min_value 0 551 0 0 552 2 0 553 4 0 554 6 0 555 8 0 556 10 0 557 12 0 558 14 0 559 16 0 560 18 0 561 20 0 562 22 0 563 24 0 564 26 0 565 28 0 566 30 0 567 32 0 568 34 0 569 36 0 570 38 0 571 40 0 572 42 0 573 44 0 574 46 0 575 48 0 576 50 0 577 52 0 578 54 0 579 56 0 580 58 0 581 60 0 582 62 0 583 64 0 584 66 0 585 68 0 586 70 0 587 72 0 588 74 0 589 76 0 590 78 0 591 80 0 592 82 0 593 84 0 594 86 0 595 88 0 596 90 0 597 92 0 598 94 0 599 96 0 600 98 0 601system.cpu.iq.IQ:residence:FloatCmp.max_value 0 602system.cpu.iq.IQ:residence:FloatCmp.end_dist 603 604system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue 605system.cpu.iq.IQ:residence:FloatCvt.samples 0 606system.cpu.iq.IQ:residence:FloatCvt.min_value 0 607 0 0 608 2 0 609 4 0 610 6 0 611 8 0 612 10 0 613 12 0 614 14 0 615 16 0 616 18 0 617 20 0 618 22 0 619 24 0 620 26 0 621 28 0 622 30 0 623 32 0 624 34 0 625 36 0 626 38 0 627 40 0 628 42 0 629 44 0 630 46 0 631 48 0 632 50 0 633 52 0 634 54 0 635 56 0 636 58 0 637 60 0 638 62 0 639 64 0 640 66 0 641 68 0 642 70 0 643 72 0 644 74 0 645 76 0 646 78 0 647 80 0 648 82 0 649 84 0 650 86 0 651 88 0 652 90 0 653 92 0 654 94 0 655 96 0 656 98 0 657system.cpu.iq.IQ:residence:FloatCvt.max_value 0 658system.cpu.iq.IQ:residence:FloatCvt.end_dist 659 660system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue 661system.cpu.iq.IQ:residence:FloatMult.samples 0 662system.cpu.iq.IQ:residence:FloatMult.min_value 0 663 0 0 664 2 0 665 4 0 666 6 0 667 8 0 668 10 0 669 12 0 670 14 0 671 16 0 672 18 0 673 20 0 674 22 0 675 24 0 676 26 0 677 28 0 678 30 0 679 32 0 680 34 0 681 36 0 682 38 0 683 40 0 684 42 0 685 44 0 686 46 0 687 48 0 688 50 0 689 52 0 690 54 0 691 56 0 692 58 0 693 60 0 694 62 0 695 64 0 696 66 0 697 68 0 698 70 0 699 72 0 700 74 0 701 76 0 702 78 0 703 80 0 704 82 0 705 84 0 706 86 0 707 88 0 708 90 0 709 92 0 710 94 0 711 96 0 712 98 0 713system.cpu.iq.IQ:residence:FloatMult.max_value 0 714system.cpu.iq.IQ:residence:FloatMult.end_dist 715 716system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue 717system.cpu.iq.IQ:residence:FloatDiv.samples 0 718system.cpu.iq.IQ:residence:FloatDiv.min_value 0 719 0 0 720 2 0 721 4 0 722 6 0 723 8 0 724 10 0 725 12 0 726 14 0 727 16 0 728 18 0 729 20 0 730 22 0 731 24 0 732 26 0 733 28 0 734 30 0 735 32 0 736 34 0 737 36 0 738 38 0 739 40 0 740 42 0 741 44 0 742 46 0 743 48 0 744 50 0 745 52 0 746 54 0 747 56 0 748 58 0 749 60 0 750 62 0 751 64 0 752 66 0 753 68 0 754 70 0 755 72 0 756 74 0 757 76 0 758 78 0 759 80 0 760 82 0 761 84 0 762 86 0 763 88 0 764 90 0 765 92 0 766 94 0 767 96 0 768 98 0 769system.cpu.iq.IQ:residence:FloatDiv.max_value 0 770system.cpu.iq.IQ:residence:FloatDiv.end_dist 771 772system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue 773system.cpu.iq.IQ:residence:FloatSqrt.samples 0 774system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 775 0 0 776 2 0 777 4 0 778 6 0 779 8 0 780 10 0 781 12 0 782 14 0 783 16 0 784 18 0 785 20 0 786 22 0 787 24 0 788 26 0 789 28 0 790 30 0 791 32 0 792 34 0 793 36 0 794 38 0 795 40 0 796 42 0 797 44 0 798 46 0 799 48 0 800 50 0 801 52 0 802 54 0 803 56 0 804 58 0 805 60 0 806 62 0 807 64 0 808 66 0 809 68 0 810 70 0 811 72 0 812 74 0 813 76 0 814 78 0 815 80 0 816 82 0 817 84 0 818 86 0 819 88 0 820 90 0 821 92 0 822 94 0 823 96 0 824 98 0 825system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 826system.cpu.iq.IQ:residence:FloatSqrt.end_dist 827 828system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue 829system.cpu.iq.IQ:residence:MemRead.samples 0 830system.cpu.iq.IQ:residence:MemRead.min_value 0 831 0 0 832 2 0 833 4 0 834 6 0 835 8 0 836 10 0 837 12 0 838 14 0 839 16 0 840 18 0 841 20 0 842 22 0 843 24 0 844 26 0 845 28 0 846 30 0 847 32 0 848 34 0 849 36 0 850 38 0 851 40 0 852 42 0 853 44 0 854 46 0 855 48 0 856 50 0 857 52 0 858 54 0 859 56 0 860 58 0 861 60 0 862 62 0 863 64 0 864 66 0 865 68 0 866 70 0 867 72 0 868 74 0 869 76 0 870 78 0 871 80 0 872 82 0 873 84 0 874 86 0 875 88 0 876 90 0 877 92 0 878 94 0 879 96 0 880 98 0 881system.cpu.iq.IQ:residence:MemRead.max_value 0 882system.cpu.iq.IQ:residence:MemRead.end_dist 883 884system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue 885system.cpu.iq.IQ:residence:MemWrite.samples 0 886system.cpu.iq.IQ:residence:MemWrite.min_value 0 887 0 0 888 2 0 889 4 0 890 6 0 891 8 0 892 10 0 893 12 0 894 14 0 895 16 0 896 18 0 897 20 0 898 22 0 899 24 0 900 26 0 901 28 0 902 30 0 903 32 0 904 34 0 905 36 0 906 38 0 907 40 0 908 42 0 909 44 0 910 46 0 911 48 0 912 50 0 913 52 0 914 54 0 915 56 0 916 58 0 917 60 0 918 62 0 919 64 0 920 66 0 921 68 0 922 70 0 923 72 0 924 74 0 925 76 0 926 78 0 927 80 0 928 82 0 929 84 0 930 86 0 931 88 0 932 90 0 933 92 0 934 94 0 935 96 0 936 98 0 937system.cpu.iq.IQ:residence:MemWrite.max_value 0 938system.cpu.iq.IQ:residence:MemWrite.end_dist 939 940system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue 941system.cpu.iq.IQ:residence:IprAccess.samples 0 942system.cpu.iq.IQ:residence:IprAccess.min_value 0 943 0 0 944 2 0 945 4 0 946 6 0 947 8 0 948 10 0 949 12 0 950 14 0 951 16 0 952 18 0 953 20 0 954 22 0 955 24 0 956 26 0 957 28 0 958 30 0 959 32 0 960 34 0 961 36 0 962 38 0 963 40 0 964 42 0 965 44 0 966 46 0 967 48 0 968 50 0 969 52 0 970 54 0 971 56 0 972 58 0 973 60 0 974 62 0 975 64 0 976 66 0 977 68 0 978 70 0 979 72 0 980 74 0 981 76 0 982 78 0 983 80 0 984 82 0 985 84 0 986 86 0 987 88 0 988 90 0 989 92 0 990 94 0 991 96 0 992 98 0 993system.cpu.iq.IQ:residence:IprAccess.max_value 0 994system.cpu.iq.IQ:residence:IprAccess.end_dist 995 996system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue 997system.cpu.iq.IQ:residence:InstPrefetch.samples 0 998system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 999 0 0 1000 2 0 1001 4 0 1002 6 0 1003 8 0 1004 10 0 1005 12 0 1006 14 0 1007 16 0 1008 18 0 1009 20 0 1010 22 0 1011 24 0 1012 26 0 1013 28 0 1014 30 0 1015 32 0 1016 34 0 1017 36 0 1018 38 0 1019 40 0 1020 42 0 1021 44 0 1022 46 0 1023 48 0 1024 50 0 1025 52 0 1026 54 0 1027 56 0 1028 58 0 1029 60 0 1030 62 0 1031 64 0 1032 66 0 1033 68 0 1034 70 0 1035 72 0 1036 74 0 1037 76 0 1038 78 0 1039 80 0 1040 82 0 1041 84 0 1042 86 0 1043 88 0 1044 90 0 1045 92 0 1046 94 0 1047 96 0 1048 98 0 1049system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 1050system.cpu.iq.IQ:residence:InstPrefetch.end_dist 1051 1052system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue 1053system.cpu.iq.ISSUE:(null)_delay.samples 0 1054system.cpu.iq.ISSUE:(null)_delay.min_value 0 1055 0 0 1056 2 0 1057 4 0 1058 6 0 1059 8 0 1060 10 0 1061 12 0 1062 14 0 1063 16 0 1064 18 0 1065 20 0 1066 22 0 1067 24 0 1068 26 0 1069 28 0 1070 30 0 1071 32 0 1072 34 0 1073 36 0 1074 38 0 1075 40 0 1076 42 0 1077 44 0 1078 46 0 1079 48 0 1080 50 0 1081 52 0 1082 54 0 1083 56 0 1084 58 0 1085 60 0 1086 62 0 1087 64 0 1088 66 0 1089 68 0 1090 70 0 1091 72 0 1092 74 0 1093 76 0 1094 78 0 1095 80 0 1096 82 0 1097 84 0 1098 86 0 1099 88 0 1100 90 0 1101 92 0 1102 94 0 1103 96 0 1104 98 0 1105system.cpu.iq.ISSUE:(null)_delay.max_value 0 1106system.cpu.iq.ISSUE:(null)_delay.end_dist 1107 1108system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue 1109system.cpu.iq.ISSUE:IntAlu_delay.samples 0 1110system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 1111 0 0 1112 2 0 1113 4 0 1114 6 0 1115 8 0 1116 10 0 1117 12 0 1118 14 0 1119 16 0 1120 18 0 1121 20 0 1122 22 0 1123 24 0 1124 26 0 1125 28 0 1126 30 0 1127 32 0 1128 34 0 1129 36 0 1130 38 0 1131 40 0 1132 42 0 1133 44 0 1134 46 0 1135 48 0 1136 50 0 1137 52 0 1138 54 0 1139 56 0 1140 58 0 1141 60 0 1142 62 0 1143 64 0 1144 66 0 1145 68 0 1146 70 0 1147 72 0 1148 74 0 1149 76 0 1150 78 0 1151 80 0 1152 82 0 1153 84 0 1154 86 0 1155 88 0 1156 90 0 1157 92 0 1158 94 0 1159 96 0 1160 98 0 1161system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 1162system.cpu.iq.ISSUE:IntAlu_delay.end_dist 1163 1164system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue 1165system.cpu.iq.ISSUE:IntMult_delay.samples 0 1166system.cpu.iq.ISSUE:IntMult_delay.min_value 0 1167 0 0 1168 2 0 1169 4 0 1170 6 0 1171 8 0 1172 10 0 1173 12 0 1174 14 0 1175 16 0 1176 18 0 1177 20 0 1178 22 0 1179 24 0 1180 26 0 1181 28 0 1182 30 0 1183 32 0 1184 34 0 1185 36 0 1186 38 0 1187 40 0 1188 42 0 1189 44 0 1190 46 0 1191 48 0 1192 50 0 1193 52 0 1194 54 0 1195 56 0 1196 58 0 1197 60 0 1198 62 0 1199 64 0 1200 66 0 1201 68 0 1202 70 0 1203 72 0 1204 74 0 1205 76 0 1206 78 0 1207 80 0 1208 82 0 1209 84 0 1210 86 0 1211 88 0 1212 90 0 1213 92 0 1214 94 0 1215 96 0 1216 98 0 1217system.cpu.iq.ISSUE:IntMult_delay.max_value 0 1218system.cpu.iq.ISSUE:IntMult_delay.end_dist 1219 1220system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue 1221system.cpu.iq.ISSUE:IntDiv_delay.samples 0 1222system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 1223 0 0 1224 2 0 1225 4 0 1226 6 0 1227 8 0 1228 10 0 1229 12 0 1230 14 0 1231 16 0 1232 18 0 1233 20 0 1234 22 0 1235 24 0 1236 26 0 1237 28 0 1238 30 0 1239 32 0 1240 34 0 1241 36 0 1242 38 0 1243 40 0 1244 42 0 1245 44 0 1246 46 0 1247 48 0 1248 50 0 1249 52 0 1250 54 0 1251 56 0 1252 58 0 1253 60 0 1254 62 0 1255 64 0 1256 66 0 1257 68 0 1258 70 0 1259 72 0 1260 74 0 1261 76 0 1262 78 0 1263 80 0 1264 82 0 1265 84 0 1266 86 0 1267 88 0 1268 90 0 1269 92 0 1270 94 0 1271 96 0 1272 98 0 1273system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 1274system.cpu.iq.ISSUE:IntDiv_delay.end_dist 1275 1276system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue 1277system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 1278system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 1279 0 0 1280 2 0 1281 4 0 1282 6 0 1283 8 0 1284 10 0 1285 12 0 1286 14 0 1287 16 0 1288 18 0 1289 20 0 1290 22 0 1291 24 0 1292 26 0 1293 28 0 1294 30 0 1295 32 0 1296 34 0 1297 36 0 1298 38 0 1299 40 0 1300 42 0 1301 44 0 1302 46 0 1303 48 0 1304 50 0 1305 52 0 1306 54 0 1307 56 0 1308 58 0 1309 60 0 1310 62 0 1311 64 0 1312 66 0 1313 68 0 1314 70 0 1315 72 0 1316 74 0 1317 76 0 1318 78 0 1319 80 0 1320 82 0 1321 84 0 1322 86 0 1323 88 0 1324 90 0 1325 92 0 1326 94 0 1327 96 0 1328 98 0 1329system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 1330system.cpu.iq.ISSUE:FloatAdd_delay.end_dist 1331 1332system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue 1333system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 1334system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 1335 0 0 1336 2 0 1337 4 0 1338 6 0 1339 8 0 1340 10 0 1341 12 0 1342 14 0 1343 16 0 1344 18 0 1345 20 0 1346 22 0 1347 24 0 1348 26 0 1349 28 0 1350 30 0 1351 32 0 1352 34 0 1353 36 0 1354 38 0 1355 40 0 1356 42 0 1357 44 0 1358 46 0 1359 48 0 1360 50 0 1361 52 0 1362 54 0 1363 56 0 1364 58 0 1365 60 0 1366 62 0 1367 64 0 1368 66 0 1369 68 0 1370 70 0 1371 72 0 1372 74 0 1373 76 0 1374 78 0 1375 80 0 1376 82 0 1377 84 0 1378 86 0 1379 88 0 1380 90 0 1381 92 0 1382 94 0 1383 96 0 1384 98 0 1385system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 1386system.cpu.iq.ISSUE:FloatCmp_delay.end_dist 1387 1388system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue 1389system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 1390system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 1391 0 0 1392 2 0 1393 4 0 1394 6 0 1395 8 0 1396 10 0 1397 12 0 1398 14 0 1399 16 0 1400 18 0 1401 20 0 1402 22 0 1403 24 0 1404 26 0 1405 28 0 1406 30 0 1407 32 0 1408 34 0 1409 36 0 1410 38 0 1411 40 0 1412 42 0 1413 44 0 1414 46 0 1415 48 0 1416 50 0 1417 52 0 1418 54 0 1419 56 0 1420 58 0 1421 60 0 1422 62 0 1423 64 0 1424 66 0 1425 68 0 1426 70 0 1427 72 0 1428 74 0 1429 76 0 1430 78 0 1431 80 0 1432 82 0 1433 84 0 1434 86 0 1435 88 0 1436 90 0 1437 92 0 1438 94 0 1439 96 0 1440 98 0 1441system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 1442system.cpu.iq.ISSUE:FloatCvt_delay.end_dist 1443 1444system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue 1445system.cpu.iq.ISSUE:FloatMult_delay.samples 0 1446system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 1447 0 0 1448 2 0 1449 4 0 1450 6 0 1451 8 0 1452 10 0 1453 12 0 1454 14 0 1455 16 0 1456 18 0 1457 20 0 1458 22 0 1459 24 0 1460 26 0 1461 28 0 1462 30 0 1463 32 0 1464 34 0 1465 36 0 1466 38 0 1467 40 0 1468 42 0 1469 44 0 1470 46 0 1471 48 0 1472 50 0 1473 52 0 1474 54 0 1475 56 0 1476 58 0 1477 60 0 1478 62 0 1479 64 0 1480 66 0 1481 68 0 1482 70 0 1483 72 0 1484 74 0 1485 76 0 1486 78 0 1487 80 0 1488 82 0 1489 84 0 1490 86 0 1491 88 0 1492 90 0 1493 92 0 1494 94 0 1495 96 0 1496 98 0 1497system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 1498system.cpu.iq.ISSUE:FloatMult_delay.end_dist 1499 1500system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue 1501system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 1502system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 1503 0 0 1504 2 0 1505 4 0 1506 6 0 1507 8 0 1508 10 0 1509 12 0 1510 14 0 1511 16 0 1512 18 0 1513 20 0 1514 22 0 1515 24 0 1516 26 0 1517 28 0 1518 30 0 1519 32 0 1520 34 0 1521 36 0 1522 38 0 1523 40 0 1524 42 0 1525 44 0 1526 46 0 1527 48 0 1528 50 0 1529 52 0 1530 54 0 1531 56 0 1532 58 0 1533 60 0 1534 62 0 1535 64 0 1536 66 0 1537 68 0 1538 70 0 1539 72 0 1540 74 0 1541 76 0 1542 78 0 1543 80 0 1544 82 0 1545 84 0 1546 86 0 1547 88 0 1548 90 0 1549 92 0 1550 94 0 1551 96 0 1552 98 0 1553system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 1554system.cpu.iq.ISSUE:FloatDiv_delay.end_dist 1555 1556system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue 1557system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 1558system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 1559 0 0 1560 2 0 1561 4 0 1562 6 0 1563 8 0 1564 10 0 1565 12 0 1566 14 0 1567 16 0 1568 18 0 1569 20 0 1570 22 0 1571 24 0 1572 26 0 1573 28 0 1574 30 0 1575 32 0 1576 34 0 1577 36 0 1578 38 0 1579 40 0 1580 42 0 1581 44 0 1582 46 0 1583 48 0 1584 50 0 1585 52 0 1586 54 0 1587 56 0 1588 58 0 1589 60 0 1590 62 0 1591 64 0 1592 66 0 1593 68 0 1594 70 0 1595 72 0 1596 74 0 1597 76 0 1598 78 0 1599 80 0 1600 82 0 1601 84 0 1602 86 0 1603 88 0 1604 90 0 1605 92 0 1606 94 0 1607 96 0 1608 98 0 1609system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 1610system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist 1611 1612system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue 1613system.cpu.iq.ISSUE:MemRead_delay.samples 0 1614system.cpu.iq.ISSUE:MemRead_delay.min_value 0 1615 0 0 1616 2 0 1617 4 0 1618 6 0 1619 8 0 1620 10 0 1621 12 0 1622 14 0 1623 16 0 1624 18 0 1625 20 0 1626 22 0 1627 24 0 1628 26 0 1629 28 0 1630 30 0 1631 32 0 1632 34 0 1633 36 0 1634 38 0 1635 40 0 1636 42 0 1637 44 0 1638 46 0 1639 48 0 1640 50 0 1641 52 0 1642 54 0 1643 56 0 1644 58 0 1645 60 0 1646 62 0 1647 64 0 1648 66 0 1649 68 0 1650 70 0 1651 72 0 1652 74 0 1653 76 0 1654 78 0 1655 80 0 1656 82 0 1657 84 0 1658 86 0 1659 88 0 1660 90 0 1661 92 0 1662 94 0 1663 96 0 1664 98 0 1665system.cpu.iq.ISSUE:MemRead_delay.max_value 0 1666system.cpu.iq.ISSUE:MemRead_delay.end_dist 1667 1668system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue 1669system.cpu.iq.ISSUE:MemWrite_delay.samples 0 1670system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 1671 0 0 1672 2 0 1673 4 0 1674 6 0 1675 8 0 1676 10 0 1677 12 0 1678 14 0 1679 16 0 1680 18 0 1681 20 0 1682 22 0 1683 24 0 1684 26 0 1685 28 0 1686 30 0 1687 32 0 1688 34 0 1689 36 0 1690 38 0 1691 40 0 1692 42 0 1693 44 0 1694 46 0 1695 48 0 1696 50 0 1697 52 0 1698 54 0 1699 56 0 1700 58 0 1701 60 0 1702 62 0 1703 64 0 1704 66 0 1705 68 0 1706 70 0 1707 72 0 1708 74 0 1709 76 0 1710 78 0 1711 80 0 1712 82 0 1713 84 0 1714 86 0 1715 88 0 1716 90 0 1717 92 0 1718 94 0 1719 96 0 1720 98 0 1721system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 1722system.cpu.iq.ISSUE:MemWrite_delay.end_dist 1723 1724system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue 1725system.cpu.iq.ISSUE:IprAccess_delay.samples 0 1726system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 1727 0 0 1728 2 0 1729 4 0 1730 6 0 1731 8 0 1732 10 0 1733 12 0 1734 14 0 1735 16 0 1736 18 0 1737 20 0 1738 22 0 1739 24 0 1740 26 0 1741 28 0 1742 30 0 1743 32 0 1744 34 0 1745 36 0 1746 38 0 1747 40 0 1748 42 0 1749 44 0 1750 46 0 1751 48 0 1752 50 0 1753 52 0 1754 54 0 1755 56 0 1756 58 0 1757 60 0 1758 62 0 1759 64 0 1760 66 0 1761 68 0 1762 70 0 1763 72 0 1764 74 0 1765 76 0 1766 78 0 1767 80 0 1768 82 0 1769 84 0 1770 86 0 1771 88 0 1772 90 0 1773 92 0 1774 94 0 1775 96 0 1776 98 0 1777system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 1778system.cpu.iq.ISSUE:IprAccess_delay.end_dist 1779 1780system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue 1781system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 1782system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 1783 0 0 1784 2 0 1785 4 0 1786 6 0 1787 8 0 1788 10 0 1789 12 0 1790 14 0 1791 16 0 1792 18 0 1793 20 0 1794 22 0 1795 24 0 1796 26 0 1797 28 0 1798 30 0 1799 32 0 1800 34 0 1801 36 0 1802 38 0 1803 40 0 1804 42 0 1805 44 0 1806 46 0 1807 48 0 1808 50 0 1809 52 0 1810 54 0 1811 56 0 1812 58 0 1813 60 0 1814 62 0 1815 64 0 1816 66 0 1817 68 0 1818 70 0 1819 72 0 1820 74 0 1821 76 0 1822 78 0 1823 80 0 1824 82 0 1825 84 0 1826 86 0 1827 88 0 1828 90 0 1829 92 0 1830 94 0 1831 96 0 1832 98 0 1833system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 1834system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist 1835 1836system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued 1837system.cpu.iq.ISSUE:FU_type_0.start_dist 1838 (null) 2 0.02% # Type of FU issued 1839 IntAlu 5594 66.69% # Type of FU issued 1840 IntMult 1 0.01% # Type of FU issued 1841 IntDiv 0 0.00% # Type of FU issued 1842 FloatAdd 2 0.02% # Type of FU issued 1843 FloatCmp 0 0.00% # Type of FU issued 1844 FloatCvt 0 0.00% # Type of FU issued 1845 FloatMult 0 0.00% # Type of FU issued 1846 FloatDiv 0 0.00% # Type of FU issued 1847 FloatSqrt 0 0.00% # Type of FU issued 1848 MemRead 1757 20.95% # Type of FU issued 1849 MemWrite 1032 12.30% # Type of FU issued 1850 IprAccess 0 0.00% # Type of FU issued 1851 InstPrefetch 0 0.00% # Type of FU issued 1852system.cpu.iq.ISSUE:FU_type_0.end_dist 1853system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested 1854system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) 1855system.cpu.iq.ISSUE:fu_full.start_dist 1856 (null) 0 0.00% # attempts to use FU when none available 1857 IntAlu 1 0.87% # attempts to use FU when none available 1858 IntMult 0 0.00% # attempts to use FU when none available 1859 IntDiv 0 0.00% # attempts to use FU when none available 1860 FloatAdd 0 0.00% # attempts to use FU when none available 1861 FloatCmp 0 0.00% # attempts to use FU when none available 1862 FloatCvt 0 0.00% # attempts to use FU when none available 1863 FloatMult 0 0.00% # attempts to use FU when none available 1864 FloatDiv 0 0.00% # attempts to use FU when none available 1865 FloatSqrt 0 0.00% # attempts to use FU when none available 1866 MemRead 76 66.09% # attempts to use FU when none available 1867 MemWrite 38 33.04% # attempts to use FU when none available 1868 IprAccess 0 0.00% # attempts to use FU when none available 1869 InstPrefetch 0 0.00% # attempts to use FU when none available 1870system.cpu.iq.ISSUE:fu_full.end_dist 1871system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle 1872system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 1873system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 1874 0 3753 5462.09% 1875 1 894 1301.12% 1876 2 723 1052.25% 1877 3 614 893.61% 1878 4 451 656.38% 1879 5 279 406.05% 1880 6 104 151.36% 1881 7 41 59.67% 1882 8 12 17.46% 1883system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 1884system.cpu.iq.ISSUE:issued_per_cycle.end_dist 1885 1886system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate 1887system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) 1888system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued 1889system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ 1890system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling 1891system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued 1892system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed 1893system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph 1894system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) 1895system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency 1896system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency 1897system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 1898system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles 1899system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses 1900system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses 1901system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles 1902system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses 1903system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses 1904system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 1905system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 1906system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. 1907system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked 1908system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked 1909system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 1910system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked 1911system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1912system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses 1913system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency 1914system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency 1915system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 1916system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles 1917system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses 1918system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses 1919system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 1920system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles 1921system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses 1922system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses 1923system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1924system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 1925system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1926system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses 1927system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency 1928system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency 1929system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 1930system.cpu.l2cache.overall_hits 2 # number of overall hits 1931system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles 1932system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses 1933system.cpu.l2cache.overall_misses 497 # number of overall misses 1934system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 1935system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles 1936system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses 1937system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses 1938system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 1939system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1940system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 1941system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 1942system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 1943system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1944system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 1945system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1946system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 1947system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 1948system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1949system.cpu.l2cache.replacements 0 # number of replacements 1950system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. 1951system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1952system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use 1953system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 1954system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1955system.cpu.l2cache.writebacks 0 # number of writebacks 1956system.cpu.numCycles 6871 # number of cpu cycles simulated 1957system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking 1958system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed 1959system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle 1960system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full 1961system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made 1962system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename 1963system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed 1964system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running 1965system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing 1966system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking 1967system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing 1968system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst 1969system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed 1970system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer 1971system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed 1972system.cpu.workload.PROG:num_syscalls 17 # Number of system calls 1973 1974---------- End Simulation Statistics ---------- 1975